ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)

When decoding a srs instruction, invalid mode encoding returns invalid instruction.
This can happen when garbage instructions are fetched from mispredicted path
This commit is contained in:
Min Kyu Jeong 2010-08-25 19:10:43 -05:00
parent edca5f7da6
commit e1168e72ca
7 changed files with 28 additions and 6 deletions

View file

@ -101,7 +101,8 @@ enum DependenceTags {
// 0..31 are the integer regs 0..31 // 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 40, FP_Base_DepTag = 40,
Ctrl_Base_DepTag = 72 Ctrl_Base_DepTag = 72,
Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs
}; };
} // namespace AlphaISA } // namespace AlphaISA

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@ -1,4 +1,16 @@
/* /*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2007-2008 The Florida State University * Copyright (c) 2007-2008 The Florida State University
* All rights reserved. * All rights reserved.
* *
@ -59,9 +71,9 @@ const int NumFloatSpecialRegs = 8;
const int NumIntRegs = NUM_INTREGS; const int NumIntRegs = NUM_INTREGS;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
const int NumMiscRegs = NUM_MISCREGS; const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
// semantically meaningful register indices // semantically meaningful register indices
const int ReturnValueReg = 0; const int ReturnValueReg = 0;
@ -85,6 +97,7 @@ const int SyscallSuccessReg = ReturnValueReg;
// These help enumerate all the registers for dependence tracking. // These help enumerate all the registers for dependence tracking.
const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1); const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
typedef union { typedef union {
IntReg intreg; IntReg intreg;

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@ -283,6 +283,7 @@ enum MiscRegIndex{
const int TotalDataRegs = NumIntRegs + NumFloatRegs; const int TotalDataRegs = NumIntRegs + NumFloatRegs;
const int NumMiscRegs = MISCREG_NUMREGS; const int NumMiscRegs = MISCREG_NUMREGS;
const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;

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@ -82,6 +82,7 @@ const int SyscallSuccessReg = 3;
// These help enumerate all the registers for dependence tracking. // These help enumerate all the registers for dependence tracking.
const int FP_Base_DepTag = NumIntRegs; const int FP_Base_DepTag = NumIntRegs;
const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
typedef union { typedef union {
IntReg intreg; IntReg intreg;

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@ -58,7 +58,8 @@ namespace SparcISA
// These enumerate all the registers for dependence tracking. // These enumerate all the registers for dependence tracking.
enum DependenceTags { enum DependenceTags {
FP_Base_DepTag = 32*3+9, FP_Base_DepTag = 32*3+9,
Ctrl_Base_DepTag = FP_Base_DepTag + 64 Ctrl_Base_DepTag = FP_Base_DepTag + 64,
Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
}; };
// semantically meaningful register indices // semantically meaningful register indices

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@ -76,7 +76,8 @@ enum DependenceTags {
//The microcode fp registers //The microcode fp registers
8 + 8 +
//The indices that are mapped over the fp stack //The indices that are mapped over the fp stack
8 8,
Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
}; };
// semantically meaningful register indices // semantically meaningful register indices

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@ -966,9 +966,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
src_reg = src_reg - TheISA::FP_Base_DepTag; src_reg = src_reg - TheISA::FP_Base_DepTag;
flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
flat_src_reg += TheISA::NumIntRegs; flat_src_reg += TheISA::NumIntRegs;
} else { } else if (src_reg < TheISA::Max_DepTag) {
flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
} else {
panic("Reg index is out of bound: %d.", src_reg);
} }
inst->flattenSrcReg(src_idx, flat_src_reg); inst->flattenSrcReg(src_idx, flat_src_reg);
@ -1012,11 +1014,13 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
// Integer registers are flattened. // Integer registers are flattened.
flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
} else { } else if (dest_reg < TheISA::Max_DepTag) {
// Floating point and Miscellaneous registers need their indexes // Floating point and Miscellaneous registers need their indexes
// adjusted to account for the expanded number of flattened int regs. // adjusted to account for the expanded number of flattened int regs.
flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
} else {
panic("Reg index is out of bound: %d.", dest_reg);
} }
inst->flattenDestReg(dest_idx, flat_dest_reg); inst->flattenDestReg(dest_idx, flat_dest_reg);