Simple CPU: Make sure only instructions which complete without faulting are counted.
--HG-- extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
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4 changed files with 27 additions and 6 deletions
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@ -546,6 +546,11 @@ AtomicSimpleCPU::tick()
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if(curStaticInst)
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{
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fault = curStaticInst->execute(this, traceData);
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// keep an instruction count
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if (fault == NoFault)
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countInst();
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postExecute();
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}
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@ -357,12 +357,6 @@ BaseSimpleCPU::preExecute()
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thread->setFloatReg(ZeroReg, 0.0);
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#endif // ALPHA_ISA
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// keep an instruction count
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numInst++;
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numInsts++;
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thread->funcExeInst++;
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// check for instruction-count-based events
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comInstEventQueue[0]->serviceEvents(numInst);
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@ -157,6 +157,14 @@ class BaseSimpleCPU : public BaseCPU
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Counter startNumInst;
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Stats::Scalar<> numInsts;
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void countInst()
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{
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numInst++;
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numInsts++;
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thread->funcExeInst++;
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}
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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@ -540,13 +540,23 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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delete dcache_pkt->req;
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delete dcache_pkt;
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dcache_pkt = NULL;
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// keep an instruction count
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if (fault == NoFault)
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countInst();
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}
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postExecute();
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advanceInst(fault);
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}
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} else {
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// non-memory instruction: execute completely now
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Fault fault = curStaticInst->execute(this, traceData);
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// keep an instruction count
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if (fault == NoFault)
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countInst();
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postExecute();
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advanceInst(fault);
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}
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@ -615,6 +625,10 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
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Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
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// keep an instruction count
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if (fault == NoFault)
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countInst();
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if (pkt->isRead() && pkt->isLocked()) {
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TheISA::handleLockedRead(thread, pkt->req);
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}
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