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Fix compiler errors.

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--HG--
extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
This commit is contained in:
Gabe Black 2007-06-20 19:46:45 -07:00
parent 5c48a05813
commit df7730b677
3 changed files with 18 additions and 19 deletions
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8
src/cpu/base_dyn_inst.hh
View file

@ -498,11 +498,11 @@ class BaseDynInst : public FastAlloc, public RefCounted
bool isQuiesce() const { return staticInst->isQuiesce(); } bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); } bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); } bool isUnverifiable() const { return staticInst->isUnverifiable(); }
bool isMacroOp() const { return staticInst->isMacroOp(); } bool isMacroop() const { return staticInst->isMacroop(); }
bool isMicroOp() const { return staticInst->isMicroOp(); } bool isMicroop() const { return staticInst->isMicroop(); }
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
bool isLastMicroOp() const { return staticInst->isLastMicroOp(); } bool isLastMicroop() const { return staticInst->isLastMicroop(); }
bool isFirstMicroOp() const { return staticInst->isFirstMicroOp(); } bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
bool isMicroBranch() const { return staticInst->isMicroBranch(); } bool isMicroBranch() const { return staticInst->isMicroBranch(); }
/** Temporarily sets this instruction as a serialize before instruction. */ /** Temporarily sets this instruction as a serialize before instruction. */

6
src/cpu/base_dyn_inst_impl.hh
View file

@ -73,7 +73,7 @@ BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
seqNum = seq_num; seqNum = seq_num;
bool nextIsMicro = bool nextIsMicro =
staticInst->isMicroOp() && !staticInst->isLastMicroOp(); staticInst->isMicroop() && !staticInst->isLastMicroop();
PC = inst_PC; PC = inst_PC;
microPC = inst_MicroPC; microPC = inst_MicroPC;
@ -101,12 +101,12 @@ BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
Addr pred_PC, Addr pred_NPC, Addr pred_PC, Addr pred_NPC,
Addr pred_MicroPC, Addr pred_MicroPC,
InstSeqNum seq_num, ImplCPU *cpu) InstSeqNum seq_num, ImplCPU *cpu)
: staticInst(inst), traceData(NULL), cpu(cpu) : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
{ {
seqNum = seq_num; seqNum = seq_num;
bool nextIsMicro = bool nextIsMicro =
staticInst->isMicroOp() && !staticInst->isLastMicroOp(); staticInst->isMicroop() && !staticInst->isLastMicroop();
PC = inst_PC; PC = inst_PC;
microPC = inst_MicroPC; microPC = inst_MicroPC;

23
src/cpu/o3/fetch_impl.hh
View file

@ -498,7 +498,7 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
bool predict_taken; bool predict_taken;
if (!inst->isControl()) { if (!inst->isControl()) {
if (inst->isMicroOp() && !inst->isLastMicroOp()) { if (inst->isMicroop() && !inst->isLastMicroop()) {
next_MicroPC++; next_MicroPC++;
} else { } else {
next_PC = next_NPC; next_PC = next_NPC;
@ -1120,14 +1120,14 @@ DefaultFetch<Impl>::fetch(bool &status_change)
predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
ext_inst = predecoder.getExtMachInst(); ext_inst = predecoder.getExtMachInst();
staticInst = StaticInstPtr(ext_inst); staticInst = StaticInstPtr(ext_inst, fetch_PC);
if (staticInst->isMacroOp()) if (staticInst->isMacroop())
macroop = staticInst; macroop = staticInst;
} }
do { do {
if (macroop) { if (macroop) {
staticInst = macroop->fetchMicroOp(fetch_MicroPC); staticInst = macroop->fetchMicroop(fetch_MicroPC);
if (staticInst->isLastMicroOp()) if (staticInst->isLastMicroop())
macroop = NULL; macroop = NULL;
} }
@ -1194,8 +1194,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
} }
++numInst; ++numInst;
} while (staticInst->isMicroOp() && } while (staticInst->isMicroop() &&
!staticInst->isLastMicroOp() && !staticInst->isLastMicroop() &&
numInst < fetchWidth); numInst < fetchWidth);
offset += instSize; offset += instSize;
} }
@ -1240,13 +1240,12 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// We will use a nop in order to carry the fault. // We will use a nop in order to carry the fault.
ext_inst = TheISA::NoopMachInst; ext_inst = TheISA::NoopMachInst;
StaticInstPtr staticInst = new StaticInst(ext_inst);
// Create a new DynInst from the dummy nop. // Create a new DynInst from the dummy nop.
DynInstPtr instruction = new DynInst(staticInst, DynInstPtr instruction = new DynInst(ext_inst,
fetch_PC, fetch_NPC, fetch_PC, fetch_NPC, fetch_MicroPC,
next_PC, next_NPC, next_PC, next_NPC, next_MicroPC,
inst_seq, cpu); inst_seq, cpu);
instruction->setPredTarg(next_PC, next_NPC); instruction->setPredTarg(next_PC, next_NPC, 1);
instruction->setTid(tid); instruction->setTid(tid);
instruction->setASID(tid); instruction->setASID(tid);