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Minor regression fixes.

Browse source 
src/python/m5/objects/BaseCPU.py:
    bug fix
tests/SConscript:
    fix up diff ignore strings to reflect changes
    in m5 output

--HG--
extra : convert_revision : b8e4acee34599ddd431b69fc9d40b6f6e440d128
This commit is contained in:
Steve Reinhardt 2006-08-16 14:16:52 -07:00
parent 597ef651df
commit df3af8018e
2 changed files with 4 additions and 3 deletions
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2
src/python/m5/objects/BaseCPU.py
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@ -49,5 +49,5 @@ class BaseCPU(SimObject):
self.toL2Bus = Bus() self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus) self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c self.l2cache = l2c
self.l2cache.cpu_side = toL2Bus.port self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side'] self._mem_ports = ['l2cache.mem_side']

5
tests/SConscript
View file

@ -61,8 +61,9 @@ def check_test(target, source, env):
# Exclude m5stats.txt since we will use diff-out on that. # Exclude m5stats.txt since we will use diff-out on that.
Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
'-I "^command line:" ' + # for stdout file '-I "^command line:" ' + # for stdout file
'-I "^M5 compiled on" ' + # for stderr file '-I "^M5 compiled " ' + # for stderr file
'-I "^M5 simulation started" ' + # for stderr file '-I "^M5 started " ' + # for stderr file
'-I "^M5 executing on " ' + # for stderr file
'-I "^Simulation complete at" ' + # for stderr file '-I "^Simulation complete at" ' + # for stderr file
'-I "^Listening for" ' + # for stderr file '-I "^Listening for" ' + # for stderr file
'--exclude=m5stats.txt --exclude=SCCS ' + '--exclude=m5stats.txt --exclude=SCCS ' +