Fix the packet data allocation methods. Small fixes from changesets after my initial work.
This now compiles. src/mem/cache/base_cache.cc: Fix getPort function that changed src/mem/cache/base_cache.hh: Fix get port function, provide default implementations of virtual functions in the base class src/mem/cache/cache.hh: Fix virtual function declerations src/mem/cache/cache_builder.cc: Fix params src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: Properly allocate data in packet --HG-- extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48
This commit is contained in:
parent
971bb55369
commit
dea1a19b2d
11 changed files with 39 additions and 26 deletions
2
src/mem/cache/base_cache.cc
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2
src/mem/cache/base_cache.cc
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@ -99,7 +99,7 @@ BaseCache::CachePort::clearBlocked()
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}
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}
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Port*
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Port*
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BaseCache::getPort(const std::string &if_name)
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BaseCache::getPort(const std::string &if_name, int idx)
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{
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{
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if(if_name == "cpu_side")
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if(if_name == "cpu_side")
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{
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{
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26
src/mem/cache/base_cache.hh
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26
src/mem/cache/base_cache.hh
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@ -41,6 +41,7 @@
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#include <list>
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#include <list>
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#include <inttypes.h>
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#include <inttypes.h>
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "base/statistics.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "mem/mem_object.hh"
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#include "mem/mem_object.hh"
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@ -122,14 +123,29 @@ class BaseCache : public MemObject
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CachePort *memSidePort;
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CachePort *memSidePort;
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public:
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public:
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virtual Port *getPort(const std::string &if_name);
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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private:
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private:
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//To be defined in cache_impl.hh not in base class
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//To be defined in cache_impl.hh not in base class
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virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide);
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virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
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virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
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{
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virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
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fatal("No implementation");
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virtual void recvStatusChange(Port::Status status, bool isCpuSide);
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}
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virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
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{
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fatal("No implementation");
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}
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virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
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{
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fatal("No implementation");
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}
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virtual void recvStatusChange(Port::Status status, bool isCpuSide)
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{
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fatal("No implementation");
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}
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/**
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/**
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* Bit vector of the blocking reasons for the access path.
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* Bit vector of the blocking reasons for the access path.
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8
src/mem/cache/cache.hh
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8
src/mem/cache/cache.hh
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@ -146,16 +146,16 @@ class Cache : public BaseCache
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/** Instantiates a basic cache object. */
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/** Instantiates a basic cache object. */
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Cache(const std::string &_name, Params ¶ms);
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Cache(const std::string &_name, Params ¶ms);
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bool doTimingAccess(Packet *pkt, CachePort *cachePort,
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virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
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bool isCpuSide);
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bool isCpuSide);
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Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
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virtual Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
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bool isCpuSide);
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bool isCpuSide);
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void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
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virtual void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
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bool isCpuSide);
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bool isCpuSide);
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void recvStatusChange(Port::Status status, bool isCpuSide);
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virtual void recvStatusChange(Port::Status status, bool isCpuSide);
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void regStats();
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void regStats();
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4
src/mem/cache/cache_builder.cc
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4
src/mem/cache/cache_builder.cc
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@ -230,7 +230,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
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Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
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Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
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do_copy, base_params, \
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do_copy, base_params, \
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/*in_bus, out_bus,*/ pf, \
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/*in_bus, out_bus,*/ pf, \
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prefetch_access); \
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prefetch_access, hit_latency); \
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Cache<CacheTags<t, comp>, b, c> *retval = \
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Cache<CacheTags<t, comp>, b, c> *retval = \
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new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
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new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
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params); \
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params); \
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@ -242,7 +242,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
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retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
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retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
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out_bus->rangeChange(); \
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out_bus->rangeChange(); \
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return retval; \
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return retval; \
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*/return true; \
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*/return retval; \
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} while (0)
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} while (0)
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#define BUILD_CACHE_PANIC(x) do { \
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#define BUILD_CACHE_PANIC(x) do { \
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3
src/mem/cache/cache_impl.hh
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3
src/mem/cache/cache_impl.hh
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@ -588,8 +588,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
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Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
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Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
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uint8_t* temp_data = new uint8_t[blkSize];
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busPkt->allocate();
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busPkt->dataDynamicArray<uint8_t>(temp_data);
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busPkt->time = curTick;
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busPkt->time = curTick;
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3
src/mem/cache/miss/blocking_buffer.cc
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3
src/mem/cache/miss/blocking_buffer.cc
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@ -210,8 +210,7 @@ BlockingBuffer::doWriteback(Addr addr, int asid,
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// Generate request
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// Generate request
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Request * req = new Request(addr, size, 0);
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Request * req = new Request(addr, size, 0);
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Packet * pkt = new Packet(req, Packet::Writeback, -1);
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Packet * pkt = new Packet(req, Packet::Writeback, -1);
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uint8_t *new_data = new uint8_t[size];
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pkt->allocate();
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pkt->dataDynamicArray<uint8_t>(new_data);
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if (data) {
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if (data) {
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memcpy(pkt->getPtr<uint8_t>(), data, size);
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memcpy(pkt->getPtr<uint8_t>(), data, size);
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}
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}
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3
src/mem/cache/miss/miss_queue.cc
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3
src/mem/cache/miss/miss_queue.cc
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@ -714,8 +714,7 @@ MissQueue::doWriteback(Addr addr, int asid,
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// Generate request
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// Generate request
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Request * req = new Request(addr, size, 0);
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Request * req = new Request(addr, size, 0);
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Packet * pkt = new Packet(req, Packet::Writeback, -1);
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Packet * pkt = new Packet(req, Packet::Writeback, -1);
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uint8_t *new_data = new uint8_t[size];
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pkt->allocate();
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pkt->dataDynamicArray<uint8_t>(new_data);
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if (data) {
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if (data) {
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memcpy(pkt->getPtr<uint8_t>(), data, size);
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memcpy(pkt->getPtr<uint8_t>(), data, size);
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}
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}
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3
src/mem/cache/miss/mshr.cc
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3
src/mem/cache/miss/mshr.cc
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@ -90,8 +90,7 @@ MSHR::allocateAsBuffer(Packet * &target)
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asid = target->req->getAsid();
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asid = target->req->getAsid();
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threadNum = target->req->getThreadNum();
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threadNum = target->req->getThreadNum();
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pkt = new Packet(target->req, target->cmd, -1);
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pkt = new Packet(target->req, target->cmd, -1);
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uint8_t *new_data = new uint8_t[target->getSize()];
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pkt->allocate();
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pkt->dataDynamicArray<uint8_t>(new_data);
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pkt->senderState = (Packet::SenderState*)this;
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pkt->senderState = (Packet::SenderState*)this;
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pkt->time = curTick;
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pkt->time = curTick;
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}
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}
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3
src/mem/cache/prefetch/base_prefetcher.cc
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3
src/mem/cache/prefetch/base_prefetcher.cc
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@ -181,8 +181,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
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Request * prefetchReq = new Request(*addr, blkSize, 0);
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Request * prefetchReq = new Request(*addr, blkSize, 0);
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Packet * prefetch;
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Packet * prefetch;
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prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
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prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
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uint8_t *new_data = new uint8_t[blkSize];
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prefetch->allocate();
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prefetch->dataDynamicArray<uint8_t>(new_data);
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prefetch->req->setThreadContext(pkt->req->getCpuNum(),
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prefetch->req->setThreadContext(pkt->req->getCpuNum(),
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pkt->req->getThreadNum());
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pkt->req->getThreadNum());
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7
src/mem/cache/tags/iic.cc
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7
src/mem/cache/tags/iic.cc
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@ -430,10 +430,11 @@ IIC::freeReplacementBlock(PacketList & writebacks)
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tag_ptr->data,
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tag_ptr->data,
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tag_ptr->size);
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tag_ptr->size);
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*/
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*/
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Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
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Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
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blkSize, 0);
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blkSize, 0);
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Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
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Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
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writeback->dataDynamic<uint8_t>(tag_ptr->data);
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writeback->allocate();
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memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);
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writebacks.push_back(writeback);
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writebacks.push_back(writeback);
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}
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}
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3
src/mem/cache/tags/lru.cc
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3
src/mem/cache/tags/lru.cc
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@ -280,7 +280,8 @@ LRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
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dest_blk->set),
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dest_blk->set),
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blkSize, 0);
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blkSize, 0);
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Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
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Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
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writeback->dataDynamic<uint8_t>(dest_blk->data);
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writeback->allocate();
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memcpy(writeback->getPtr<uint8_t>(),dest_blk->data, blkSize);
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writebacks.push_back(writeback);
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writebacks.push_back(writeback);
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}
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}
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dest_blk->tag = extractTag(dest);
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dest_blk->tag = extractTag(dest);
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