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x86: Fix the flag handling code in FABS and FCHS

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This changeset fixes two problems in the FABS and FCHS
implementation. First, the ISA parser expects the assignment in
flag_code to be a pure assignment and not an and-assignment, which
leads to the isa_parser omitting the misc reg update. Second, the FCHS
and FABS macro-ops don't set the SetStatus flag, which means that the
default micro-op version, which doesn't update FSW, is executed.
This commit is contained in:
Andreas Sandberg 2013-06-18 16:10:21 +02:00
parent 59befdb628
commit de89e133d8
2 changed files with 4 additions and 4 deletions
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4
src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
View file

@ -38,10 +38,10 @@
microcode = ''' microcode = '''
def macroop FABS { def macroop FABS {
absfp st(0), st(0) absfp st(0), st(0), SetStatus=True
}; };
def macroop FCHS { def macroop FCHS {
chsfp st(0), st(0) chsfp st(0), st(0), SetStatus=True
}; };
''' '''

4
src/arch/x86/isa/microops/fpop.isa
View file

@ -365,9 +365,9 @@ let {{
class absfp(FpUnaryOp): class absfp(FpUnaryOp):
code = 'FpDestReg = fabs(FpSrcReg1);' code = 'FpDestReg = fabs(FpSrcReg1);'
flag_code = 'FSW &= (~CC1Bit);' flag_code = 'FSW = FSW & (~CC1Bit);'
class chsfp(FpUnaryOp): class chsfp(FpUnaryOp):
code = 'FpDestReg = (-1) * (FpSrcReg1);' code = 'FpDestReg = (-1) * (FpSrcReg1);'
flag_code = 'FSW &= (~CC1Bit);' flag_code = 'FSW = FSW & (~CC1Bit);'
}}; }};