sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

SE/FS: Get rid of FULL_SYSTEM in the CPU directory.

Browse source
This commit is contained in:
Gabe Black 2011-11-18 01:33:28 -08:00
parent ec32d85f9d
commit de21bb93ea
56 changed files with 488 additions and 777 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/cpu/BaseCPU.py
View file

@ -81,8 +81,7 @@ class BaseCPU(MemObject):
profile = Param.Latency('0ns', "trace the kernel stack") profile = Param.Latency('0ns', "trace the kernel stack")
do_quiesce = Param.Bool(True, "enable quiesce instructions") do_quiesce = Param.Bool(True, "enable quiesce instructions")
if not buildEnv['FULL_SYSTEM']: workload = VectorParam.Process([], "processes to run")
workload = VectorParam.Process("processes to run")
if buildEnv['TARGET_ISA'] == 'sparc': if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB") dtb = Param.SparcTLB(SparcTLB(), "Data TLB")

7
src/cpu/SConscript
View file

@ -129,10 +129,9 @@ Source('simple_thread.cc')
Source('thread_context.cc') Source('thread_context.cc')
Source('thread_state.cc') Source('thread_state.cc')
if env['FULL_SYSTEM']: if env['TARGET_ISA'] == 'sparc':
if env['TARGET_ISA'] == 'sparc': SimObject('LegionTrace.py')
SimObject('LegionTrace.py') Source('legiontrace.cc')
Source('legiontrace.cc')
if env['USE_CHECKER']: if env['USE_CHECKER']:
Source('checker/cpu.cc') Source('checker/cpu.cc')

2
src/cpu/base.cc
View file

@ -199,11 +199,9 @@ BaseCPU::BaseCPU(Params *p)
interrupts->setCPU(this); interrupts->setCPU(this);
if (FullSystem) { if (FullSystem) {
#if FULL_SYSTEM
profileEvent = NULL; profileEvent = NULL;
if (params()->profile) if (params()->profile)
profileEvent = new ProfileEvent(this, params()->profile); profileEvent = new ProfileEvent(this, params()->profile);
#endif
} }
tracer = params()->tracer; tracer = params()->tracer;
} }

2
src/cpu/base.hh
View file

@ -158,7 +158,7 @@ class BaseCPU : public MemObject
bool bool
checkInterrupts(ThreadContext *tc) const checkInterrupts(ThreadContext *tc) const
{ {
return interrupts->checkInterrupts(tc); return FullSystem && interrupts->checkInterrupts(tc);
} }
class ProfileEvent : public Event class ProfileEvent : public Event

14
src/cpu/checker/cpu.cc
View file

@ -31,17 +31,14 @@
#include <list> #include <list>
#include <string> #include <string>
#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#include "cpu/checker/cpu.hh" #include "cpu/checker/cpu.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/simple_thread.hh" #include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#endif // FULL_SYSTEM
using namespace std; using namespace std;
//The CheckerCPU does alpha only //The CheckerCPU does alpha only
using namespace AlphaISA; using namespace AlphaISA;
@ -66,17 +63,14 @@ CheckerCPU::CheckerCPU(Params *p)
exitOnError = p->exitOnError; exitOnError = p->exitOnError;
warnOnlyOnLoadError = p->warnOnlyOnLoadError; warnOnlyOnLoadError = p->warnOnlyOnLoadError;
#if FULL_SYSTEM
itb = p->itb; itb = p->itb;
dtb = p->dtb; dtb = p->dtb;
systemPtr = NULL; systemPtr = NULL;
#else
process = p->process; process = p->process;
thread = new SimpleThread(this, /* thread_num */ 0, process); thread = new SimpleThread(this, /* thread_num */ 0, process);
tc = thread->getTC(); tc = thread->getTC();
threadContexts.push_back(tc); threadContexts.push_back(tc);
#endif
result.integer = 0; result.integer = 0;
} }
@ -88,7 +82,6 @@ CheckerCPU::~CheckerCPU()
void void
CheckerCPU::setSystem(System *system) CheckerCPU::setSystem(System *system)
{ {
#if FULL_SYSTEM
systemPtr = system; systemPtr = system;
thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false); thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
@ -97,7 +90,6 @@ CheckerCPU::setSystem(System *system)
threadContexts.push_back(tc); threadContexts.push_back(tc);
delete thread->kernelStats; delete thread->kernelStats;
thread->kernelStats = NULL; thread->kernelStats = NULL;
#endif
} }
void void
@ -301,13 +293,11 @@ CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
} }
#if FULL_SYSTEM
Addr Addr
CheckerCPU::dbg_vtophys(Addr addr) CheckerCPU::dbg_vtophys(Addr addr)
{ {
return vtophys(tc, addr); return vtophys(tc, addr);
} }
#endif // FULL_SYSTEM
bool bool
CheckerCPU::checkFlags(Request *req) CheckerCPU::checkFlags(Request *req)

20
src/cpu/checker/cpu.hh
View file

@ -46,25 +46,20 @@
#include "sim/eventq.hh" #include "sim/eventq.hh"
// forward declarations // forward declarations
#if FULL_SYSTEM
namespace TheISA namespace TheISA
{ {
class TLB; class TLB;
} }
class Processor;
class PhysicalMemory;
#else
class Process;
#endif // FULL_SYSTEM
template <class> template <class>
class BaseDynInst; class BaseDynInst;
class CheckerCPUParams; class CheckerCPUParams;
class ThreadContext;
class MemInterface;
class Checkpoint; class Checkpoint;
class MemInterface;
class PhysicalMemory;
class Process;
class Processor;
class ThreadContext;
class Request; class Request;
/** /**
@ -129,9 +124,7 @@ class CheckerCPU : public BaseCPU
TheISA::TLB *itb; TheISA::TLB *itb;
TheISA::TLB *dtb; TheISA::TLB *dtb;
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr); Addr dbg_vtophys(Addr addr);
#endif
union Result { union Result {
uint64_t integer; uint64_t integer;
@ -273,14 +266,11 @@ class CheckerCPU : public BaseCPU
this->dtb->demapPage(vaddr, asn); this->dtb->demapPage(vaddr, asn);
} }
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); } Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
// Assume that the normal CPU's call to syscall was successful. // Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall. // The checker's state would have already been updated by the syscall.
void syscall(uint64_t callnum) { } void syscall(uint64_t callnum) { }
#endif
void handleError() void handleError()
{ {

46
src/cpu/checker/cpu_impl.hh
View file

@ -31,6 +31,7 @@
#include <list> #include <list>
#include <string> #include <string>
#include "arch/vtophys.hh"
#include "base/refcnt.hh" #include "base/refcnt.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "cpu/checker/cpu.hh" #include "cpu/checker/cpu.hh"
@ -38,13 +39,10 @@
#include "cpu/simple_thread.hh" #include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "sim/full_system.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "sim/stats.hh" #include "sim/stats.hh"
#if FULL_SYSTEM
#include "arch/vtophys.hh"
#endif // FULL_SYSTEM
using namespace std; using namespace std;
//The CheckerCPU does alpha only //The CheckerCPU does alpha only
using namespace AlphaISA; using namespace AlphaISA;
@ -141,11 +139,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
// Try to fetch the instruction // Try to fetch the instruction
#if FULL_SYSTEM #define IFETCH_FLAGS(pc) (FullSystem ? 0 : ((pc) & 1) ? PHYSICAL : 0)
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
#else
#define IFETCH_FLAGS(pc) 0
#endif
uint64_t fetch_PC = thread->readPC() & ~3; uint64_t fetch_PC = thread->readPC() & ~3;
@ -235,12 +229,10 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
} }
if (fault != NoFault) { if (fault != NoFault) {
#if FULL_SYSTEM
fault->invoke(tc, curStaticInst); fault->invoke(tc, curStaticInst);
willChangePC = true; willChangePC = true;
newPC = thread->readPC(); newPC = thread->readPC();
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC); DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
#endif
} else { } else {
#if THE_ISA != MIPS_ISA #if THE_ISA != MIPS_ISA
// go to the next instruction // go to the next instruction
@ -255,23 +247,23 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
} }
#if FULL_SYSTEM if (FullSystem) {
// @todo: Determine if these should happen only if the // @todo: Determine if these should happen only if the
// instruction hasn't faulted. In the SimpleCPU case this may // instruction hasn't faulted. In the SimpleCPU case this may
// not be true, but in the O3 or Ozone case this may be true. // not be true, but in the O3 or Ozone case this may be true.
Addr oldpc; Addr oldpc;
int count = 0; int count = 0;
do { do {
oldpc = thread->readPC(); oldpc = thread->readPC();
system->pcEventQueue.service(tc); system->pcEventQueue.service(tc);
count++; count++;
} while (oldpc != thread->readPC()); } while (oldpc != thread->readPC());
if (count > 1) { if (count > 1) {
willChangePC = true; willChangePC = true;
newPC = thread->readPC(); newPC = thread->readPC();
DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC); DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
}
} }
#endif
// @todo: Optionally can check all registers. (Or just those // @todo: Optionally can check all registers. (Or just those
// that have been modified). // that have been modified).

9
src/cpu/checker/thread_context.hh
View file

@ -89,14 +89,13 @@ class CheckerThreadContext : public ThreadContext
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); } System *getSystemPtr() { return actualTC->getSystemPtr(); }
PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
TheISA::Kernel::Statistics *getKernelStats() TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); } { return actualTC->getKernelStats(); }
#endif
Process *getProcessPtr() { return actualTC->getProcessPtr(); } Process *getProcessPtr() { return actualTC->getProcessPtr(); }
TranslatingPort *getMemPort() { return actualTC->getMemPort(); } TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
@ -124,9 +123,7 @@ class CheckerThreadContext : public ThreadContext
/// Set the status to Halted. /// Set the status to Halted.
void halt() { actualTC->halt(); } void halt() { actualTC->halt(); }
#if FULL_SYSTEM
void dumpFuncProfile() { actualTC->dumpFuncProfile(); } void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
#endif
void takeOverFrom(ThreadContext *oldContext) void takeOverFrom(ThreadContext *oldContext)
{ {
@ -140,7 +137,6 @@ class CheckerThreadContext : public ThreadContext
void unserialize(Checkpoint *cp, const std::string &section) void unserialize(Checkpoint *cp, const std::string &section)
{ actualTC->unserialize(cp, section); } { actualTC->unserialize(cp, section); }
#if FULL_SYSTEM
EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
Tick readLastActivate() { return actualTC->readLastActivate(); } Tick readLastActivate() { return actualTC->readLastActivate(); }
@ -148,7 +144,6 @@ class CheckerThreadContext : public ThreadContext
void profileClear() { return actualTC->profileClear(); } void profileClear() { return actualTC->profileClear(); }
void profileSample() { return actualTC->profileSample(); } void profileSample() { return actualTC->profileSample(); }
#endif
int threadId() { return actualTC->threadId(); } int threadId() { return actualTC->threadId(); }
@ -252,9 +247,7 @@ class CheckerThreadContext : public ThreadContext
// @todo: Fix this! // @todo: Fix this!
bool misspeculating() { return actualTC->misspeculating(); } bool misspeculating() { return actualTC->misspeculating(); }
#if !FULL_SYSTEM
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
}; };
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__

5
src/cpu/exetrace.cc
View file

@ -83,10 +83,7 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
std::string sym_str; std::string sym_str;
Addr sym_addr; Addr sym_addr;
Addr cur_pc = pc.instAddr(); Addr cur_pc = pc.instAddr();
if (debugSymbolTable && Debug::ExecSymbol if (debugSymbolTable && Debug::ExecSymbol && !inUserMode(thread)
#if FULL_SYSTEM
&& !inUserMode(thread)
#endif
&& debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
if (cur_pc != sym_addr) if (cur_pc != sym_addr)
sym_str += csprintf("+%d",cur_pc - sym_addr); sym_str += csprintf("+%d",cur_pc - sym_addr);

128
src/cpu/inorder/cpu.cc
View file

@ -33,7 +33,6 @@
#include "arch/utility.hh" #include "arch/utility.hh"
#include "base/bigint.hh" #include "base/bigint.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "cpu/inorder/resources/resource_list.hh" #include "cpu/inorder/resources/resource_list.hh"
#include "cpu/inorder/cpu.hh" #include "cpu/inorder/cpu.hh"
@ -51,11 +50,13 @@
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "debug/Activity.hh" #include "debug/Activity.hh"
#include "debug/InOrderCPU.hh" #include "debug/InOrderCPU.hh"
#include "debug/Interrupt.hh"
#include "debug/RefCount.hh" #include "debug/RefCount.hh"
#include "debug/SkedCache.hh" #include "debug/SkedCache.hh"
#include "debug/Quiesce.hh" #include "debug/Quiesce.hh"
#include "mem/translating_port.hh" #include "mem/translating_port.hh"
#include "params/InOrderCPU.hh" #include "params/InOrderCPU.hh"
#include "sim/full_system.hh"
#include "sim/process.hh" #include "sim/process.hh"
#include "sim/stat_control.hh" #include "sim/stat_control.hh"
#include "sim/system.hh" #include "sim/system.hh"
@ -150,12 +151,11 @@ InOrderCPU::CPUEvent::process()
cpu->trapPending[tid] = false; cpu->trapPending[tid] = false;
break; break;
#if !FULL_SYSTEM
case Syscall: case Syscall:
cpu->syscall(inst->syscallNum, tid); cpu->syscall(inst->syscallNum, tid);
cpu->resPool->trap(fault, tid, inst); cpu->resPool->trap(fault, tid, inst);
break; break;
#endif
default: default:
fatal("Unrecognized Event Type %s", eventNames[cpuEventType]); fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
} }
@ -195,9 +195,7 @@ InOrderCPU::InOrderCPU(Params *params)
timeBuffer(2 , 2), timeBuffer(2 , 2),
removeInstsThisCycle(false), removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity), activityRec(params->name, NumStages, 10, params->activity),
#if FULL_SYSTEM
system(params->system), system(params->system),
#endif // FULL_SYSTEM
#ifdef DEBUG #ifdef DEBUG
cpuEventNum(0), cpuEventNum(0),
resReqCount(0), resReqCount(0),
@ -216,35 +214,32 @@ InOrderCPU::InOrderCPU(Params *params)
// Resize for Multithreading CPUs // Resize for Multithreading CPUs
thread.resize(numThreads); thread.resize(numThreads);
#if FULL_SYSTEM if (FullSystem) {
active_threads = 1; active_threads = 1;
#else
active_threads = params->workload.size();
if (active_threads > MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'"
"in your InOrder implementation or "
"edit your workload size.");
}
if (active_threads > 1) {
threadModel = (InOrderCPU::ThreadModel) params->threadModel;
if (threadModel == SMT) {
DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
} else if (threadModel == SwitchOnCacheMiss) {
DPRINTF(InOrderCPU, "Setting Thread Model to "
"Switch On Cache Miss\n");
}
} else { } else {
threadModel = Single; active_threads = params->workload.size();
if (active_threads > MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'"
"in your InOrder implementation or "
"edit your workload size.");
}
if (active_threads > 1) {
threadModel = (InOrderCPU::ThreadModel) params->threadModel;
if (threadModel == SMT) {
DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
} else if (threadModel == SwitchOnCacheMiss) {
DPRINTF(InOrderCPU, "Setting Thread Model to "
"Switch On Cache Miss\n");
}
} else {
threadModel = Single;
}
} }
#endif
// Bind the fetch & data ports from the resource pool. // Bind the fetch & data ports from the resource pool.
fetchPortIdx = resPool->getPortIdx(params->fetchMemPort); fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
@ -261,36 +256,34 @@ InOrderCPU::InOrderCPU(Params *params)
pc[tid].set(0); pc[tid].set(0);
lastCommittedPC[tid].set(0); lastCommittedPC[tid].set(0);
#if FULL_SYSTEM if (FullSystem) {
// SMT is not supported in FS mode yet. // SMT is not supported in FS mode yet.
assert(numThreads == 1); assert(numThreads == 1);
thread[tid] = new Thread(this, 0, NULL); thread[tid] = new Thread(this, 0, NULL);
#else
if (tid < (ThreadID)params->workload.size()) {
DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
tid, params->workload[tid]->prog_fname);
thread[tid] =
new Thread(this, tid, params->workload[tid]);
} else { } else {
//Allocate Empty thread so M5 can use later if (tid < (ThreadID)params->workload.size()) {
//when scheduling threads to CPU DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
Process* dummy_proc = params->workload[0]; tid, params->workload[tid]->prog_fname);
thread[tid] = new Thread(this, tid, dummy_proc); thread[tid] =
new Thread(this, tid, params->workload[tid]);
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = params->workload[0];
thread[tid] = new Thread(this, tid, dummy_proc);
}
// Eventually set this with parameters...
asid[tid] = tid;
} }
// Eventually set this with parameters...
asid[tid] = tid;
#endif
// Setup the TC that will serve as the interface to the threads/CPU. // Setup the TC that will serve as the interface to the threads/CPU.
InOrderThreadContext *tc = new InOrderThreadContext; InOrderThreadContext *tc = new InOrderThreadContext;
tc->cpu = this; tc->cpu = this;
tc->thread = thread[tid]; tc->thread = thread[tid];
#if FULL_SYSTEM
// Setup quiesce event. // Setup quiesce event.
this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
#endif
// Give the thread the TC. // Give the thread the TC.
thread[tid]->tc = tc; thread[tid]->tc = tc;
@ -349,16 +342,17 @@ InOrderCPU::InOrderCPU(Params *params)
dummyReq[tid] = new ResourceRequest(resPool->getResource(0)); dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
#if FULL_SYSTEM
// Use this dummy inst to force squashing behind every instruction
// in pipeline
dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyTrapInst[tid]->seqNum = 0;
dummyTrapInst[tid]->squashSeqNum = 0;
dummyTrapInst[tid]->setTid(tid);
#endif
trapPending[tid] = false; if (FullSystem) {
// Use this dummy inst to force squashing behind every instruction
// in pipeline
dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyTrapInst[tid]->seqNum = 0;
dummyTrapInst[tid]->squashSeqNum = 0;
dummyTrapInst[tid]->setTid(tid);
}
trapPending[tid] = false;
} }
@ -699,9 +693,7 @@ InOrderCPU::tick()
++numCycles; ++numCycles;
#if FULL_SYSTEM
checkForInterrupts(); checkForInterrupts();
#endif
bool pipes_idle = true; bool pipes_idle = true;
//Tick each of the stages //Tick each of the stages
@ -762,12 +754,12 @@ InOrderCPU::init()
for (ThreadID tid = 0; tid < numThreads; ++tid) for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true; thread[tid]->inSyscall = true;
#if FULL_SYSTEM if (FullSystem) {
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid]; ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId()); TheISA::initCPU(src_tc, src_tc->contextId());
}
} }
#endif
// Clear inSyscall. // Clear inSyscall.
for (ThreadID tid = 0; tid < numThreads; ++tid) for (ThreadID tid = 0; tid < numThreads; ++tid)

2
src/cpu/inorder/cpu.hh
View file

@ -780,10 +780,8 @@ class InOrderCPU : public BaseCPU
return total; return total;
} }
#if FULL_SYSTEM
/** Pointer to the system. */ /** Pointer to the system. */
System *system; System *system;
#endif
/** The global sequence number counter. */ /** The global sequence number counter. */
InstSeqNum globalSeqNum[ThePipeline::MaxThreads]; InstSeqNum globalSeqNum[ThePipeline::MaxThreads];

20
src/cpu/inorder/inorder_cpu_builder.cc
View file

@ -38,21 +38,23 @@
#include "cpu/inst_seq.hh" #include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "params/InOrderCPU.hh" #include "params/InOrderCPU.hh"
#include "sim/full_system.hh"
InOrderCPU * InOrderCPU *
InOrderCPUParams::create() InOrderCPUParams::create()
{ {
#if FULL_SYSTEM ThreadID actual_num_threads;
// Full-system only supports a single thread for the moment. if (FullSystem) {
ThreadID actual_num_threads = 1; // Full-system only supports a single thread for the moment.
#else actual_num_threads = 1;
ThreadID actual_num_threads = } else {
(numThreads >= workload.size()) ? numThreads : workload.size(); actual_num_threads =
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) { if (workload.size() == 0) {
fatal("Must specify at least one workload!"); fatal("Must specify at least one workload!");
}
} }
#endif
numThreads = actual_num_threads; numThreads = actual_num_threads;

2
src/cpu/inorder/params.hh
View file

@ -50,10 +50,8 @@ class InOrderParams : public BaseCPU::Params
public: public:
// Workloads // Workloads
#if !FULL_SYSTEM
std::vector<Process *> workload; std::vector<Process *> workload;
Process *process; Process *process;
#endif // FULL_SYSTEM
// //
// Memory System/Caches // Memory System/Caches

5
src/cpu/inorder/resources/cache_unit.cc
View file

@ -150,14 +150,11 @@ CacheUnit::CachePort::setPeer(Port *port)
{ {
Port::setPeer(port); Port::setPeer(port);
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual // Update the ThreadContext's memory ports (Functional/Virtual
// Ports) // Ports)
if (cachePortUnit->resName == "dcache_port") { if (cachePortUnit->resName == "dcache_port") {
cachePortUnit->cpu->updateMemPorts(); cachePortUnit->cpu->updateMemPorts();
} }
#endif
} }
Port * Port *
@ -454,13 +451,11 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
} }
} }
#if !FULL_SYSTEM
void void
CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst) CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
{ {
tlbBlocked[tid] = false; tlbBlocked[tid] = false;
} }
#endif
Fault Fault
CacheUnit::read(DynInstPtr inst, Addr addr, CacheUnit::read(DynInstPtr inst, Addr addr,

3
src/cpu/inorder/resources/cache_unit.hh
View file

@ -158,9 +158,8 @@ class CacheUnit : public Resource
bool processSquash(CacheReqPacket *cache_pkt); bool processSquash(CacheReqPacket *cache_pkt);
#if !FULL_SYSTEM
void trap(Fault fault, ThreadID tid, DynInstPtr inst); void trap(Fault fault, ThreadID tid, DynInstPtr inst);
#endif
void recvRetry(); void recvRetry();
/** Returns a specific port. */ /** Returns a specific port. */

15
src/cpu/inorder/resources/execution_unit.cc
View file

@ -38,6 +38,7 @@
#include "debug/Fault.hh" #include "debug/Fault.hh"
#include "debug/InOrderExecute.hh" #include "debug/InOrderExecute.hh"
#include "debug/InOrderStall.hh" #include "debug/InOrderStall.hh"
#include "sim/full_system.hh"
using namespace std; using namespace std;
using namespace ThePipeline; using namespace ThePipeline;
@ -219,14 +220,14 @@ ExecutionUnit::execute(int slot_num)
seq_num, didx, inst->readIntResult(didx)); seq_num, didx, inst->readIntResult(didx));
#endif #endif
#if !FULL_SYSTEM if (!FullSystem) {
// The Syscall might change the PC, so conservatively // The Syscall might change the PC, so conservatively
// squash everything behing it // squash everything behing it
if (inst->isSyscall()) { if (inst->isSyscall()) {
inst->setSquashInfo(stage_num); inst->setSquashInfo(stage_num);
setupSquash(inst, stage_num, tid); setupSquash(inst, stage_num, tid);
}
} }
#endif
} else { } else {
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s " DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
"fault.\n", inst->readTid(), seq_num, fault->name()); "fault.\n", inst->readTid(), seq_num, fault->name());

12
src/cpu/inorder/thread_context.cc
View file

@ -34,6 +34,7 @@
#include "cpu/inorder/thread_context.hh" #include "cpu/inorder/thread_context.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "debug/InOrderCPU.hh" #include "debug/InOrderCPU.hh"
#include "sim/full_system.hh"
using namespace TheISA; using namespace TheISA;
@ -88,9 +89,7 @@ InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
setStatus(old_context->status()); setStatus(old_context->status());
copyArchRegs(old_context); copyArchRegs(old_context);
#if !FULL_SYSTEM
thread->funcExeInst = old_context->readFuncExeInst(); thread->funcExeInst = old_context->readFuncExeInst();
#endif
old_context->setStatus(ThreadContext::Halted); old_context->setStatus(ThreadContext::Halted);
@ -143,11 +142,10 @@ InOrderThreadContext::halt(int delay)
void void
InOrderThreadContext::regStats(const std::string &name) InOrderThreadContext::regStats(const std::string &name)
{ {
#if FULL_SYSTEM if (FullSystem) {
thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
thread->kernelStats->regStats(name + ".kern"); thread->kernelStats->regStats(name + ".kern");
#endif }
;
} }

2
src/cpu/inorder/thread_context.hh
View file

@ -109,11 +109,9 @@ class InOrderThreadContext : public ThreadContext
void setNextMicroPC(uint64_t val) { }; void setNextMicroPC(uint64_t val) { };
#if FULL_SYSTEM
/** Returns a pointer to physical memory. */ /** Returns a pointer to physical memory. */
PhysicalMemory *getPhysMemPtr() PhysicalMemory *getPhysMemPtr()
{ assert(0); return 0; /*return cpu->physmem;*/ } { assert(0); return 0; /*return cpu->physmem;*/ }
#endif
/** Returns a pointer to this thread's kernel statistics. */ /** Returns a pointer to this thread's kernel statistics. */
TheISA::Kernel::Statistics *getKernelStats() TheISA::Kernel::Statistics *getKernelStats()

12
src/cpu/inorder/thread_state.hh
View file

@ -39,17 +39,13 @@
#include "cpu/thread_state.hh" #include "cpu/thread_state.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
class Event;
class InOrderCPU;
#if FULL_SYSTEM
class EndQuiesceEvent; class EndQuiesceEvent;
class FunctionProfile; class Event;
class ProfileNode;
#else
class FunctionalMemory; class FunctionalMemory;
#endif class FunctionProfile;
class InOrderCPU;
class Process; class Process;
class ProfileNode;
/** /**
* Class that has various thread state, such as the status, the * Class that has various thread state, such as the status, the

8
src/cpu/intr_control.cc
View file

@ -48,27 +48,19 @@ IntrControl::IntrControl(const Params *p)
void void
IntrControl::post(int cpu_id, int int_num, int index) IntrControl::post(int cpu_id, int int_num, int index)
{ {
#if FULL_SYSTEM
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id); DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts; std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->postInterrupt(int_num, index); cpu->postInterrupt(int_num, index);
#else
panic("Called IntrControl::post in SE mode.\n");
#endif
} }
void void
IntrControl::clear(int cpu_id, int int_num, int index) IntrControl::clear(int cpu_id, int int_num, int index)
{ {
#if FULL_SYSTEM
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id); DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts; std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->clearInterrupt(int_num, index); cpu->clearInterrupt(int_num, index);
#else
panic("Called IntrControl::clear in SE mode.\n");
#endif
} }
IntrControl * IntrControl *

15
src/cpu/legiontrace.cc
View file

@ -36,11 +36,6 @@
#error Legion tracing only works with SPARC simulations! #error Legion tracing only works with SPARC simulations!
#endif #endif
#include "config/full_system.hh"
#if !FULL_SYSTEM
#error Legion tracing only works in full system!
#endif
#include <sys/ipc.h> #include <sys/ipc.h>
#include <sys/shm.h> #include <sys/shm.h>
@ -50,28 +45,24 @@
#include "arch/sparc/predecoder.hh" #include "arch/sparc/predecoder.hh"
#include "arch/sparc/registers.hh" #include "arch/sparc/registers.hh"
#include "arch/sparc/utility.hh" #include "arch/sparc/utility.hh"
#include "arch/tlb.hh"
#include "base/socket.hh" #include "base/socket.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/decode.hh" #include "cpu/decode.hh"
#include "cpu/legiontrace.hh" #include "cpu/legiontrace.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "sim/full_system.hh"
#include "sim/system.hh" #include "sim/system.hh"
#if FULL_SYSTEM
#include "arch/tlb.hh"
#endif
//XXX This is temporary //XXX This is temporary
#include "cpu/m5legion_interface.h" #include "cpu/m5legion_interface.h"
using namespace std; using namespace std;
using namespace TheISA; using namespace TheISA;
#if FULL_SYSTEM
static int diffcount = 0; static int diffcount = 0;
static bool wasMicro = false; static bool wasMicro = false;
#endif
namespace Trace { namespace Trace {
SharedData *shared_data = NULL; SharedData *shared_data = NULL;
@ -597,5 +588,7 @@ Trace::LegionTraceRecord::dump()
Trace::LegionTrace * Trace::LegionTrace *
LegionTraceParams::create() LegionTraceParams::create()
{ {
if (!FullSystem)
panic("Legion tracing only works in full system!");
return new Trace::LegionTrace(this); return new Trace::LegionTrace(this);
}; };

14
src/cpu/o3/O3CPU.py
View file

@ -40,15 +40,11 @@ class DerivO3CPU(BaseCPU):
activity = Param.Unsigned(0, "Initial count") activity = Param.Unsigned(0, "Initial count")
if buildEnv['USE_CHECKER']: if buildEnv['USE_CHECKER']:
if not buildEnv['FULL_SYSTEM']: checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
checker = Param.BaseCPU(O3Checker(workload=Parent.workload, exitOnError=False,
exitOnError=False, updateOnError=True,
updateOnError=True, warnOnlyOnLoadError=False),
warnOnlyOnLoadError=False), "checker")
"checker")
else:
checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
warnOnlyOnLoadError=False), "checker")
checker.itb = Parent.itb checker.itb = Parent.itb
checker.dtb = Parent.dtb checker.dtb = Parent.dtb

3
src/cpu/o3/checker_builder.cc
View file

@ -90,11 +90,8 @@ O3CheckerParams::create()
params->dtb = dtb; params->dtb = dtb;
params->system = system; params->system = system;
params->cpu_id = cpu_id; params->cpu_id = cpu_id;
#if FULL_SYSTEM
params->profile = profile; params->profile = profile;
#else
params->process = workload; params->process = workload;
#endif
O3Checker *cpu = new O3Checker(params); O3Checker *cpu = new O3Checker(params);
return cpu; return cpu;

2
src/cpu/o3/commit.hh
View file

@ -267,13 +267,11 @@ class DefaultCommit
void squashAfter(ThreadID tid, DynInstPtr &head_inst, void squashAfter(ThreadID tid, DynInstPtr &head_inst,
uint64_t squash_after_seq_num); uint64_t squash_after_seq_num);
#if FULL_SYSTEM
/** Handles processing an interrupt. */ /** Handles processing an interrupt. */
void handleInterrupt(); void handleInterrupt();
/** Get fetch redirecting so we can handle an interrupt */ /** Get fetch redirecting so we can handle an interrupt */
void propagateInterrupt(); void propagateInterrupt();
#endif // FULL_SYSTEM
/** Commits as many instructions as possible. */ /** Commits as many instructions as possible. */
void commitInsts(); void commitInsts();

51
src/cpu/o3/commit_impl.hh
View file

@ -47,7 +47,6 @@
#include "arch/utility.hh" #include "arch/utility.hh"
#include "base/loader/symtab.hh" #include "base/loader/symtab.hh"
#include "base/cp_annotate.hh" #include "base/cp_annotate.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "config/use_checker.hh" #include "config/use_checker.hh"
#include "cpu/o3/commit.hh" #include "cpu/o3/commit.hh"
@ -61,6 +60,7 @@
#include "debug/O3PipeView.hh" #include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh" #include "params/DerivO3CPU.hh"
#include "sim/faults.hh" #include "sim/faults.hh"
#include "sim/full_system.hh"
#if USE_CHECKER #if USE_CHECKER
#include "cpu/checker/cpu.hh" #include "cpu/checker/cpu.hh"
@ -148,9 +148,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
pc[tid].set(0); pc[tid].set(0);
lastCommitedSeqNum[tid] = 0; lastCommitedSeqNum[tid] = 0;
} }
#if FULL_SYSTEM
interrupt = NoFault; interrupt = NoFault;
#endif
} }
template <class Impl> template <class Impl>
@ -700,7 +698,6 @@ DefaultCommit<Impl>::tick()
updateStatus(); updateStatus();
} }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
void void
DefaultCommit<Impl>::handleInterrupt() DefaultCommit<Impl>::handleInterrupt()
@ -766,22 +763,20 @@ DefaultCommit<Impl>::propagateInterrupt()
toIEW->commitInfo[0].interruptPending = true; toIEW->commitInfo[0].interruptPending = true;
} }
#endif // FULL_SYSTEM
template <class Impl> template <class Impl>
void void
DefaultCommit<Impl>::commit() DefaultCommit<Impl>::commit()
{ {
if (FullSystem) {
// Check for any interrupt that we've already squashed for and start
// processing it.
if (interrupt != NoFault)
handleInterrupt();
#if FULL_SYSTEM // Check if we have a interrupt and get read to handle it
// Check for any interrupt that we've already squashed for and start processing it. if (cpu->checkInterrupts(cpu->tcBase(0)))
if (interrupt != NoFault) propagateInterrupt();
handleInterrupt(); }
// Check if we have a interrupt and get read to handle it
if (cpu->checkInterrupts(cpu->tcBase(0)))
propagateInterrupt();
#endif // FULL_SYSTEM
//////////////////////////////////// ////////////////////////////////////
// Check for any possible squashes, handle them first // Check for any possible squashes, handle them first
@ -1173,22 +1168,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
updateComInstStats(head_inst); updateComInstStats(head_inst);
#if FULL_SYSTEM if (FullSystem) {
if (thread[tid]->profile) { if (thread[tid]->profile) {
thread[tid]->profilePC = head_inst->instAddr(); thread[tid]->profilePC = head_inst->instAddr();
ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), ProfileNode *node = thread[tid]->profile->consume(
head_inst->staticInst); thread[tid]->getTC(), head_inst->staticInst);
if (node) if (node)
thread[tid]->profileNode = node; thread[tid]->profileNode = node;
} }
if (CPA::available()) { if (CPA::available()) {
if (head_inst->isControl()) { if (head_inst->isControl()) {
ThreadContext *tc = thread[tid]->getTC(); ThreadContext *tc = thread[tid]->getTC();
CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
}
} }
} }
#endif
DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
head_inst->seqNum, head_inst->pcState()); head_inst->seqNum, head_inst->pcState());
if (head_inst->traceData) { if (head_inst->traceData) {

113
src/cpu/o3/cpu.cc
View file

@ -32,7 +32,6 @@
*/ */
#include "arch/kernel_stats.hh" #include "arch/kernel_stats.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "config/use_checker.hh" #include "config/use_checker.hh"
#include "cpu/o3/cpu.hh" #include "cpu/o3/cpu.hh"
@ -47,6 +46,7 @@
#include "debug/Quiesce.hh" #include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh" #include "enums/MemoryMode.hh"
#include "sim/core.hh" #include "sim/core.hh"
#include "sim/full_system.hh"
#include "sim/process.hh" #include "sim/process.hh"
#include "sim/stat_control.hh" #include "sim/stat_control.hh"
#include "sim/system.hh" #include "sim/system.hh"
@ -215,18 +215,16 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
if (params->checker) { if (params->checker) {
BaseCPU *temp_checker = params->checker; BaseCPU *temp_checker = params->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
#if FULL_SYSTEM
checker->setSystem(params->system); checker->setSystem(params->system);
#endif
} else { } else {
checker = NULL; checker = NULL;
} }
#endif // USE_CHECKER #endif // USE_CHECKER
#if !FULL_SYSTEM if (!FullSystem) {
thread.resize(numThreads); thread.resize(numThreads);
tids.resize(numThreads); tids.resize(numThreads);
#endif }
// The stages also need their CPU pointer setup. However this // The stages also need their CPU pointer setup. However this
// must be done at the upper level CPU because they have pointers // must be done at the upper level CPU because they have pointers
@ -262,17 +260,18 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
rename.setIEWStage(&iew); rename.setIEWStage(&iew);
rename.setCommitStage(&commit); rename.setCommitStage(&commit);
#if !FULL_SYSTEM ThreadID active_threads;
ThreadID active_threads = params->workload.size(); if (FullSystem) {
active_threads = 1;
} else {
active_threads = params->workload.size();
if (active_threads > Impl::MaxThreads) { if (active_threads > Impl::MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'" panic("Workload Size too large. Increase the 'MaxThreads' "
"constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
"edit your workload size."); "or edit your workload size.");
}
} }
#else
ThreadID active_threads = 1;
#endif
//Make Sure That this a Valid Architeture //Make Sure That this a Valid Architeture
assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
@ -351,31 +350,31 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
this->thread.resize(this->numThreads); this->thread.resize(this->numThreads);
for (ThreadID tid = 0; tid < this->numThreads; ++tid) { for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
#if FULL_SYSTEM if (FullSystem) {
// SMT is not supported in FS mode yet. // SMT is not supported in FS mode yet.
assert(this->numThreads == 1); assert(this->numThreads == 1);
this->thread[tid] = new Thread(this, 0, NULL); this->thread[tid] = new Thread(this, 0, NULL);
#else
if (tid < params->workload.size()) {
DPRINTF(O3CPU, "Workload[%i] process is %#x",
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
tid, params->workload[tid]);
//usedTids[tid] = true;
//threadMap[tid] = tid;
} else { } else {
//Allocate Empty thread so M5 can use later if (tid < params->workload.size()) {
//when scheduling threads to CPU DPRINTF(O3CPU, "Workload[%i] process is %#x",
Process* dummy_proc = NULL; tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
tid, params->workload[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread( //usedTids[tid] = true;
(typename Impl::O3CPU *)(this), //threadMap[tid] = tid;
tid, dummy_proc); } else {
//usedTids[tid] = false; //Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = NULL;
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
tid, dummy_proc);
//usedTids[tid] = false;
}
} }
#endif // !FULL_SYSTEM
ThreadContext *tc; ThreadContext *tc;
@ -397,10 +396,10 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
assert(o3_tc->cpu); assert(o3_tc->cpu);
o3_tc->thread = this->thread[tid]; o3_tc->thread = this->thread[tid];
#if FULL_SYSTEM if (FullSystem) {
// Setup quiesce event. // Setup quiesce event.
this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
#endif }
// Give the thread the TC. // Give the thread the TC.
this->thread[tid]->tc = tc; this->thread[tid]->tc = tc;
@ -547,9 +546,8 @@ FullO3CPU<Impl>::tick()
commit.tick(); commit.tick();
#if !FULL_SYSTEM if (!FullSystem)
doContextSwitch(); doContextSwitch();
#endif
// Now advance the time buffers // Now advance the time buffers
timeBuffer.advance(); timeBuffer.advance();
@ -581,9 +579,8 @@ FullO3CPU<Impl>::tick()
} }
} }
#if !FULL_SYSTEM if (!FullSystem)
updateThreadPriority(); updateThreadPriority();
#endif
} }
template <class Impl> template <class Impl>
@ -597,12 +594,12 @@ FullO3CPU<Impl>::init()
for (ThreadID tid = 0; tid < numThreads; ++tid) for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true; thread[tid]->inSyscall = true;
#if FULL_SYSTEM if (FullSystem) {
for (ThreadID tid = 0; tid < numThreads; tid++) { for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid]; ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId()); TheISA::initCPU(src_tc, src_tc->contextId());
}
} }
#endif
// Clear inSyscall. // Clear inSyscall.
for (int tid = 0; tid < numThreads; ++tid) for (int tid = 0; tid < numThreads; ++tid)
@ -738,11 +735,11 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
// Will change now that the PC and thread state is internal to the CPU // Will change now that the PC and thread state is internal to the CPU
// and not in the ThreadContext. // and not in the ThreadContext.
#if FULL_SYSTEM ThreadContext *src_tc;
ThreadContext *src_tc = system->threadContexts[tid]; if (FullSystem)
#else src_tc = system->threadContexts[tid];
ThreadContext *src_tc = tcBase(tid); else
#endif src_tc = tcBase(tid);
//Bind Int Regs to Rename Map //Bind Int Regs to Rename Map
for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {

31
src/cpu/o3/cpu_builder.cc
View file

@ -47,22 +47,23 @@ class DerivO3CPU : public FullO3CPU<O3CPUImpl>
DerivO3CPU * DerivO3CPU *
DerivO3CPUParams::create() DerivO3CPUParams::create()
{ {
#if FULL_SYSTEM ThreadID actual_num_threads;
// Full-system only supports a single thread for the moment. if (FullSystem) {
ThreadID actual_num_threads = 1; // Full-system only supports a single thread for the moment.
#else actual_num_threads = 1;
if (workload.size() > numThreads) { } else {
fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU", if (workload.size() > numThreads) {
workload.size(), numThreads); fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
} else if (workload.size() == 0) { workload.size(), numThreads);
fatal("Must specify at least one workload!"); } else if (workload.size() == 0) {
fatal("Must specify at least one workload!");
}
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
actual_num_threads =
(numThreads >= workload.size()) ? numThreads : workload.size();
} }
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
ThreadID actual_num_threads =
(numThreads >= workload.size()) ? numThreads : workload.size();
#endif
numThreads = actual_num_threads; numThreads = actual_num_threads;

23
src/cpu/o3/decode_impl.hh
View file

@ -30,13 +30,13 @@
#include "arch/types.hh" #include "arch/types.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "cpu/o3/decode.hh" #include "cpu/o3/decode.hh"
#include "cpu/inst_seq.hh" #include "cpu/inst_seq.hh"
#include "debug/Activity.hh" #include "debug/Activity.hh"
#include "debug/Decode.hh" #include "debug/Decode.hh"
#include "params/DerivO3CPU.hh" #include "params/DerivO3CPU.hh"
#include "sim/full_system.hh"
using namespace std; using namespace std;
@ -322,19 +322,18 @@ DefaultDecode<Impl>::squash(ThreadID tid)
if (decodeStatus[tid] == Blocked || if (decodeStatus[tid] == Blocked ||
decodeStatus[tid] == Unblocking) { decodeStatus[tid] == Unblocking) {
#if !FULL_SYSTEM if (FullSystem) {
// In syscall emulation, we can have both a block and a squash due
// to a syscall in the same cycle. This would cause both signals to
// be high. This shouldn't happen in full system.
// @todo: Determine if this still happens.
if (toFetch->decodeBlock[tid]) {
toFetch->decodeBlock[tid] = 0;
} else {
toFetch->decodeUnblock[tid] = 1; toFetch->decodeUnblock[tid] = 1;
} else {
// In syscall emulation, we can have both a block and a squash due
// to a syscall in the same cycle. This would cause both signals
// to be high. This shouldn't happen in full system.
// @todo: Determine if this still happens.
if (toFetch->decodeBlock[tid])
toFetch->decodeBlock[tid] = 0;
else
toFetch->decodeUnblock[tid] = 1;
} }
#else
toFetch->decodeUnblock[tid] = 1;
#endif
} }
// Set status to squashing. // Set status to squashing.

22
src/cpu/o3/fetch_impl.hh
View file

@ -45,7 +45,9 @@
#include <cstring> #include <cstring>
#include "arch/isa_traits.hh" #include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "arch/utility.hh" #include "arch/utility.hh"
#include "arch/vtophys.hh"
#include "base/types.hh" #include "base/types.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "config/use_checker.hh" #include "config/use_checker.hh"
@ -61,12 +63,8 @@
#include "sim/byteswap.hh" #include "sim/byteswap.hh"
#include "sim/core.hh" #include "sim/core.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"
#include "sim/full_system.hh"
#if FULL_SYSTEM
#include "arch/tlb.hh"
#include "arch/vtophys.hh"
#include "sim/system.hh" #include "sim/system.hh"
#endif // FULL_SYSTEM
using namespace std; using namespace std;
@ -907,15 +905,15 @@ DefaultFetch<Impl>::tick()
DPRINTF(Fetch, "Running stage.\n"); DPRINTF(Fetch, "Running stage.\n");
#if FULL_SYSTEM if (FullSystem) {
if (fromCommit->commitInfo[0].interruptPending) { if (fromCommit->commitInfo[0].interruptPending) {
interruptPending = true; interruptPending = true;
} }
if (fromCommit->commitInfo[0].clearInterrupt) { if (fromCommit->commitInfo[0].clearInterrupt) {
interruptPending = false; interruptPending = false;
}
} }
#endif
for (threadFetched = 0; threadFetched < numFetchingThreads; for (threadFetched = 0; threadFetched < numFetchingThreads;
threadFetched++) { threadFetched++) {

2
src/cpu/o3/lsq.hh
View file

@ -334,10 +334,8 @@ class LSQ {
/** D-cache port. */ /** D-cache port. */
DcachePort dcachePort; DcachePort dcachePort;
#if FULL_SYSTEM
/** Tell the CPU to update the Phys and Virt ports. */ /** Tell the CPU to update the Phys and Virt ports. */
void updateMemPorts() { cpu->updateMemPorts(); } void updateMemPorts() { cpu->updateMemPorts(); }
#endif
protected: protected:
/** The LSQ policy for SMT mode. */ /** The LSQ policy for SMT mode. */

2
src/cpu/o3/lsq_impl.hh
View file

@ -46,11 +46,9 @@ LSQ<Impl>::DcachePort::setPeer(Port *port)
{ {
Port::setPeer(port); Port::setPeer(port);
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual // Update the ThreadContext's memory ports (Functional/Virtual
// Ports) // Ports)
lsq->updateMemPorts(); lsq->updateMemPorts();
#endif
} }
template <class Impl> template <class Impl>

7
src/cpu/o3/regfile.hh
View file

@ -35,6 +35,7 @@
#include <vector> #include <vector>
#include "arch/isa_traits.hh" #include "arch/isa_traits.hh"
#include "arch/kernel_stats.hh"
#include "arch/types.hh" #include "arch/types.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
@ -42,10 +43,6 @@
#include "cpu/o3/comm.hh" #include "cpu/o3/comm.hh"
#include "debug/IEW.hh" #include "debug/IEW.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#endif
/** /**
* Simple physical register file class. * Simple physical register file class.
* Right now this is specific to Alpha until we decide if/how to make things * Right now this is specific to Alpha until we decide if/how to make things
@ -174,10 +171,8 @@ class PhysRegFile
/** Floating point register file. */ /** Floating point register file. */
PhysFloatReg *floatRegFile; PhysFloatReg *floatRegFile;
#if FULL_SYSTEM
private: private:
int intrflag; // interrupt flag int intrflag; // interrupt flag
#endif
private: private:
/** CPU pointer. */ /** CPU pointer. */

74
src/cpu/o3/thread_context_impl.hh
View file

@ -41,6 +41,7 @@
* Korey Sewell * Korey Sewell
*/ */
#include "arch/kernel_stats.hh"
#include "arch/registers.hh" #include "arch/registers.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "cpu/o3/thread_context.hh" #include "cpu/o3/thread_context.hh"
@ -66,9 +67,7 @@ void
O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
{ {
// some things should already be set up // some things should already be set up
#if FULL_SYSTEM
assert(getSystemPtr() == old_context->getSystemPtr()); assert(getSystemPtr() == old_context->getSystemPtr());
#endif
assert(getProcessPtr() == old_context->getProcessPtr()); assert(getProcessPtr() == old_context->getProcessPtr());
// copy over functional state // copy over functional state
@ -77,24 +76,23 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
setContextId(old_context->contextId()); setContextId(old_context->contextId());
setThreadId(old_context->threadId()); setThreadId(old_context->threadId());
#if !FULL_SYSTEM if (FullSystem) {
thread->funcExeInst = old_context->readFuncExeInst(); EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
#else if (other_quiesce) {
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); // Point the quiesce event's TC at this TC so that it wakes up
if (other_quiesce) { // the proper CPU.
// Point the quiesce event's TC at this TC so that it wakes up other_quiesce->tc = this;
// the proper CPU. }
other_quiesce->tc = this; if (thread->quiesceEvent) {
} thread->quiesceEvent->tc = this;
if (thread->quiesceEvent) { }
thread->quiesceEvent->tc = this;
}
// Transfer kernel stats from one CPU to the other. // Transfer kernel stats from one CPU to the other.
thread->kernelStats = old_context->getKernelStats(); thread->kernelStats = old_context->getKernelStats();
// storeCondFailures = 0; cpu->lockFlag = false;
cpu->lockFlag = false; } else {
#endif thread->funcExeInst = old_context->readFuncExeInst();
}
old_context->setStatus(ThreadContext::Halted); old_context->setStatus(ThreadContext::Halted);
@ -112,10 +110,7 @@ O3ThreadContext<Impl>::activate(int delay)
if (thread->status() == ThreadContext::Active) if (thread->status() == ThreadContext::Active)
return; return;
#if FULL_SYSTEM
thread->lastActivate = curTick(); thread->lastActivate = curTick();
#endif
thread->setStatus(ThreadContext::Active); thread->setStatus(ThreadContext::Active);
// status() == Suspended // status() == Suspended
@ -132,19 +127,9 @@ O3ThreadContext<Impl>::suspend(int delay)
if (thread->status() == ThreadContext::Suspended) if (thread->status() == ThreadContext::Suspended)
return; return;
#if FULL_SYSTEM
thread->lastActivate = curTick(); thread->lastActivate = curTick();
thread->lastSuspend = curTick(); thread->lastSuspend = curTick();
#endif
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->checkInterrupts()) {
assert(status() == ThreadContext::Active);
return;
}
#endif
*/
thread->setStatus(ThreadContext::Suspended); thread->setStatus(ThreadContext::Suspended);
cpu->suspendContext(thread->threadId()); cpu->suspendContext(thread->threadId());
} }
@ -167,32 +152,26 @@ template <class Impl>
void void
O3ThreadContext<Impl>::regStats(const std::string &name) O3ThreadContext<Impl>::regStats(const std::string &name)
{ {
#if FULL_SYSTEM if (FullSystem) {
thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
thread->kernelStats->regStats(name + ".kern"); thread->kernelStats->regStats(name + ".kern");
#endif }
} }
template <class Impl> template <class Impl>
void void
O3ThreadContext<Impl>::serialize(std::ostream &os) O3ThreadContext<Impl>::serialize(std::ostream &os)
{ {
#if FULL_SYSTEM if (FullSystem && thread->kernelStats)
if (thread->kernelStats)
thread->kernelStats->serialize(os); thread->kernelStats->serialize(os);
#endif
} }
template <class Impl> template <class Impl>
void void
O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section) O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
{ {
#if FULL_SYSTEM if (FullSystem && thread->kernelStats)
if (thread->kernelStats)
thread->kernelStats->unserialize(cp, section); thread->kernelStats->unserialize(cp, section);
#endif
} }
template <class Impl> template <class Impl>
@ -232,9 +211,8 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
TheISA::copyRegs(tc, this); TheISA::copyRegs(tc, this);
thread->inSyscall = false; thread->inSyscall = false;
#if !FULL_SYSTEM if (!FullSystem)
this->thread->funcExeInst = tc->readFuncExeInst(); this->thread->funcExeInst = tc->readFuncExeInst();
#endif
} }
template <class Impl> template <class Impl>

30
src/cpu/o3/thread_state.hh
View file

@ -35,6 +35,7 @@
#include "base/output.hh" #include "base/output.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "cpu/thread_state.hh" #include "cpu/thread_state.hh"
#include "sim/full_system.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
class EndQuiesceEvent; class EndQuiesceEvent;
@ -74,21 +75,22 @@ struct O3ThreadState : public ThreadState {
: ThreadState(_cpu, _thread_num, _process), : ThreadState(_cpu, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0) cpu(_cpu), inSyscall(0), trapPending(0)
{ {
#if FULL_SYSTEM if (FullSystem) {
if (cpu->params()->profile) { if (cpu->params()->profile) {
profile = new FunctionProfile(cpu->params()->system->kernelSymtab); profile = new FunctionProfile(
Callback *cb = cpu->params()->system->kernelSymtab);
new MakeCallback<O3ThreadState, Callback *cb =
&O3ThreadState::dumpFuncProfile>(this); new MakeCallback<O3ThreadState,
registerExitCallback(cb); &O3ThreadState::dumpFuncProfile>(this);
} registerExitCallback(cb);
}
// let's fill with a dummy node for now so we don't get a segfault // let's fill with a dummy node for now so we don't get a segfault
// on the first cycle when there's no node available. // on the first cycle when there's no node available.
static ProfileNode dummyNode; static ProfileNode dummyNode;
profileNode = &dummyNode; profileNode = &dummyNode;
profilePC = 3; profilePC = 3;
#endif }
} }
/** Pointer to the ThreadContext of this thread. */ /** Pointer to the ThreadContext of this thread. */

3
src/cpu/ozone/SimpleOzoneCPU.py
View file

@ -35,8 +35,7 @@ class SimpleOzoneCPU(BaseCPU):
numThreads = Param.Unsigned("number of HW thread contexts") numThreads = Param.Unsigned("number of HW thread contexts")
if not buildEnv['FULL_SYSTEM']: mem = Param.FunctionalMemory(NULL, "memory")
mem = Param.FunctionalMemory(NULL, "memory")
width = Param.Unsigned("Width") width = Param.Unsigned("Width")
frontEndWidth = Param.Unsigned("Front end width") frontEndWidth = Param.Unsigned("Front end width")

9
src/cpu/ozone/back_end_impl.hh
View file

@ -1456,7 +1456,6 @@ BackEnd<Impl>::commitInst(int inst_num)
// thread->funcExeInst--; // thread->funcExeInst--;
if (inst->isNonSpeculative()) { if (inst->isNonSpeculative()) {
#if !FULL_SYSTEM
// Hack to make sure syscalls aren't executed until all stores // Hack to make sure syscalls aren't executed until all stores
// write back their data. This direct communication shouldn't // write back their data. This direct communication shouldn't
// be used for anything other than this. // be used for anything other than this.
@ -1464,7 +1463,6 @@ BackEnd<Impl>::commitInst(int inst_num)
DPRINTF(BE, "Waiting for all stores to writeback.\n"); DPRINTF(BE, "Waiting for all stores to writeback.\n");
return false; return false;
} }
#endif
DPRINTF(BE, "Encountered a store or non-speculative " DPRINTF(BE, "Encountered a store or non-speculative "
"instruction at the head of the ROB, PC %#x.\n", "instruction at the head of the ROB, PC %#x.\n",
@ -1512,7 +1510,6 @@ BackEnd<Impl>::commitInst(int inst_num)
if (inst_fault != NoFault) { if (inst_fault != NoFault) {
if (!inst->isNop()) { if (!inst->isNop()) {
#if FULL_SYSTEM
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n", DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
inst->seqNum, inst->readPC()); inst->seqNum, inst->readPC());
@ -1533,10 +1530,6 @@ BackEnd<Impl>::commitInst(int inst_num)
// generateTrapEvent(); // generateTrapEvent();
return false; return false;
#else // !FULL_SYSTEM
panic("fault (%d) detected @ PC %08p", inst_fault,
inst->PC);
#endif // FULL_SYSTEM
} }
} }
@ -1574,7 +1567,6 @@ BackEnd<Impl>::commitInst(int inst_num)
// Write the done sequence number here. // Write the done sequence number here.
toIEW->doneSeqNum = inst->seqNum; toIEW->doneSeqNum = inst->seqNum;
#if FULL_SYSTEM
int count = 0; int count = 0;
Addr oldpc; Addr oldpc;
do { do {
@ -1591,7 +1583,6 @@ BackEnd<Impl>::commitInst(int inst_num)
// squashPending = true; // squashPending = true;
return false; return false;
} }
#endif
return true; return true;
} }

3
src/cpu/ozone/checker_builder.cc
View file

@ -91,11 +91,8 @@ OzoneCheckerParams::create()
params->dtb = dtb; params->dtb = dtb;
params->system = system; params->system = system;
params->cpu_id = cpu_id; params->cpu_id = cpu_id;
#if FULL_SYSTEM
params->profile = profile; params->profile = profile;
#else
params->process = workload; params->process = workload;
#endif
OzoneChecker *cpu = new OzoneChecker(params); OzoneChecker *cpu = new OzoneChecker(params);
return cpu; return cpu;

34
src/cpu/ozone/cpu.hh
View file

@ -33,6 +33,7 @@
#include <set> #include <set>
#include "arch/alpha/tlb.hh"
#include "base/statistics.hh" #include "base/statistics.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
@ -48,31 +49,20 @@
#include "sim/eventq.hh" #include "sim/eventq.hh"
// forward declarations // forward declarations
#if FULL_SYSTEM
#include "arch/alpha/tlb.hh"
namespace TheISA
{
class TLB;
}
class PhysicalMemory;
class MemoryController;
namespace TheISA { namespace TheISA {
namespace Kernel { namespace Kernel {
class Statistics; class Statistics;
}; };
class TLB;
}; };
#else
class Process;
#endif // FULL_SYSTEM
class Checkpoint; class Checkpoint;
class EndQuiesceEvent; class EndQuiesceEvent;
class MemoryController;
class MemObject; class MemObject;
class PhysicalMemory;
class Process;
class Request; class Request;
namespace Trace { namespace Trace {
@ -116,14 +106,13 @@ class OzoneCPU : public BaseCPU
TheISA::TLB * getDTBPtr() { return cpu->dtb; } TheISA::TLB * getDTBPtr() { return cpu->dtb; }
#if FULL_SYSTEM
System *getSystemPtr() { return cpu->system; } System *getSystemPtr() { return cpu->system; }
PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
TheISA::Kernel::Statistics *getKernelStats() TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); } { return thread->getKernelStats(); }
#endif
Process *getProcessPtr() { return thread->getProcessPtr(); } Process *getProcessPtr() { return thread->getProcessPtr(); }
TranslatingPort *getMemPort() { return thread->getMemPort(); } TranslatingPort *getMemPort() { return thread->getMemPort(); }
@ -147,9 +136,7 @@ class OzoneCPU : public BaseCPU
/// Set the status to Halted. /// Set the status to Halted.
void halt(); void halt();
#if FULL_SYSTEM
void dumpFuncProfile(); void dumpFuncProfile();
#endif
void takeOverFrom(ThreadContext *old_context); void takeOverFrom(ThreadContext *old_context);
@ -158,7 +145,6 @@ class OzoneCPU : public BaseCPU
void serialize(std::ostream &os); void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section); void unserialize(Checkpoint *cp, const std::string &section);
#if FULL_SYSTEM
EndQuiesceEvent *getQuiesceEvent(); EndQuiesceEvent *getQuiesceEvent();
Tick readLastActivate(); Tick readLastActivate();
@ -166,7 +152,6 @@ class OzoneCPU : public BaseCPU
void profileClear(); void profileClear();
void profileSample(); void profileSample();
#endif
int threadId(); int threadId();
@ -226,12 +211,10 @@ class OzoneCPU : public BaseCPU
bool misspeculating() { return false; } bool misspeculating() { return false; }
#if !FULL_SYSTEM
Counter readFuncExeInst() { return thread->funcExeInst; } Counter readFuncExeInst() { return thread->funcExeInst; }
void setFuncExeInst(Counter new_val) void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; } { thread->funcExeInst = new_val; }
#endif
}; };
// Ozone specific thread context // Ozone specific thread context
@ -325,7 +308,6 @@ class OzoneCPU : public BaseCPU
int switchCount; int switchCount;
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr); Addr dbg_vtophys(Addr addr);
bool interval_stats; bool interval_stats;
@ -334,7 +316,6 @@ class OzoneCPU : public BaseCPU
TheISA::TLB *dtb; TheISA::TLB *dtb;
System *system; System *system;
PhysicalMemory *physmem; PhysicalMemory *physmem;
#endif
virtual Port *getPort(const std::string &name, int idx); virtual Port *getPort(const std::string &name, int idx);
@ -413,13 +394,10 @@ class OzoneCPU : public BaseCPU
void dumpInsts() { frontEnd->dumpInsts(); } void dumpInsts() { frontEnd->dumpInsts(); }
#if FULL_SYSTEM
Fault hwrei(); Fault hwrei();
bool simPalCheck(int palFunc); bool simPalCheck(int palFunc);
void processInterrupts(); void processInterrupts();
#else
void syscall(uint64_t &callnum); void syscall(uint64_t &callnum);
#endif
ThreadContext *tcBase() { return tc; } ThreadContext *tcBase() { return tc; }

27
src/cpu/ozone/cpu_builder.cc
View file

@ -57,21 +57,20 @@ DerivOzoneCPUParams::create()
{ {
DerivOzoneCPU *cpu; DerivOzoneCPU *cpu;
#if FULL_SYSTEM if (FullSystem) {
// Full-system only supports a single thread for the moment. // Full-system only supports a single thread for the moment.
ThreadID actual_num_threads = 1; ThreadID actual_num_threads = 1;
#else } else {
// In non-full-system mode, we infer the number of threads from // In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified. // the workload if it's not explicitly specified.
ThreadID actual_num_threads = ThreadID actual_num_threads =
numThreads.isValid() ? numThreads : workload.size(); numThreads.isValid() ? numThreads : workload.size();
if (workload.size() == 0) { if (workload.size() == 0) {
fatal("Must specify at least one workload!"); fatal("Must specify at least one workload!");
}
} }
#endif
SimpleParams *params = new SimpleParams; SimpleParams *params = new SimpleParams;
params->clock = clock; params->clock = clock;
@ -84,15 +83,11 @@ DerivOzoneCPUParams::create()
params->system = system; params->system = system;
params->cpu_id = cpu_id; params->cpu_id = cpu_id;
#if FULL_SYSTEM
params->profile = profile; params->profile = profile;
params->do_quiesce = do_quiesce; params->do_quiesce = do_quiesce;
params->do_checkpoint_insts = do_checkpoint_insts; params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts; params->do_statistics_insts = do_statistics_insts;
#else
params->workload = workload; params->workload = workload;
// params->pTable = page_table;
#endif // FULL_SYSTEM
params->checker = checker; params->checker = checker;
params->max_insts_any_thread = max_insts_any_thread; params->max_insts_any_thread = max_insts_any_thread;

167
src/cpu/ozone/cpu_impl.hh
View file

@ -29,37 +29,33 @@
* Nathan Binkert * Nathan Binkert
*/ */
#include "arch/isa_traits.hh" // For MachInst
#include "base/trace.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#if FULL_SYSTEM
#include "arch/alpha/osfpal.hh" #include "arch/alpha/osfpal.hh"
#include "arch/faults.hh" #include "arch/faults.hh"
#include "arch/isa_traits.hh" // For MachInst
#include "arch/kernel_stats.hh" #include "arch/kernel_stats.hh"
#include "arch/tlb.hh" #include "arch/tlb.hh"
#include "arch/types.hh" #include "arch/types.hh"
#include "arch/vtophys.hh" #include "arch/vtophys.hh"
#include "base/callback.hh" #include "base/callback.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/profile.hh" #include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/faults.hh" #include "sim/faults.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh" #include "sim/sim_events.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "sim/system.hh" #include "sim/system.hh"
#else // !FULL_SYSTEM
#include "sim/process.hh"
#endif // FULL_SYSTEM
#if USE_CHECKER #if USE_CHECKER
#include "cpu/checker/thread_context.hh" #include "cpu/checker/thread_context.hh"
@ -89,12 +85,8 @@ OzoneCPU<Impl>::TickEvent::description() const
template <class Impl> template <class Impl>
OzoneCPU<Impl>::OzoneCPU(Params *p) OzoneCPU<Impl>::OzoneCPU(Params *p)
#if FULL_SYSTEM : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this,
: BaseCPU(p), thread(this, 0), tickEvent(this, p->width), p->width),
#else
: BaseCPU(p), thread(this, 0, p->workload[0], 0),
tickEvent(this, p->width),
#endif
#ifndef NDEBUG #ifndef NDEBUG
instcount(0), instcount(0),
#endif #endif
@ -109,9 +101,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
#if USE_CHECKER #if USE_CHECKER
BaseCPU *temp_checker = p->checker; BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
#if FULL_SYSTEM
checker->setSystem(p->system); checker->setSystem(p->system);
#endif
checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker); checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
thread.tc = checkerTC; thread.tc = checkerTC;
tc = checkerTC; tc = checkerTC;
@ -133,34 +123,36 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
itb = p->itb; itb = p->itb;
dtb = p->dtb; dtb = p->dtb;
#if FULL_SYSTEM
// Setup thread state stuff.
thread.cpu = this;
thread.setTid(0);
thread.quiesceEvent = new EndQuiesceEvent(tc); if (FullSystem) {
// Setup thread state stuff.
thread.cpu = this;
thread.setTid(0);
system = p->system; thread.quiesceEvent = new EndQuiesceEvent(tc);
physmem = p->system->physmem;
if (p->profile) { system = p->system;
thread.profile = new FunctionProfile(p->system->kernelSymtab); physmem = p->system->physmem;
// @todo: This might be better as an ThreadContext instead of OzoneTC
Callback *cb = if (p->profile) {
new MakeCallback<OzoneTC, thread.profile = new FunctionProfile(p->system->kernelSymtab);
&OzoneTC::dumpFuncProfile>(&ozoneTC); // @todo: This might be better as an ThreadContext instead of
registerExitCallback(cb); // OzoneTC
Callback *cb =
new MakeCallback<OzoneTC,
&OzoneTC::dumpFuncProfile>(&ozoneTC);
registerExitCallback(cb);
}
// let's fill with a dummy node for now so we don't get a segfault
// on the first cycle when there's no node available.
static ProfileNode dummyNode;
thread.profileNode = &dummyNode;
thread.profilePC = 3;
} else {
thread.cpu = this;
} }
// let's fill with a dummy node for now so we don't get a segfault
// on the first cycle when there's no node available.
static ProfileNode dummyNode;
thread.profileNode = &dummyNode;
thread.profilePC = 3;
#else
thread.cpu = this;
#endif // !FULL_SYSTEM
numInst = 0; numInst = 0;
startNumInst = 0; startNumInst = 0;
@ -194,25 +186,25 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
frontEnd->renameTable.copyFrom(thread.renameTable); frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable);
#if FULL_SYSTEM if (FullSystem) {
Port *mem_port; Port *mem_port;
FunctionalPort *phys_port; FunctionalPort *phys_port;
VirtualPort *virt_port; VirtualPort *virt_port;
phys_port = new FunctionalPort(csprintf("%s-%d-funcport", phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
name(), 0)); name(), 0));
mem_port = system->physmem->getPort("functional"); mem_port = system->physmem->getPort("functional");
mem_port->setPeer(phys_port); mem_port->setPeer(phys_port);
phys_port->setPeer(mem_port); phys_port->setPeer(mem_port);
virt_port = new VirtualPort(csprintf("%s-%d-vport", virt_port = new VirtualPort(csprintf("%s-%d-vport",
name(), 0)); name(), 0));
mem_port = system->physmem->getPort("functional"); mem_port = system->physmem->getPort("functional");
mem_port->setPeer(virt_port); mem_port->setPeer(virt_port);
virt_port->setPeer(mem_port); virt_port->setPeer(mem_port);
thread.setPhysPort(phys_port); thread.setPhysPort(phys_port);
thread.setVirtPort(virt_port); thread.setVirtPort(virt_port);
#endif }
DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n"); DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
} }
@ -321,10 +313,8 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay)
notIdleFraction++; notIdleFraction++;
scheduleTickEvent(delay); scheduleTickEvent(delay);
_status = Running; _status = Running;
#if FULL_SYSTEM
if (thread.quiesceEvent && thread.quiesceEvent->scheduled()) if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
thread.quiesceEvent->deschedule(); thread.quiesceEvent->deschedule();
#endif
thread.setStatus(ThreadContext::Active); thread.setStatus(ThreadContext::Active);
frontEnd->wakeFromQuiesce(); frontEnd->wakeFromQuiesce();
} }
@ -414,14 +404,14 @@ OzoneCPU<Impl>::init()
// Mark this as in syscall so it won't need to squash // Mark this as in syscall so it won't need to squash
thread.inSyscall = true; thread.inSyscall = true;
#if FULL_SYSTEM if (FullSystem) {
for (int i = 0; i < threadContexts.size(); ++i) { for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i]; ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC // initialize CPU, including PC
TheISA::initCPU(tc, tc->contextId()); TheISA::initCPU(tc, tc->contextId());
}
} }
#endif
frontEnd->renameTable.copyFrom(thread.renameTable); frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable);
@ -480,29 +470,24 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
thread.getTC()->copyArchRegs(temp.getTC()); thread.getTC()->copyArchRegs(temp.getTC());
} }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
Addr Addr
OzoneCPU<Impl>::dbg_vtophys(Addr addr) OzoneCPU<Impl>::dbg_vtophys(Addr addr)
{ {
return vtophys(tc, addr); return vtophys(tc, addr);
} }
#endif // FULL_SYSTEM
#if FULL_SYSTEM
template <class Impl> template <class Impl>
void void
OzoneCPU<Impl>::wakeup() OzoneCPU<Impl>::wakeup()
{ {
if (_status == Idle) { if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n"); DPRINTF(IPI,"Suspended Processor awoke\n");
// thread.activate();
// Hack for now. Otherwise might have to go through the tc, or // Hack for now. Otherwise might have to go through the tc, or
// I need to figure out what's the right thing to call. // I need to figure out what's the right thing to call.
activateContext(thread.threadId(), 1); activateContext(thread.threadId(), 1);
} }
} }
#endif // FULL_SYSTEM
/* start simulation, program loaded, processor precise state initialized */ /* start simulation, program loaded, processor precise state initialized */
template <class Impl> template <class Impl>
@ -535,7 +520,6 @@ OzoneCPU<Impl>::squashFromTC()
backEnd->generateTCEvent(); backEnd->generateTCEvent();
} }
#if !FULL_SYSTEM
template <class Impl> template <class Impl>
void void
OzoneCPU<Impl>::syscall(uint64_t &callnum) OzoneCPU<Impl>::syscall(uint64_t &callnum)
@ -558,7 +542,7 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum)
frontEnd->renameTable.copyFrom(thread.renameTable); frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable);
} }
#else
template <class Impl> template <class Impl>
Fault Fault
OzoneCPU<Impl>::hwrei() OzoneCPU<Impl>::hwrei()
@ -616,7 +600,6 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
return true; return true;
} }
#endif
template <class Impl> template <class Impl>
BaseCPU * BaseCPU *
@ -655,23 +638,19 @@ OzoneCPU<Impl>::OzoneTC::halt()
cpu->haltContext(thread->threadId()); cpu->haltContext(thread->threadId());
} }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
void void
OzoneCPU<Impl>::OzoneTC::dumpFuncProfile() OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
{ {
thread->dumpFuncProfile(); thread->dumpFuncProfile();
} }
#endif
template <class Impl> template <class Impl>
void void
OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context) OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
{ {
// some things should already be set up // some things should already be set up
#if FULL_SYSTEM
assert(getSystemPtr() == old_context->getSystemPtr()); assert(getSystemPtr() == old_context->getSystemPtr());
#endif
assert(getProcessPtr() == old_context->getProcessPtr()); assert(getProcessPtr() == old_context->getProcessPtr());
// copy over functional state // copy over functional state
@ -680,9 +659,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
setCpuId(old_context->cpuId()); setCpuId(old_context->cpuId());
setContextId(old_context->contextId()); setContextId(old_context->contextId());
#if !FULL_SYSTEM
setFuncExeInst(old_context->readFuncExeInst()); setFuncExeInst(old_context->readFuncExeInst());
#else
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
if (other_quiesce) { if (other_quiesce) {
// Point the quiesce event's TC at this TC so that it wakes up // Point the quiesce event's TC at this TC so that it wakes up
@ -706,10 +683,10 @@ template <class Impl>
void void
OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name) OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
{ {
#if FULL_SYSTEM if (FullSystem) {
thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
thread->kernelStats->regStats(name + ".kern"); thread->kernelStats->regStats(name + ".kern");
#endif }
} }
template <class Impl> template <class Impl>
@ -726,7 +703,6 @@ void
OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string &section) OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string &section)
{ } { }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
EndQuiesceEvent * EndQuiesceEvent *
OzoneCPU<Impl>::OzoneTC::getQuiesceEvent() OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
@ -761,7 +737,6 @@ OzoneCPU<Impl>::OzoneTC::profileSample()
{ {
thread->profileSample(); thread->profileSample();
} }
#endif
template <class Impl> template <class Impl>
int int
@ -796,9 +771,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i)); thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
} }
#if !FULL_SYSTEM
thread->funcExeInst = tc->readFuncExeInst(); thread->funcExeInst = tc->readFuncExeInst();
#endif
// Need to copy the TC values into the current rename table, // Need to copy the TC values into the current rename table,
// copy the misc regs. // copy the misc regs.

3
src/cpu/ozone/dyn_inst.hh
View file

@ -214,13 +214,10 @@ class OzoneDynInst : public BaseDynInst<Impl>
void setMiscReg(int misc_reg, const MiscReg &val); void setMiscReg(int misc_reg, const MiscReg &val);
#if FULL_SYSTEM
Fault hwrei(); Fault hwrei();
void trap(Fault fault); void trap(Fault fault);
bool simPalCheck(int palFunc); bool simPalCheck(int palFunc);
#else
void syscall(uint64_t &callnum); void syscall(uint64_t &callnum);
#endif
ListIt iqIt; ListIt iqIt;
bool iqItValid; bool iqItValid;

10
src/cpu/ozone/dyn_inst_impl.hh
View file

@ -31,11 +31,8 @@
#include "config/full_system.hh" #include "config/full_system.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
#include "cpu/ozone/dyn_inst.hh" #include "cpu/ozone/dyn_inst.hh"
#include "sim/faults.hh"
#if FULL_SYSTEM
#include "kern/kernel_stats.hh" #include "kern/kernel_stats.hh"
#endif #include "sim/faults.hh"
template <class Impl> template <class Impl>
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu) OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
@ -239,8 +236,6 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
this->thread->setMiscReg(misc_reg, val); this->thread->setMiscReg(misc_reg, val);
} }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
Fault Fault
OzoneDynInst<Impl>::hwrei() OzoneDynInst<Impl>::hwrei()
@ -269,11 +264,10 @@ OzoneDynInst<Impl>::simPalCheck(int palFunc)
{ {
return this->cpu->simPalCheck(palFunc); return this->cpu->simPalCheck(palFunc);
} }
#else
template <class Impl> template <class Impl>
void void
OzoneDynInst<Impl>::syscall(uint64_t &callnum) OzoneDynInst<Impl>::syscall(uint64_t &callnum)
{ {
this->cpu->syscall(callnum); this->cpu->syscall(callnum);
} }
#endif

6
src/cpu/ozone/front_end_impl.hh
View file

@ -430,13 +430,10 @@ FrontEnd<Impl>::tick()
numInstsReady[0]++; numInstsReady[0]++;
++num_inst; ++num_inst;
#if FULL_SYSTEM
if (inst->isQuiesce()) { if (inst->isQuiesce()) {
// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
status = QuiescePending; status = QuiescePending;
break; break;
} }
#endif
if (inst->predTaken()) { if (inst->predTaken()) {
// Start over with tick? // Start over with tick?
@ -984,9 +981,6 @@ FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
cacheBlkValid = false; cacheBlkValid = false;
#if !FULL_SYSTEM
// pTable = params->pTable;
#endif
fetchFault = NoFault; fetchFault = NoFault;
serializeNext = false; serializeNext = false;
barrierInst = NULL; barrierInst = NULL;

2
src/cpu/ozone/inorder_back_end.hh
View file

@ -73,9 +73,7 @@ class InorderBackEnd
void regStats() { } void regStats() { }
#if FULL_SYSTEM
void checkInterrupts(); void checkInterrupts();
#endif
void tick(); void tick();
void executeInsts(); void executeInsts();

51
src/cpu/ozone/inorder_back_end_impl.hh
View file

@ -79,7 +79,6 @@ InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
thread->setFuncExeInst(0); thread->setFuncExeInst(0);
} }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
void void
InorderBackEnd<Impl>::checkInterrupts() InorderBackEnd<Impl>::checkInterrupts()
@ -134,7 +133,6 @@ InorderBackEnd<Impl>::checkInterrupts()
setSquashInfoFromXC(); setSquashInfoFromXC();
} }
} }
#endif
template <class Impl> template <class Impl>
void void
@ -149,8 +147,7 @@ InorderBackEnd<Impl>::tick()
// if (interrupt) then set thread PC, stall front end, record that // if (interrupt) then set thread PC, stall front end, record that
// I'm waiting for it to drain. (for now just squash) // I'm waiting for it to drain. (for now just squash)
#if FULL_SYSTEM if (FullSystem && (interruptBlocked || cpu->checkInterrupts(tc))) {
if (interruptBlocked || cpu->checkInterrupts(tc)) {
if (!robEmpty()) { if (!robEmpty()) {
interruptBlocked = true; interruptBlocked = true;
//AlphaDep //AlphaDep
@ -165,7 +162,6 @@ InorderBackEnd<Impl>::tick()
return; return;
} }
} }
#endif
if (status != DcacheMissLoadStall && if (status != DcacheMissLoadStall &&
status != DcacheMissStoreStall) { status != DcacheMissStoreStall) {
@ -180,15 +176,11 @@ InorderBackEnd<Impl>::tick()
(*instsAdded)++; (*instsAdded)++;
} }
#if FULL_SYSTEM
if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) { if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
handleFault(); handleFault();
} else { } else {
executeInsts(); executeInsts();
} }
#else
executeInsts();
#endif
} }
} }
@ -209,24 +201,24 @@ InorderBackEnd<Impl>::executeInsts()
thread->setPC(commitPC); thread->setPC(commitPC);
thread->setNextPC(inst->readNextPC()); thread->setNextPC(inst->readNextPC());
#if FULL_SYSTEM if (FullSystem) {
int count = 0; int count = 0;
Addr oldpc; Addr oldpc;
do { do {
if (count == 0) if (count == 0)
assert(!thread->inSyscall && !thread->trapPending); assert(!thread->inSyscall && !thread->trapPending);
oldpc = thread->readPC(); oldpc = thread->readPC();
cpu->system->pcEventQueue.service( cpu->system->pcEventQueue.service(
thread->getXCProxy()); thread->getXCProxy());
count++; count++;
} while (oldpc != thread->readPC()); } while (oldpc != thread->readPC());
if (count > 1) { if (count > 1) {
DPRINTF(IBE, "PC skip function event, stopping commit\n"); DPRINTF(IBE, "PC skip function event, stopping commit\n");
completed_last_inst = false; completed_last_inst = false;
squashPending = true; squashPending = true;
break; break;
}
} }
#endif
Fault inst_fault = NoFault; Fault inst_fault = NoFault;
@ -296,7 +288,6 @@ InorderBackEnd<Impl>::executeInsts()
} }
if (inst_fault != NoFault) { if (inst_fault != NoFault) {
#if FULL_SYSTEM
DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n", DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
inst->seqNum, inst->readPC()); inst->seqNum, inst->readPC());
@ -313,14 +304,8 @@ InorderBackEnd<Impl>::executeInsts()
squashPending = true; squashPending = true;
// Generate trap squash event.
// generateTrapEvent(tid);
completed_last_inst = false; completed_last_inst = false;
break; break;
#else // !FULL_SYSTEM
panic("fault (%d) detected @ PC %08p", inst_fault,
inst->PC);
#endif // FULL_SYSTEM
} }
for (int i = 0; i < inst->numDestRegs(); ++i) { for (int i = 0; i < inst->numDestRegs(); ++i) {

53
src/cpu/ozone/lw_back_end_impl.hh
View file

@ -520,7 +520,6 @@ LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
fromCommit = comm->getWire(-1); fromCommit = comm->getWire(-1);
} }
#if FULL_SYSTEM
template <class Impl> template <class Impl>
void void
LWBackEnd<Impl>::checkInterrupts() LWBackEnd<Impl>::checkInterrupts()
@ -557,7 +556,6 @@ LWBackEnd<Impl>::checkInterrupts()
} }
} }
} }
#endif
template <class Impl> template <class Impl>
void void
@ -604,9 +602,7 @@ LWBackEnd<Impl>::tick()
wbCycle = 0; wbCycle = 0;
#if FULL_SYSTEM
checkInterrupts(); checkInterrupts();
#endif
if (trapSquash) { if (trapSquash) {
assert(!tcSquash); assert(!tcSquash);
@ -1049,16 +1045,8 @@ LWBackEnd<Impl>::commitInst(int inst_num)
(inst->isStoreConditional() && inst->getFault() == NoFault) || (inst->isStoreConditional() && inst->getFault() == NoFault) ||
inst->isMemBarrier() || inst->isMemBarrier() ||
inst->isWriteBarrier()) { inst->isWriteBarrier()) {
#if !FULL_SYSTEM
// Hack to make sure syscalls aren't executed until all stores
// write back their data. This direct communication shouldn't
// be used for anything other than this.
if (inst_num > 0 || LSQ.hasStoresToWB())
#else
if ((inst->isMemBarrier() || inst->isWriteBarrier() || if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
inst->isQuiesce()) && inst->isQuiesce()) && LSQ.hasStoresToWB())
LSQ.hasStoresToWB())
#endif
{ {
DPRINTF(BE, "Waiting for all stores to writeback.\n"); DPRINTF(BE, "Waiting for all stores to writeback.\n");
return false; return false;
@ -1184,11 +1172,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
++freed_regs; ++freed_regs;
} }
#if FULL_SYSTEM if (FullSystem && thread->profile) {
if (thread->profile) {
// bool usermode =
// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
// thread->profilePC = usermode ? 1 : inst->readPC();
thread->profilePC = inst->readPC(); thread->profilePC = inst->readPC();
ProfileNode *node = thread->profile->consume(thread->getTC(), ProfileNode *node = thread->profile->consume(thread->getTC(),
inst->staticInst); inst->staticInst);
@ -1196,7 +1180,6 @@ LWBackEnd<Impl>::commitInst(int inst_num)
if (node) if (node)
thread->profileNode = node; thread->profileNode = node;
} }
#endif
if (inst->traceData) { if (inst->traceData) {
inst->traceData->setFetchSeq(inst->seqNum); inst->traceData->setFetchSeq(inst->seqNum);
@ -1225,23 +1208,23 @@ LWBackEnd<Impl>::commitInst(int inst_num)
toIEW->doneSeqNum = inst->seqNum; toIEW->doneSeqNum = inst->seqNum;
lastCommitCycle = curTick(); lastCommitCycle = curTick();
#if FULL_SYSTEM if (FullSystem) {
int count = 0; int count = 0;
Addr oldpc; Addr oldpc;
do { do {
if (count == 0) if (count == 0)
assert(!thread->inSyscall && !thread->trapPending); assert(!thread->inSyscall && !thread->trapPending);
oldpc = thread->readPC(); oldpc = thread->readPC();
cpu->system->pcEventQueue.service( cpu->system->pcEventQueue.service(
thread->getTC()); thread->getTC());
count++; count++;
} while (oldpc != thread->readPC()); } while (oldpc != thread->readPC());
if (count > 1) { if (count > 1) {
DPRINTF(BE, "PC skip function event, stopping commit\n"); DPRINTF(BE, "PC skip function event, stopping commit\n");
tcSquash = true; tcSquash = true;
return false; return false;
}
} }
#endif
return true; return true;
} }

26
src/cpu/ozone/simple_cpu_builder.cc
View file

@ -60,21 +60,20 @@ SimpleOzoneCPUParams::create()
{ {
SimpleOzoneCPU *cpu; SimpleOzoneCPU *cpu;
#if FULL_SYSTEM if (FullSystem) {
// Full-system only supports a single thread for the moment. // Full-system only supports a single thread for the moment.
ThreadID actual_num_threads = 1; ThreadID actual_num_threads = 1;
#else } else {
// In non-full-system mode, we infer the number of threads from // In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified. // the workload if it's not explicitly specified.
ThreadID actual_num_threads = ThreadID actual_num_threads =
numThreads.isValid() ? numThreads : workload.size(); numThreads.isValid() ? numThreads : workload.size();
if (workload.size() == 0) { if (workload.size() == 0) {
fatal("Must specify at least one workload!"); fatal("Must specify at least one workload!");
}
} }
#endif
SimpleParams *params = new SimpleParams; SimpleParams *params = new SimpleParams;
params->clock = clock; params->clock = clock;
@ -87,10 +86,7 @@ SimpleOzoneCPUParams::create()
params->system = system; params->system = system;
params->cpu_id = cpu_id; params->cpu_id = cpu_id;
#if !FULL_SYSTEM
params->workload = workload; params->workload = workload;
// params->pTable = page_table;
#endif // FULL_SYSTEM
params->mem = mem; params->mem = mem;
params->checker = checker; params->checker = checker;

2
src/cpu/ozone/simple_params.hh
View file

@ -56,9 +56,7 @@ class SimpleParams : public BaseCPU::Params
public: public:
TheISA::TLB *itb; TheISA::TLB *dtb; TheISA::TLB *itb; TheISA::TLB *dtb;
#if !FULL_SYSTEM
std::vector<Process *> workload; std::vector<Process *> workload;
#endif // FULL_SYSTEM
//Page Table //Page Table
PageTable *pTable; PageTable *pTable;

15
src/cpu/ozone/thread_state.hh
View file

@ -45,14 +45,11 @@
class Event; class Event;
//class Process; //class Process;
#if FULL_SYSTEM
class EndQuiesceEvent; class EndQuiesceEvent;
class FunctionProfile;
class ProfileNode;
#else
class Process;
class FunctionalMemory; class FunctionalMemory;
#endif class FunctionProfile;
class Process;
class ProfileNode;
// Maybe this ozone thread state should only really have committed state? // Maybe this ozone thread state should only really have committed state?
// I need to think about why I'm using this and what it's useful for. Clearly // I need to think about why I'm using this and what it's useful for. Clearly
@ -66,7 +63,6 @@ struct OzoneThreadState : public ThreadState {
typedef typename Impl::CPUType CPUType; typedef typename Impl::CPUType CPUType;
typedef TheISA::MiscReg MiscReg; typedef TheISA::MiscReg MiscReg;
#if FULL_SYSTEM
OzoneThreadState(CPUType *_cpu, int _thread_num) OzoneThreadState(CPUType *_cpu, int _thread_num)
: ThreadState(_cpu, -1, _thread_num), : ThreadState(_cpu, -1, _thread_num),
intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0) intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
@ -86,14 +82,13 @@ struct OzoneThreadState : public ThreadState {
profilePC = 3; profilePC = 3;
miscRegFile.clear(); miscRegFile.clear();
} }
#else
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process) OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, -1, _thread_num, _process), : ThreadState(_cpu, -1, _thread_num, _process),
cpu(_cpu), inSyscall(0), trapPending(0) cpu(_cpu), inSyscall(0), trapPending(0)
{ {
miscRegFile.clear(); miscRegFile.clear();
} }
#endif
RenameTable<Impl> renameTable; RenameTable<Impl> renameTable;
@ -147,13 +142,11 @@ struct OzoneThreadState : public ThreadState {
void setNextPC(uint64_t val) void setNextPC(uint64_t val)
{ nextPC = val; } { nextPC = val; }
#if FULL_SYSTEM
void dumpFuncProfile() void dumpFuncProfile()
{ {
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
profile->dump(tc, *os); profile->dump(tc, *os);
} }
#endif
}; };
#endif // __CPU_OZONE_THREAD_STATE_HH__ #endif // __CPU_OZONE_THREAD_STATE_HH__

3
src/cpu/pc_event.cc
View file

@ -36,7 +36,6 @@
#include "base/debug.hh" #include "base/debug.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/pc_event.hh" #include "cpu/pc_event.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
@ -138,7 +137,6 @@ BreakPCEvent::process(ThreadContext *tc)
delete this; delete this;
} }
#if FULL_SYSTEM
void void
sched_break_pc_sys(System *sys, Addr addr) sched_break_pc_sys(System *sys, Addr addr)
{ {
@ -154,4 +152,3 @@ sched_break_pc(Addr addr)
} }
} }
#endif

4
src/cpu/simple/atomic.cc
View file

@ -87,11 +87,9 @@ AtomicSimpleCPU::init()
if (FullSystem) { if (FullSystem) {
ThreadID size = threadContexts.size(); ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) { for (ThreadID i = 0; i < size; ++i) {
#if FULL_SYSTEM
ThreadContext *tc = threadContexts[i]; ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC // initialize CPU, including PC
TheISA::initCPU(tc, tc->contextId()); TheISA::initCPU(tc, tc->contextId());
#endif
} }
} }
if (hasPhysMemPort) { if (hasPhysMemPort) {
@ -618,9 +616,7 @@ AtomicSimpleCPU *
AtomicSimpleCPUParams::create() AtomicSimpleCPUParams::create()
{ {
numThreads = 1; numThreads = 1;
#if !FULL_SYSTEM
if (!FullSystem && workload.size() != 1) if (!FullSystem && workload.size() != 1)
panic("only one workload allowed"); panic("only one workload allowed");
#endif
return new AtomicSimpleCPU(this); return new AtomicSimpleCPU(this);
} }

12
src/cpu/simple/base.cc
View file

@ -73,6 +73,7 @@
#include "params/BaseSimpleCPU.hh" #include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh" #include "sim/byteswap.hh"
#include "sim/debug.hh" #include "sim/debug.hh"
#include "sim/full_system.hh"
#include "sim/sim_events.hh" #include "sim/sim_events.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "sim/stats.hh" #include "sim/stats.hh"
@ -84,12 +85,11 @@ using namespace TheISA;
BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
{ {
#if FULL_SYSTEM if (FullSystem)
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
#else else
thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
p->itb, p->dtb); p->itb, p->dtb);
#endif // !FULL_SYSTEM
thread->setStatus(ThreadContext::Halted); thread->setStatus(ThreadContext::Halted);

4
src/cpu/simple/timing.cc
View file

@ -77,11 +77,9 @@ TimingSimpleCPU::init()
BaseCPU::init(); BaseCPU::init();
if (FullSystem) { if (FullSystem) {
for (int i = 0; i < threadContexts.size(); ++i) { for (int i = 0; i < threadContexts.size(); ++i) {
#if FULL_SYSTEM
ThreadContext *tc = threadContexts[i]; ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC // initialize CPU, including PC
TheISA::initCPU(tc, _cpuId); TheISA::initCPU(tc, _cpuId);
#endif
} }
} }
} }
@ -1009,9 +1007,7 @@ TimingSimpleCPU *
TimingSimpleCPUParams::create() TimingSimpleCPUParams::create()
{ {
numThreads = 1; numThreads = 1;
#if !FULL_SYSTEM
if (!FullSystem && workload.size() != 1) if (!FullSystem && workload.size() != 1)
panic("only one workload allowed"); panic("only one workload allowed");
#endif
return new TimingSimpleCPU(this); return new TimingSimpleCPU(this);
} }

73
src/cpu/simple_thread.cc
View file

@ -50,6 +50,7 @@
#include "mem/translating_port.hh" #include "mem/translating_port.hh"
#include "mem/vport.hh" #include "mem/vport.hh"
#include "params/BaseCPU.hh" #include "params/BaseCPU.hh"
#include "sim/full_system.hh"
#include "sim/process.hh" #include "sim/process.hh"
#include "sim/serialize.hh" #include "sim/serialize.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
@ -58,7 +59,6 @@
using namespace std; using namespace std;
// constructor // constructor
#if !FULL_SYSTEM
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::TLB *_itb, TheISA::TLB *_dtb) TheISA::TLB *_itb, TheISA::TLB *_dtb)
: ThreadState(_cpu, _thread_num, _process), : ThreadState(_cpu, _thread_num, _process),
@ -67,7 +67,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
clearArchRegs(); clearArchRegs();
tc = new ProxyThreadContext<SimpleThread>(this); tc = new ProxyThreadContext<SimpleThread>(this);
} }
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats) bool use_kernel_stats)
@ -98,7 +97,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
if (use_kernel_stats) if (use_kernel_stats)
kernelStats = new TheISA::Kernel::Statistics(system); kernelStats = new TheISA::Kernel::Statistics(system);
} }
#endif
SimpleThread::SimpleThread() SimpleThread::SimpleThread()
: ThreadState(NULL, -1, NULL) : ThreadState(NULL, -1, NULL)
@ -117,28 +115,27 @@ void
SimpleThread::takeOverFrom(ThreadContext *oldContext) SimpleThread::takeOverFrom(ThreadContext *oldContext)
{ {
// some things should already be set up // some things should already be set up
#if FULL_SYSTEM if (FullSystem)
assert(system == oldContext->getSystemPtr()); assert(system == oldContext->getSystemPtr());
#endif
assert(process == oldContext->getProcessPtr()); assert(process == oldContext->getProcessPtr());
copyState(oldContext); copyState(oldContext);
#if FULL_SYSTEM if (FullSystem) {
EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
if (quiesce) { if (quiesce) {
// Point the quiesce event's TC at this TC so that it wakes up // Point the quiesce event's TC at this TC so that it wakes up
// the proper CPU. // the proper CPU.
quiesce->tc = tc; quiesce->tc = tc;
} }
if (quiesceEvent) { if (quiesceEvent) {
quiesceEvent->tc = tc; quiesceEvent->tc = tc;
} }
TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
if (stats) { if (stats) {
kernelStats = stats; kernelStats = stats;
}
} }
#endif
storeCondFailures = 0; storeCondFailures = 0;
@ -150,16 +147,16 @@ SimpleThread::copyTC(ThreadContext *context)
{ {
copyState(context); copyState(context);
#if FULL_SYSTEM if (FullSystem) {
EndQuiesceEvent *quiesce = context->getQuiesceEvent(); EndQuiesceEvent *quiesce = context->getQuiesceEvent();
if (quiesce) { if (quiesce) {
quiesceEvent = quiesce; quiesceEvent = quiesce;
}
TheISA::Kernel::Statistics *stats = context->getKernelStats();
if (stats) {
kernelStats = stats;
}
} }
TheISA::Kernel::Statistics *stats = context->getKernelStats();
if (stats) {
kernelStats = stats;
}
#endif
} }
void void
@ -168,9 +165,8 @@ SimpleThread::copyState(ThreadContext *oldContext)
// copy over functional state // copy over functional state
_status = oldContext->status(); _status = oldContext->status();
copyArchRegs(oldContext); copyArchRegs(oldContext);
#if !FULL_SYSTEM if (FullSystem)
funcExeInst = oldContext->readFuncExeInst(); funcExeInst = oldContext->readFuncExeInst();
#endif
_threadId = oldContext->threadId(); _threadId = oldContext->threadId();
_contextId = oldContext->contextId(); _contextId = oldContext->contextId();
@ -241,15 +237,6 @@ SimpleThread::suspend()
lastActivate = curTick(); lastActivate = curTick();
lastSuspend = curTick(); lastSuspend = curTick();
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->checkInterrupts()) {
assert(status() == ThreadContext::Active);
return;
}
#endif
*/
_status = ThreadContext::Suspended; _status = ThreadContext::Suspended;
cpu->suspendContext(_threadId); cpu->suspendContext(_threadId);
} }
@ -269,10 +256,8 @@ SimpleThread::halt()
void void
SimpleThread::regStats(const string &name) SimpleThread::regStats(const string &name)
{ {
#if FULL_SYSTEM if (FullSystem && kernelStats)
if (kernelStats)
kernelStats->regStats(name + ".kern"); kernelStats->regStats(name + ".kern");
#endif
} }
void void

5
src/cpu/simple_thread.hh
View file

@ -126,14 +126,13 @@ class SimpleThread : public ThreadState
Decoder decoder; Decoder decoder;
// constructor: initialize SimpleThread from given process structure // constructor: initialize SimpleThread from given process structure
#if FULL_SYSTEM // FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats = true); bool use_kernel_stats = true);
#else // SE
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::TLB *_itb, TheISA::TLB *_dtb); TheISA::TLB *_itb, TheISA::TLB *_dtb);
#endif
SimpleThread(); SimpleThread();

47
src/cpu/thread_state.cc
View file

@ -28,29 +28,24 @@
* Authors: Kevin Lim * Authors: Kevin Lim
*/ */
#include "arch/kernel_stats.hh"
#include "base/output.hh" #include "base/output.hh"
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/profile.hh" #include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/thread_state.hh" #include "cpu/thread_state.hh"
#include "mem/port.hh" #include "mem/port.hh"
#include "mem/translating_port.hh" #include "mem/translating_port.hh"
#include "mem/vport.hh" #include "mem/vport.hh"
#include "sim/full_system.hh"
#include "sim/serialize.hh" #include "sim/serialize.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#include "cpu/quiesce_event.hh"
#endif
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
: numInst(0), numLoad(0), _status(ThreadContext::Halted), : numInst(0), numLoad(0), _status(ThreadContext::Halted),
baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0), baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
#if FULL_SYSTEM
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
kernelStats(NULL), kernelStats(NULL), process(_process), port(NULL), virtPort(NULL),
#endif physPort(NULL), funcExeInst(0), storeCondFailures(0)
process(_process), port(NULL), virtPort(NULL), physPort(NULL),
funcExeInst(0), storeCondFailures(0)
{ {
} }
@ -69,14 +64,14 @@ ThreadState::serialize(std::ostream &os)
// thread_num and cpu_id are deterministic from the config // thread_num and cpu_id are deterministic from the config
SERIALIZE_SCALAR(funcExeInst); SERIALIZE_SCALAR(funcExeInst);
#if FULL_SYSTEM if (FullSystem) {
Tick quiesceEndTick = 0; Tick quiesceEndTick = 0;
if (quiesceEvent->scheduled()) if (quiesceEvent->scheduled())
quiesceEndTick = quiesceEvent->when(); quiesceEndTick = quiesceEvent->when();
SERIALIZE_SCALAR(quiesceEndTick); SERIALIZE_SCALAR(quiesceEndTick);
if (kernelStats) if (kernelStats)
kernelStats->serialize(os); kernelStats->serialize(os);
#endif }
} }
void void
@ -87,14 +82,14 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
// thread_num and cpu_id are deterministic from the config // thread_num and cpu_id are deterministic from the config
UNSERIALIZE_SCALAR(funcExeInst); UNSERIALIZE_SCALAR(funcExeInst);
#if FULL_SYSTEM if (FullSystem) {
Tick quiesceEndTick; Tick quiesceEndTick;
UNSERIALIZE_SCALAR(quiesceEndTick); UNSERIALIZE_SCALAR(quiesceEndTick);
if (quiesceEndTick) if (quiesceEndTick)
baseCpu->schedule(quiesceEvent, quiesceEndTick); baseCpu->schedule(quiesceEvent, quiesceEndTick);
if (kernelStats) if (kernelStats)
kernelStats->unserialize(cp, section); kernelStats->unserialize(cp, section);
#endif }
} }
void void