updated tsunami_dma
dev/tsunami_dma.cc: decide actually differentiating between the different i/o requests would be a better idea dev/tsunami_dma.hh: added mask and mode variables, incase they are needed dev/tsunamireg.h: added some i/o port defs --HG-- extra : convert_revision : 5c7a88a8f8c8725359737b399cfa80610149a5f4
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0e805e1ff3
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3 changed files with 51 additions and 2 deletions
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@ -39,7 +39,8 @@ TsunamiDMA::read(MemReqPtr req, uint8_t *data)
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// Addr daddr = (req->paddr & addr_mask) >> 6;
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// ExecContext *xc = req->xc;
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// int cpuid = xc->cpu_id;
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*(uint64_t*)data = 0x00;
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panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
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// *(uint64_t*)data = 0x00;
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return No_Fault;
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}
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@ -50,7 +51,40 @@ TsunamiDMA::write(MemReqPtr req, const uint8_t *data)
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DPRINTF(Tsunami, "dma write - va=%#x size=%d IOPort=%#x\n",
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req->vaddr, req->size, req->vaddr & 0xfff);
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//Addr daddr = (req->paddr & addr_mask) >> 6;
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Addr daddr = (req->paddr & addr_mask);
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switch(req->size) {
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case sizeof(uint8_t):
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switch(daddr) {
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case TSDEV_PIC1_MASK:
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mask1 = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_PIC2_MASK:
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mask2 = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_DMA1_RESET:
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return No_Fault;
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case TSDEV_DMA2_RESET:
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return No_Fault;
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case TSDEV_DMA1_MODE:
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mode1 = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_DMA2_MODE:
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mode2 = *(uint8_t*)data;
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return No_Fault;
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case TSDEV_DMA1_MASK:
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case TSDEV_DMA2_MASK:
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return No_Fault;
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default:
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panic("I/O Write - va%#x size %d\n", req->vaddr, req->size);
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}
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case sizeof(uint16_t):
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case sizeof(uint32_t):
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case sizeof(uint64_t):
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default:
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panic("I/O Write - invalid size - va %#x size %d\n", req->vaddr, req->size);
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}
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return No_Fault;
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}
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@ -45,6 +45,11 @@ class TsunamiDMA : public MmapDevice
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protected:
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uint8_t mask1;
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uint8_t mask2;
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uint8_t mode1;
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uint8_t mode2;
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public:
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TsunamiDMA(const std::string &name, /*Tsunami *t,*/
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Addr addr, Addr mask, MemoryController *mmu);
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@ -65,4 +65,14 @@
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#define TSDEV_DC_DREV 0x22
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#define TSDEV_DC_DSC2 0x23
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// I/O Ports
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#define TSDEV_PIC1_MASK 0x21
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#define TSDEV_PIC2_MASK 0xA1
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#define TSDEV_DMA1_RESET 0x0D
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#define TSDEV_DMA2_RESET 0xDA
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#define TSDEV_DMA1_MODE 0x0B
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#define TSDEV_DMA2_MODE 0xD6
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#define TSDEV_DMA1_MASK 0x0A
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#define TSDEV_DMA2_MASK 0xD4
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#endif // __TSUNAMIREG_H__
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