get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
This commit is contained in:
parent
d857faf073
commit
dd99ff23c6
20 changed files with 112 additions and 106 deletions
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@ -196,7 +196,7 @@ def format MT_Control(code, *opt_flags) {{
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def format MT_MFTR(code, *flags) {{
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flags += ('IsNonSpeculative', )
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# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
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# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
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code += 'if (MT_H == 1) {\n'
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code += 'data = bits(data, top_bit, bottom_bit);\n'
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@ -212,7 +212,7 @@ def format MT_MFTR(code, *flags) {{
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def format MT_MTTR(code, *flags) {{
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flags += ('IsNonSpeculative', )
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# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
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# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
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iop = InstObjParams(name, Name, 'MTOp', code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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@ -52,7 +52,7 @@ handleLockedRead(XC *xc, Request *req)
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xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
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xc->setMiscRegNoEffect(LLFlag, true);
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DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
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req->getThreadNum(), req->getPaddr() & ~0xf);
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req->threadId(), req->getPaddr() & ~0xf);
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}
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@ -94,10 +94,10 @@ handleLockedWrite(XC *xc, Request *req)
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if (!lock_flag){
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DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
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req->getThreadNum());
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req->threadId());
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} else if ((req->getPaddr() & ~0xf) != lock_addr) {
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DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
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req->getThreadNum());
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req->threadId());
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}
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// store conditional failed already, so don't issue it to mem
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return false;
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@ -78,7 +78,7 @@ haltThread(TC *tc)
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// @TODO: Needs to check if this is a branch and if so, take previous instruction
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tc->setMiscReg(TCRestart, tc->readNextPC());
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warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
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warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
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tc->readPC(), tc->readNextPC());
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}
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}
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@ -98,7 +98,7 @@ restoreThread(TC *tc)
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tc->setNextNPC(pc + 8);
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tc->activate(0);
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warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
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warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
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tc->readPC());
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}
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}
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@ -217,7 +217,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
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if (ok == 1) {
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unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
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tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
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warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->getThreadNum());
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warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
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}
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} else if (src_reg > 0) {
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if (src_reg && !yield_mask != 0) {
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@ -238,7 +238,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
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fault = new ThreadFault();
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} else {
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//tc->ScheduleOtherThreads();
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//std::cerr << "T" << tc->getThreadNum() << "YIELD: Schedule Other Threads.\n" << std::endl;
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//std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
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//tc->suspend();
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// Save last known PC in TCRestart
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// @TODO: Needs to check if this is a branch and if so, take previous instruction
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@ -259,7 +259,7 @@ zeroRegisters(CPU *cpu)
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void
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startupCPU(ThreadContext *tc, int cpuId)
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{
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tc->activate(0/*tc->getThreadNum()*/);
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tc->activate(0/*tc->threadId()*/);
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}
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} // namespace MipsISA
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@ -329,6 +329,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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CpuEvent::replaceThreadContext(oldTC, newTC);
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assert(newTC->contextId() == oldTC->contextId());
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assert(newTC->threadId() == oldTC->threadId());
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system->replaceThreadContext(newTC, newTC->contextId());
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if (DTRACE(Context))
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@ -153,7 +153,7 @@ class CheckerThreadContext : public ThreadContext
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void profileSample() { return actualTC->profileSample(); }
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#endif
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int getThreadNum() { return actualTC->getThreadNum(); }
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int threadId() { return actualTC->threadId(); }
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// @todo: Do I need this?
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MachInst getInst() { return actualTC->getInst(); }
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@ -59,7 +59,7 @@ Trace::ExeTracerRecord::dump()
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outs << (misspeculating ? "-" : "+") << " ";
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if (IsOn(ExecThread))
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outs << "T" << thread->getThreadNum() << " : ";
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outs << "T" << thread->threadId() << " : ";
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std::string sym_str;
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@ -82,6 +82,10 @@ class O3ThreadContext : public ThreadContext
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virtual void setContextId(int id) { thread->setContextId(id); }
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/** Returns this thread's ID number. */
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virtual int threadId() { return thread->threadId(); }
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virtual void setThreadId(int id) { return thread->setThreadId(id); }
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#if FULL_SYSTEM
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/** Returns a pointer to the system. */
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virtual System *getSystemPtr() { return cpu->system; }
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@ -152,9 +156,6 @@ class O3ThreadContext : public ThreadContext
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/** Samples the function profiling information. */
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virtual void profileSample();
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#endif
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/** Returns this thread's ID number. */
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virtual int getThreadNum() { return thread->readTid(); }
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/** Returns the instruction this thread is currently committing.
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* Only used when an instruction faults.
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*/
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@ -190,36 +191,36 @@ class O3ThreadContext : public ThreadContext
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/** Reads this thread's PC. */
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virtual uint64_t readPC()
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{ return cpu->readPC(thread->readTid()); }
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{ return cpu->readPC(thread->threadId()); }
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/** Sets this thread's PC. */
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virtual void setPC(uint64_t val);
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/** Reads this thread's next PC. */
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virtual uint64_t readNextPC()
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{ return cpu->readNextPC(thread->readTid()); }
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{ return cpu->readNextPC(thread->threadId()); }
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/** Sets this thread's next PC. */
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virtual void setNextPC(uint64_t val);
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virtual uint64_t readMicroPC()
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{ return cpu->readMicroPC(thread->readTid()); }
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{ return cpu->readMicroPC(thread->threadId()); }
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virtual void setMicroPC(uint64_t val);
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virtual uint64_t readNextMicroPC()
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{ return cpu->readNextMicroPC(thread->readTid()); }
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{ return cpu->readNextMicroPC(thread->threadId()); }
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virtual void setNextMicroPC(uint64_t val);
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/** Reads a miscellaneous register. */
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virtual MiscReg readMiscRegNoEffect(int misc_reg)
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{ return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
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{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
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/** Reads a misc. register, including any side-effects the
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* read might have as defined by the architecture. */
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virtual MiscReg readMiscReg(int misc_reg)
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{ return cpu->readMiscReg(misc_reg, thread->readTid()); }
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{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
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/** Sets a misc. register. */
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virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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@ -257,7 +258,7 @@ class O3ThreadContext : public ThreadContext
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/** Executes a syscall in SE mode. */
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virtual void syscall(int64_t callnum)
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{ return cpu->syscall(callnum, thread->readTid()); }
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{ return cpu->syscall(callnum, thread->threadId()); }
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/** Reads the funcExeInst counter. */
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virtual Counter readFuncExeInst() { return thread->funcExeInst; }
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@ -271,7 +272,7 @@ class O3ThreadContext : public ThreadContext
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virtual uint64_t readNextNPC()
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{
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return this->cpu->readNextNPC(this->thread->readTid());
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return this->cpu->readNextNPC(this->thread->threadId());
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}
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virtual void setNextNPC(uint64_t val)
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@ -279,7 +280,7 @@ class O3ThreadContext : public ThreadContext
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#if THE_ISA == ALPHA_ISA
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panic("Not supported on Alpha!");
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#endif
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this->cpu->setNextNPC(val, this->thread->readTid());
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this->cpu->setNextNPC(val, this->thread->threadId());
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}
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/** This function exits the thread context in the CPU and returns
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@ -64,6 +64,7 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
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setStatus(old_context->status());
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copyArchRegs(old_context);
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setContextId(old_context->contextId());
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setThreadId(old_context->threadId());
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#if !FULL_SYSTEM
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thread->funcExeInst = old_context->readFuncExeInst();
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@ -95,7 +96,7 @@ void
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O3ThreadContext<Impl>::activate(int delay)
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{
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DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
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getThreadNum());
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threadId());
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if (thread->status() == ThreadContext::Active)
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return;
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#endif
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if (thread->status() == ThreadContext::Unallocated) {
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cpu->activateWhenReady(thread->readTid());
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cpu->activateWhenReady(thread->threadId());
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return;
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}
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thread->setStatus(ThreadContext::Active);
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// status() == Suspended
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cpu->activateContext(thread->readTid(), delay);
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cpu->activateContext(thread->threadId(), delay);
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}
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template <class Impl>
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O3ThreadContext<Impl>::suspend(int delay)
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{
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DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
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getThreadNum());
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threadId());
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if (thread->status() == ThreadContext::Suspended)
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return;
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@ -139,7 +140,7 @@ O3ThreadContext<Impl>::suspend(int delay)
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#endif
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*/
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thread->setStatus(ThreadContext::Suspended);
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cpu->suspendContext(thread->readTid());
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cpu->suspendContext(thread->threadId());
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}
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template <class Impl>
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@ -147,13 +148,13 @@ void
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O3ThreadContext<Impl>::deallocate(int delay)
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{
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DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n",
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getThreadNum(), delay);
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threadId(), delay);
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if (thread->status() == ThreadContext::Unallocated)
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return;
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thread->setStatus(ThreadContext::Unallocated);
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cpu->deallocateContext(thread->readTid(), true, delay);
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cpu->deallocateContext(thread->threadId(), true, delay);
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}
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template <class Impl>
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@ -161,13 +162,13 @@ void
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O3ThreadContext<Impl>::halt(int delay)
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{
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DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
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getThreadNum());
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threadId());
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if (thread->status() == ThreadContext::Halted)
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return;
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thread->setStatus(ThreadContext::Halted);
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cpu->haltContext(thread->readTid());
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cpu->haltContext(thread->threadId());
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}
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template <class Impl>
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@ -245,7 +246,7 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
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{
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// This function will mess things up unless the ROB is empty and
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// there are no instructions in the pipeline.
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unsigned tid = thread->readTid();
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unsigned tid = thread->threadId();
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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@ -292,7 +293,7 @@ uint64_t
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O3ThreadContext<Impl>::readIntReg(int reg_idx)
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{
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reg_idx = TheISA::flattenIntIndex(this, reg_idx);
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return cpu->readArchIntReg(reg_idx, thread->readTid());
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return cpu->readArchIntReg(reg_idx, thread->threadId());
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}
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template <class Impl>
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@ -302,9 +303,9 @@ O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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switch(width) {
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case 32:
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return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
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return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
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case 64:
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return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
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return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
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default:
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panic("Unsupported width!");
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return 0;
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@ -316,7 +317,7 @@ TheISA::FloatReg
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O3ThreadContext<Impl>::readFloatReg(int reg_idx)
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{
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
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return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
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}
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template <class Impl>
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@ -325,7 +326,7 @@ O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
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{
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DPRINTF(Fault, "Reading floatint register through the TC!\n");
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
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return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
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}
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template <class Impl>
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@ -333,7 +334,7 @@ TheISA::FloatRegBits
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O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
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{
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
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return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
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}
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template <class Impl>
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@ -341,11 +342,11 @@ void
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O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
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{
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reg_idx = TheISA::flattenIntIndex(this, reg_idx);
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cpu->setArchIntReg(reg_idx, val, thread->readTid());
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cpu->setArchIntReg(reg_idx, val, thread->threadId());
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// Squash if we're not already in a state update mode.
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromTC(thread->readTid());
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cpu->squashFromTC(thread->threadId());
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}
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}
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@ -356,16 +357,16 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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switch(width) {
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case 32:
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cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
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cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
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break;
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case 64:
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cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
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cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
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break;
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}
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// Squash if we're not already in a state update mode.
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromTC(thread->readTid());
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cpu->squashFromTC(thread->threadId());
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}
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}
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@ -374,10 +375,10 @@ void
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O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
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{
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
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cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromTC(thread->readTid());
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cpu->squashFromTC(thread->threadId());
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}
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}
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@ -388,11 +389,11 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
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{
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DPRINTF(Fault, "Setting floatint register through the TC!\n");
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
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cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
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// Squash if we're not already in a state update mode.
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if (!thread->trapPending && !thread->inSyscall) {
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cpu->squashFromTC(thread->readTid());
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cpu->squashFromTC(thread->threadId());
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}
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}
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@ -401,11 +402,11 @@ void
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O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
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{
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reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
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cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
|
||||
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -413,11 +414,11 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setPC(uint64_t val)
|
||||
{
|
||||
cpu->setPC(val, thread->readTid());
|
||||
cpu->setPC(val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -425,11 +426,11 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setNextPC(uint64_t val)
|
||||
{
|
||||
cpu->setNextPC(val, thread->readTid());
|
||||
cpu->setNextPC(val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -437,11 +438,11 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setMicroPC(uint64_t val)
|
||||
{
|
||||
cpu->setMicroPC(val, thread->readTid());
|
||||
cpu->setMicroPC(val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -449,11 +450,11 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
|
||||
{
|
||||
cpu->setNextMicroPC(val, thread->readTid());
|
||||
cpu->setNextMicroPC(val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -461,11 +462,11 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
|
||||
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -474,11 +475,11 @@ void
|
|||
O3ThreadContext<Impl>::setMiscReg(int misc_reg,
|
||||
const MiscReg &val)
|
||||
{
|
||||
cpu->setMiscReg(misc_reg, val, thread->readTid());
|
||||
cpu->setMiscReg(misc_reg, val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
cpu->squashFromTC(thread->readTid());
|
||||
cpu->squashFromTC(thread->threadId());
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -488,21 +489,21 @@ template <class Impl>
|
|||
TheISA::IntReg
|
||||
O3ThreadContext<Impl>::getSyscallArg(int i)
|
||||
{
|
||||
return cpu->getSyscallArg(i, thread->readTid());
|
||||
return cpu->getSyscallArg(i, thread->threadId());
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
|
||||
{
|
||||
cpu->setSyscallArg(i, val, thread->readTid());
|
||||
cpu->setSyscallArg(i, val, thread->threadId());
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
|
||||
{
|
||||
cpu->setSyscallReturn(return_value, thread->readTid());
|
||||
cpu->setSyscallReturn(return_value, thread->threadId());
|
||||
}
|
||||
|
||||
#endif // FULL_SYSTEM
|
||||
|
|
|
@ -176,7 +176,7 @@ class OzoneCPU : public BaseCPU
|
|||
void profileSample();
|
||||
#endif
|
||||
|
||||
int getThreadNum();
|
||||
int threadId();
|
||||
|
||||
// Also somewhat obnoxious. Really only used for the TLB fault.
|
||||
TheISA::MachInst getInst();
|
||||
|
@ -260,7 +260,7 @@ class OzoneCPU : public BaseCPU
|
|||
}
|
||||
|
||||
void setSyscallReturn(SyscallReturn return_value)
|
||||
{ cpu->setSyscallReturn(return_value, thread->readTid()); }
|
||||
{ cpu->setSyscallReturn(return_value, thread->threadId()); }
|
||||
|
||||
Counter readFuncExeInst() { return thread->funcExeInst; }
|
||||
|
||||
|
|
|
@ -588,7 +588,7 @@ OzoneCPU<Impl>::postInterrupt(int int_num, int index)
|
|||
// thread.activate();
|
||||
// Hack for now. Otherwise might have to go through the tc, or
|
||||
// I need to figure out what's the right thing to call.
|
||||
activateContext(thread.readTid(), 1);
|
||||
activateContext(thread.threadId(), 1);
|
||||
}
|
||||
}
|
||||
#endif // FULL_SYSTEM
|
||||
|
@ -711,7 +711,7 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
|
|||
|
||||
switch (palFunc) {
|
||||
case PAL::halt:
|
||||
haltContext(thread.readTid());
|
||||
haltContext(thread.threadId());
|
||||
if (--System::numSystemsRunning == 0)
|
||||
exitSimLoop("all cpus halted");
|
||||
break;
|
||||
|
@ -745,7 +745,7 @@ template <class Impl>
|
|||
void
|
||||
OzoneCPU<Impl>::OzoneTC::activate(int delay)
|
||||
{
|
||||
cpu->activateContext(thread->readTid(), delay);
|
||||
cpu->activateContext(thread->threadId(), delay);
|
||||
}
|
||||
|
||||
/// Set the status to Suspended.
|
||||
|
@ -753,7 +753,7 @@ template <class Impl>
|
|||
void
|
||||
OzoneCPU<Impl>::OzoneTC::suspend()
|
||||
{
|
||||
cpu->suspendContext(thread->readTid());
|
||||
cpu->suspendContext(thread->threadId());
|
||||
}
|
||||
|
||||
/// Set the status to Unallocated.
|
||||
|
@ -761,7 +761,7 @@ template <class Impl>
|
|||
void
|
||||
OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
|
||||
{
|
||||
cpu->deallocateContext(thread->readTid(), delay);
|
||||
cpu->deallocateContext(thread->threadId(), delay);
|
||||
}
|
||||
|
||||
/// Set the status to Halted.
|
||||
|
@ -769,7 +769,7 @@ template <class Impl>
|
|||
void
|
||||
OzoneCPU<Impl>::OzoneTC::halt()
|
||||
{
|
||||
cpu->haltContext(thread->readTid());
|
||||
cpu->haltContext(thread->threadId());
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
|
@ -884,9 +884,9 @@ OzoneCPU<Impl>::OzoneTC::profileSample()
|
|||
|
||||
template <class Impl>
|
||||
int
|
||||
OzoneCPU<Impl>::OzoneTC::getThreadNum()
|
||||
OzoneCPU<Impl>::OzoneTC::threadId()
|
||||
{
|
||||
return thread->readTid();
|
||||
return thread->threadId();
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
|
|
@ -183,6 +183,7 @@ SimpleThread::copyState(ThreadContext *oldContext)
|
|||
#endif
|
||||
inst = oldContext->getInst();
|
||||
|
||||
_threadId = oldContext->threadId();
|
||||
_contextId = oldContext->contextId();
|
||||
}
|
||||
|
||||
|
@ -221,14 +222,14 @@ SimpleThread::activate(int delay)
|
|||
lastActivate = curTick;
|
||||
|
||||
// if (status() == ThreadContext::Unallocated) {
|
||||
// cpu->activateWhenReady(tid);
|
||||
// cpu->activateWhenReady(_threadId);
|
||||
// return;
|
||||
// }
|
||||
|
||||
_status = ThreadContext::Active;
|
||||
|
||||
// status() == Suspended
|
||||
cpu->activateContext(tid, delay);
|
||||
cpu->activateContext(_threadId, delay);
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -249,7 +250,7 @@ SimpleThread::suspend()
|
|||
#endif
|
||||
*/
|
||||
_status = ThreadContext::Suspended;
|
||||
cpu->suspendContext(tid);
|
||||
cpu->suspendContext(_threadId);
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -259,7 +260,7 @@ SimpleThread::deallocate()
|
|||
return;
|
||||
|
||||
_status = ThreadContext::Unallocated;
|
||||
cpu->deallocateContext(tid);
|
||||
cpu->deallocateContext(_threadId);
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -269,7 +270,7 @@ SimpleThread::halt()
|
|||
return;
|
||||
|
||||
_status = ThreadContext::Halted;
|
||||
cpu->haltContext(tid);
|
||||
cpu->haltContext(_threadId);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -197,8 +197,6 @@ class SimpleThread : public ThreadState
|
|||
|
||||
BaseCPU *getCpuPtr() { return cpu; }
|
||||
|
||||
int getThreadNum() { return tid; }
|
||||
|
||||
TheISA::ITB *getITBPtr() { return itb; }
|
||||
|
||||
TheISA::DTB *getDTBPtr() { return dtb; }
|
||||
|
|
|
@ -117,7 +117,9 @@ class ThreadContext
|
|||
|
||||
virtual int cpuId() = 0;
|
||||
|
||||
virtual int getThreadNum() = 0;
|
||||
virtual int threadId() = 0;
|
||||
|
||||
virtual void setThreadId(int id) = 0;
|
||||
|
||||
virtual int contextId() = 0;
|
||||
|
||||
|
@ -304,7 +306,9 @@ class ProxyThreadContext : public ThreadContext
|
|||
|
||||
int cpuId() { return actualTC->cpuId(); }
|
||||
|
||||
int getThreadNum() { return actualTC->getThreadNum(); }
|
||||
int threadId() { return actualTC->threadId(); }
|
||||
|
||||
void setThreadId(int id) { return actualTC->setThreadId(id); }
|
||||
|
||||
int contextId() { return actualTC->contextId(); }
|
||||
|
||||
|
|
|
@ -44,14 +44,14 @@
|
|||
|
||||
#if FULL_SYSTEM
|
||||
ThreadState::ThreadState(BaseCPU *cpu, int _tid)
|
||||
: baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
|
||||
: baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
|
||||
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
|
||||
kernelStats(NULL), physPort(NULL), virtPort(NULL),
|
||||
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
|
||||
#else
|
||||
ThreadState::ThreadState(BaseCPU *cpu, int _tid, Process *_process,
|
||||
short _asid)
|
||||
: baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
|
||||
: baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
|
||||
port(NULL), process(_process), asid(_asid),
|
||||
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
|
||||
#endif
|
||||
|
@ -129,7 +129,7 @@ ThreadState::connectPhysPort()
|
|||
physPort->removeConn();
|
||||
else
|
||||
physPort = new FunctionalPort(csprintf("%s-%d-funcport",
|
||||
baseCpu->name(), tid));
|
||||
baseCpu->name(), _threadId));
|
||||
connectToMemFunc(physPort);
|
||||
}
|
||||
|
||||
|
@ -143,7 +143,7 @@ ThreadState::connectVirtPort(ThreadContext *tc)
|
|||
virtPort->removeConn();
|
||||
else
|
||||
virtPort = new VirtualPort(csprintf("%s-%d-vport",
|
||||
baseCpu->name(), tid), tc);
|
||||
baseCpu->name(), _threadId), tc);
|
||||
connectToMemFunc(virtPort);
|
||||
}
|
||||
|
||||
|
@ -169,7 +169,7 @@ ThreadState::getMemPort()
|
|||
return port;
|
||||
|
||||
/* Use this port to for syscall emulation writes to memory. */
|
||||
port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid),
|
||||
port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), _threadId),
|
||||
process, TranslatingPort::NextPage);
|
||||
|
||||
connectToMemFunc(port);
|
||||
|
|
|
@ -84,9 +84,9 @@ struct ThreadState {
|
|||
|
||||
void setContextId(int id) { _contextId = id; }
|
||||
|
||||
void setTid(int id) { tid = id; }
|
||||
void setThreadId(int id) { _threadId = id; }
|
||||
|
||||
int readTid() { return tid; }
|
||||
int threadId() { return _threadId; }
|
||||
|
||||
Tick readLastActivate() { return lastActivate; }
|
||||
|
||||
|
@ -177,7 +177,7 @@ struct ThreadState {
|
|||
int _contextId;
|
||||
|
||||
// Index of hardware thread context on the CPU that this represents.
|
||||
int tid;
|
||||
int _threadId;
|
||||
|
||||
public:
|
||||
/** Last time activate was called on this thread. */
|
||||
|
|
2
src/mem/cache/base.hh
vendored
2
src/mem/cache/base.hh
vendored
|
@ -481,7 +481,7 @@ class BaseCache : public MemObject
|
|||
|
||||
void incMissCount(PacketPtr pkt)
|
||||
{
|
||||
misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
|
||||
|
||||
if (missCount) {
|
||||
--missCount;
|
||||
|
|
20
src/mem/cache/cache_impl.hh
vendored
20
src/mem/cache/cache_impl.hh
vendored
|
@ -296,7 +296,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
|
|||
|
||||
if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) {
|
||||
// OK to satisfy access
|
||||
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
|
||||
satisfyCpuSideRequest(pkt, blk);
|
||||
return true;
|
||||
}
|
||||
|
@ -325,7 +325,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
|
|||
blk->status |= BlkDirty;
|
||||
// nothing else to do; writeback doesn't expect response
|
||||
assert(!pkt->needsResponse());
|
||||
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
@ -467,8 +467,8 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
|
|||
if (mshr) {
|
||||
// MSHR hit
|
||||
//@todo remove hw_pf here
|
||||
mshr_hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
if (mshr->threadNum != 0/*pkt->req->getThreadNum()*/) {
|
||||
mshr_hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
|
||||
if (mshr->threadNum != 0/*pkt->req->threadId()*/) {
|
||||
mshr->threadNum = -1;
|
||||
}
|
||||
mshr->allocateTarget(pkt, time, order++);
|
||||
|
@ -482,7 +482,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
|
|||
}
|
||||
} else {
|
||||
// no MSHR
|
||||
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
|
||||
// always mark as cache fill for now... if we implement
|
||||
// no-write-allocate or bypass accesses this will have to
|
||||
// be changed.
|
||||
|
@ -740,10 +740,10 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
PacketList writebacks;
|
||||
|
||||
if (pkt->req->isUncacheable()) {
|
||||
mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->getThreadNum()*/] +=
|
||||
mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
|
||||
miss_latency;
|
||||
} else {
|
||||
mshr_miss_latency[stats_cmd_idx][0/*pkt->req->getThreadNum()*/] +=
|
||||
mshr_miss_latency[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
|
||||
miss_latency;
|
||||
}
|
||||
|
||||
|
@ -784,7 +784,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
|
|||
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
|
||||
|
||||
assert(!target->pkt->req->isUncacheable());
|
||||
missLatency[target->pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] +=
|
||||
missLatency[target->pkt->cmdToIndex()][0/*pkt->req->threadId()*/] +=
|
||||
completion_time - target->recvTime;
|
||||
} else {
|
||||
// not a cache fill, just forwarding response
|
||||
|
@ -862,7 +862,7 @@ Cache<TagStore>::writebackBlk(BlkType *blk)
|
|||
{
|
||||
assert(blk && blk->isValid() && blk->isDirty());
|
||||
|
||||
writebacks[0/*pkt->req->getThreadNum()*/]++;
|
||||
writebacks[0/*pkt->req->threadId()*/]++;
|
||||
|
||||
Request *writebackReq =
|
||||
new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
|
||||
|
@ -1261,7 +1261,7 @@ Cache<TagStore>::getNextMSHR()
|
|||
if (pkt) {
|
||||
// Update statistic on number of prefetches issued
|
||||
// (hwpf_mshr_misses)
|
||||
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
|
||||
// Don't request bus, since we already have it
|
||||
return allocateMissBuffer(pkt, curTick, false);
|
||||
}
|
||||
|
|
2
src/mem/cache/mshr_queue.cc
vendored
2
src/mem/cache/mshr_queue.cc
vendored
|
@ -230,7 +230,7 @@ MSHRQueue::squash(int threadNum)
|
|||
if (mshr->threadNum == threadNum) {
|
||||
while (mshr->hasTargets()) {
|
||||
mshr->popTarget();
|
||||
assert(0/*target->req->getThreadNum()*/ == threadNum);
|
||||
assert(0/*target->req->threadId()*/ == threadNum);
|
||||
}
|
||||
assert(!mshr->hasTargets());
|
||||
assert(mshr->ntargets==0);
|
||||
|
|
Loading…
Reference in a new issue