get rid of all instances of readTid() and getThreadNum(). Unify and eliminate

redundancies with threadId() as their replacement.

src/arch/mips/isa/formats/mt.isa

@@ -196,7 +196,7 @@ def format MT_Control(code, *opt_flags) {{
 
 def format MT_MFTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
-#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 
         code += 'if (MT_H == 1) {\n'
         code += 'data = bits(data, top_bit, bottom_bit);\n'
@@ -212,7 +212,7 @@ def format MT_MFTR(code, *flags) {{
 
 def format MT_MTTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
-#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
         iop = InstObjParams(name, Name, 'MTOp', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)

src/arch/mips/locked_mem.hh

@@ -52,7 +52,7 @@ handleLockedRead(XC *xc, Request *req)
     xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
     xc->setMiscRegNoEffect(LLFlag, true);
     DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
-            req->getThreadNum(), req->getPaddr() & ~0xf);
+            req->threadId(), req->getPaddr() & ~0xf);
 }
 
 
@@ -94,10 +94,10 @@ handleLockedWrite(XC *xc, Request *req)
 
             if (!lock_flag){
                 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
-                        req->getThreadNum());
+                        req->threadId());
             } else if ((req->getPaddr() & ~0xf) != lock_addr) {
                 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
-                        req->getThreadNum());
+                        req->threadId());
             }
             // store conditional failed already, so don't issue it to mem
             return false;

src/arch/mips/mt.hh

@@ -78,7 +78,7 @@ haltThread(TC *tc)
         // @TODO: Needs to check if this is a branch and if so, take previous instruction
         tc->setMiscReg(TCRestart, tc->readNextPC());
 
-        warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
+        warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
              tc->readPC(), tc->readNextPC());
     }
 }
@@ -98,7 +98,7 @@ restoreThread(TC *tc)
         tc->setNextNPC(pc + 8);
         tc->activate(0);
 
-        warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
+        warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
              tc->readPC());
     }
 }
@@ -217,7 +217,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
         if (ok == 1) {
             unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
             tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
-            warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->getThreadNum());
+            warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
         }
     } else if (src_reg > 0) {
         if (src_reg && !yield_mask != 0) {
@@ -238,7 +238,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
             fault = new ThreadFault();
         } else {
             //tc->ScheduleOtherThreads();
-            //std::cerr << "T" << tc->getThreadNum() << "YIELD: Schedule Other Threads.\n" << std::endl;
+            //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
             //tc->suspend();
             // Save last known PC in TCRestart
             // @TODO: Needs to check if this is a branch and if so, take previous instruction

src/arch/mips/utility.cc

@@ -259,7 +259,7 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(0/*tc->getThreadNum()*/);
+    tc->activate(0/*tc->threadId()*/);
 }
 
 } // namespace MipsISA

src/cpu/base.cc

@@ -329,6 +329,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
         CpuEvent::replaceThreadContext(oldTC, newTC);
 
         assert(newTC->contextId() == oldTC->contextId());
+        assert(newTC->threadId() == oldTC->threadId());
         system->replaceThreadContext(newTC, newTC->contextId());
 
         if (DTRACE(Context))

src/cpu/base.hh

@@ -82,7 +82,7 @@ class BaseCPU : public MemObject
     Tick instCnt;
     // every cpu has an id, put it in the base cpu
     // Set at initialization, only time a cpuId might change is during a
-    // takeover (which should be done from within the BaseCPU anyway, 
+    // takeover (which should be done from within the BaseCPU anyway,
     // therefore no setCpuId() method is provided
     int _cpuId;
 

src/cpu/checker/thread_context.hh

@@ -153,7 +153,7 @@ class CheckerThreadContext : public ThreadContext
     void profileSample() { return actualTC->profileSample(); }
 #endif
 
-    int getThreadNum() { return actualTC->getThreadNum(); }
+    int threadId() { return actualTC->threadId(); }
 
     // @todo: Do I need this?
     MachInst getInst() { return actualTC->getInst(); }

src/cpu/exetrace.cc

@@ -59,7 +59,7 @@ Trace::ExeTracerRecord::dump()
         outs << (misspeculating ? "-" : "+") << " ";
 
     if (IsOn(ExecThread))
-        outs << "T" << thread->getThreadNum() << " : ";
+        outs << "T" << thread->threadId() << " : ";
 
 
     std::string sym_str;

src/cpu/o3/thread_context.hh

@@ -82,6 +82,10 @@ class O3ThreadContext : public ThreadContext
 
     virtual void setContextId(int id) { thread->setContextId(id); }
 
+    /** Returns this thread's ID number. */
+    virtual int threadId() { return thread->threadId(); }
+    virtual void setThreadId(int id) { return thread->setThreadId(id); }
+
 #if FULL_SYSTEM
     /** Returns a pointer to the system. */
     virtual System *getSystemPtr() { return cpu->system; }
@@ -152,9 +156,6 @@ class O3ThreadContext : public ThreadContext
     /** Samples the function profiling information. */
     virtual void profileSample();
 #endif
-    /** Returns this thread's ID number. */
-    virtual int getThreadNum() { return thread->readTid(); }
-
     /** Returns the instruction this thread is currently committing.
      *  Only used when an instruction faults.
      */
@@ -190,36 +191,36 @@ class O3ThreadContext : public ThreadContext
 
     /** Reads this thread's PC. */
     virtual uint64_t readPC()
-    { return cpu->readPC(thread->readTid()); }
+    { return cpu->readPC(thread->threadId()); }
 
     /** Sets this thread's PC. */
     virtual void setPC(uint64_t val);
 
     /** Reads this thread's next PC. */
     virtual uint64_t readNextPC()
-    { return cpu->readNextPC(thread->readTid()); }
+    { return cpu->readNextPC(thread->threadId()); }
 
     /** Sets this thread's next PC. */
     virtual void setNextPC(uint64_t val);
 
     virtual uint64_t readMicroPC()
-    { return cpu->readMicroPC(thread->readTid()); }
+    { return cpu->readMicroPC(thread->threadId()); }
 
     virtual void setMicroPC(uint64_t val);
 
     virtual uint64_t readNextMicroPC()
-    { return cpu->readNextMicroPC(thread->readTid()); }
+    { return cpu->readNextMicroPC(thread->threadId()); }
 
     virtual void setNextMicroPC(uint64_t val);
 
     /** Reads a miscellaneous register. */
     virtual MiscReg readMiscRegNoEffect(int misc_reg)
-    { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
+    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
     virtual MiscReg readMiscReg(int misc_reg)
-    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
+    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 
     /** Sets a misc. register. */
     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
@@ -257,7 +258,7 @@ class O3ThreadContext : public ThreadContext
 
     /** Executes a syscall in SE mode. */
     virtual void syscall(int64_t callnum)
-    { return cpu->syscall(callnum, thread->readTid()); }
+    { return cpu->syscall(callnum, thread->threadId()); }
 
     /** Reads the funcExeInst counter. */
     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
@@ -271,7 +272,7 @@ class O3ThreadContext : public ThreadContext
 
     virtual uint64_t readNextNPC()
     {
-        return this->cpu->readNextNPC(this->thread->readTid());
+        return this->cpu->readNextNPC(this->thread->threadId());
     }
 
     virtual void setNextNPC(uint64_t val)
@@ -279,7 +280,7 @@ class O3ThreadContext : public ThreadContext
 #if THE_ISA == ALPHA_ISA
         panic("Not supported on Alpha!");
 #endif
-        this->cpu->setNextNPC(val, this->thread->readTid());
+        this->cpu->setNextNPC(val, this->thread->threadId());
     }
 
     /** This function exits the thread context in the CPU and returns

src/cpu/o3/thread_context_impl.hh

@@ -64,6 +64,7 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
     setStatus(old_context->status());
     copyArchRegs(old_context);
     setContextId(old_context->contextId());
+    setThreadId(old_context->threadId());
 
 #if !FULL_SYSTEM
     thread->funcExeInst = old_context->readFuncExeInst();
@@ -95,7 +96,7 @@ void
 O3ThreadContext<Impl>::activate(int delay)
 {
     DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
-            getThreadNum());
+            threadId());
 
     if (thread->status() == ThreadContext::Active)
         return;
@@ -105,14 +106,14 @@ O3ThreadContext<Impl>::activate(int delay)
 #endif
 
     if (thread->status() == ThreadContext::Unallocated) {
-        cpu->activateWhenReady(thread->readTid());
+        cpu->activateWhenReady(thread->threadId());
         return;
     }
 
     thread->setStatus(ThreadContext::Active);
 
     // status() == Suspended
-    cpu->activateContext(thread->readTid(), delay);
+    cpu->activateContext(thread->threadId(), delay);
 }
 
 template <class Impl>
@@ -120,7 +121,7 @@ void
 O3ThreadContext<Impl>::suspend(int delay)
 {
     DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
-            getThreadNum());
+            threadId());
 
     if (thread->status() == ThreadContext::Suspended)
         return;
@@ -139,7 +140,7 @@ O3ThreadContext<Impl>::suspend(int delay)
 #endif
 */
     thread->setStatus(ThreadContext::Suspended);
-    cpu->suspendContext(thread->readTid());
+    cpu->suspendContext(thread->threadId());
 }
 
 template <class Impl>
@@ -147,13 +148,13 @@ void
 O3ThreadContext<Impl>::deallocate(int delay)
 {
     DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n",
-            getThreadNum(), delay);
+            threadId(), delay);
 
     if (thread->status() == ThreadContext::Unallocated)
         return;
 
     thread->setStatus(ThreadContext::Unallocated);
-    cpu->deallocateContext(thread->readTid(), true, delay);
+    cpu->deallocateContext(thread->threadId(), true, delay);
 }
 
 template <class Impl>
@@ -161,13 +162,13 @@ void
 O3ThreadContext<Impl>::halt(int delay)
 {
     DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
-            getThreadNum());
+            threadId());
 
     if (thread->status() == ThreadContext::Halted)
         return;
 
     thread->setStatus(ThreadContext::Halted);
-    cpu->haltContext(thread->readTid());
+    cpu->haltContext(thread->threadId());
 }
 
 template <class Impl>
@@ -245,7 +246,7 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
 {
     // This function will mess things up unless the ROB is empty and
     // there are no instructions in the pipeline.
-    unsigned tid = thread->readTid();
+    unsigned tid = thread->threadId();
     PhysRegIndex renamed_reg;
 
     // First loop through the integer registers.
@@ -292,7 +293,7 @@ uint64_t
 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 {
     reg_idx = TheISA::flattenIntIndex(this, reg_idx);
-    return cpu->readArchIntReg(reg_idx, thread->readTid());
+    return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -302,9 +303,9 @@ O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     switch(width) {
       case 32:
-        return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
+        return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
       case 64:
-        return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
+        return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
       default:
         panic("Unsupported width!");
         return 0;
@@ -316,7 +317,7 @@ TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
-    return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
+    return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -325,7 +326,7 @@ O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
 {
     DPRINTF(Fault, "Reading floatint register through the TC!\n");
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
-    return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
+    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -333,7 +334,7 @@ TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 {
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
-    return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
+    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -341,11 +342,11 @@ void
 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
     reg_idx = TheISA::flattenIntIndex(this, reg_idx);
-    cpu->setArchIntReg(reg_idx, val, thread->readTid());
+    cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -356,16 +357,16 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     switch(width) {
       case 32:
-        cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
+        cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
         break;
       case 64:
-        cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
+        cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
         break;
     }
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -374,10 +375,10 @@ void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
-    cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
+    cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
 
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -388,11 +389,11 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
 {
     DPRINTF(Fault, "Setting floatint register through the TC!\n");
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
-    cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
+    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -401,11 +402,11 @@ void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
-    cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
+    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -413,11 +414,11 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setPC(uint64_t val)
 {
-    cpu->setPC(val, thread->readTid());
+    cpu->setPC(val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -425,11 +426,11 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setNextPC(uint64_t val)
 {
-    cpu->setNextPC(val, thread->readTid());
+    cpu->setNextPC(val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -437,11 +438,11 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setMicroPC(uint64_t val)
 {
-    cpu->setMicroPC(val, thread->readTid());
+    cpu->setMicroPC(val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -449,11 +450,11 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
 {
-    cpu->setNextMicroPC(val, thread->readTid());
+    cpu->setNextMicroPC(val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -461,11 +462,11 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
-    cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
+    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -474,11 +475,11 @@ void
 O3ThreadContext<Impl>::setMiscReg(int misc_reg,
                                                 const MiscReg &val)
 {
-    cpu->setMiscReg(misc_reg, val, thread->readTid());
+    cpu->setMiscReg(misc_reg, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
+        cpu->squashFromTC(thread->threadId());
     }
 }
 
@@ -488,21 +489,21 @@ template <class Impl>
 TheISA::IntReg
 O3ThreadContext<Impl>::getSyscallArg(int i)
 {
-    return cpu->getSyscallArg(i, thread->readTid());
+    return cpu->getSyscallArg(i, thread->threadId());
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
 {
-    cpu->setSyscallArg(i, val, thread->readTid());
+    cpu->setSyscallArg(i, val, thread->threadId());
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
 {
-    cpu->setSyscallReturn(return_value, thread->readTid());
+    cpu->setSyscallReturn(return_value, thread->threadId());
 }
 
 #endif // FULL_SYSTEM

src/cpu/ozone/cpu.hh

@@ -176,7 +176,7 @@ class OzoneCPU : public BaseCPU
         void profileSample();
 #endif
 
-        int getThreadNum();
+        int threadId();
 
         // Also somewhat obnoxious.  Really only used for the TLB fault.
         TheISA::MachInst getInst();
@@ -260,7 +260,7 @@ class OzoneCPU : public BaseCPU
         }
 
         void setSyscallReturn(SyscallReturn return_value)
-        { cpu->setSyscallReturn(return_value, thread->readTid()); }
+        { cpu->setSyscallReturn(return_value, thread->threadId()); }
 
         Counter readFuncExeInst() { return thread->funcExeInst; }
 

src/cpu/ozone/cpu_impl.hh

@@ -588,7 +588,7 @@ OzoneCPU<Impl>::postInterrupt(int int_num, int index)
 //      thread.activate();
         // Hack for now.  Otherwise might have to go through the tc, or
         // I need to figure out what's the right thing to call.
-        activateContext(thread.readTid(), 1);
+        activateContext(thread.threadId(), 1);
     }
 }
 #endif // FULL_SYSTEM
@@ -711,7 +711,7 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
 
     switch (palFunc) {
       case PAL::halt:
-        haltContext(thread.readTid());
+        haltContext(thread.threadId());
         if (--System::numSystemsRunning == 0)
             exitSimLoop("all cpus halted");
         break;
@@ -745,7 +745,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::activate(int delay)
 {
-    cpu->activateContext(thread->readTid(), delay);
+    cpu->activateContext(thread->threadId(), delay);
 }
 
 /// Set the status to Suspended.
@@ -753,7 +753,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::suspend()
 {
-    cpu->suspendContext(thread->readTid());
+    cpu->suspendContext(thread->threadId());
 }
 
 /// Set the status to Unallocated.
@@ -761,7 +761,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
 {
-    cpu->deallocateContext(thread->readTid(), delay);
+    cpu->deallocateContext(thread->threadId(), delay);
 }
 
 /// Set the status to Halted.
@@ -769,7 +769,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::halt()
 {
-    cpu->haltContext(thread->readTid());
+    cpu->haltContext(thread->threadId());
 }
 
 #if FULL_SYSTEM
@@ -884,9 +884,9 @@ OzoneCPU<Impl>::OzoneTC::profileSample()
 
 template <class Impl>
 int
-OzoneCPU<Impl>::OzoneTC::getThreadNum()
+OzoneCPU<Impl>::OzoneTC::threadId()
 {
-    return thread->readTid();
+    return thread->threadId();
 }
 
 template <class Impl>

src/cpu/simple_thread.cc

@@ -183,6 +183,7 @@ SimpleThread::copyState(ThreadContext *oldContext)
 #endif
     inst = oldContext->getInst();
 
+    _threadId = oldContext->threadId();
     _contextId = oldContext->contextId();
 }
 
@@ -221,14 +222,14 @@ SimpleThread::activate(int delay)
     lastActivate = curTick;
 
 //    if (status() == ThreadContext::Unallocated) {
-//      cpu->activateWhenReady(tid);
+//      cpu->activateWhenReady(_threadId);
 //      return;
 //   }
 
     _status = ThreadContext::Active;
 
     // status() == Suspended
-    cpu->activateContext(tid, delay);
+    cpu->activateContext(_threadId, delay);
 }
 
 void
@@ -249,7 +250,7 @@ SimpleThread::suspend()
 #endif
 */
     _status = ThreadContext::Suspended;
-    cpu->suspendContext(tid);
+    cpu->suspendContext(_threadId);
 }
 
 void
@@ -259,7 +260,7 @@ SimpleThread::deallocate()
         return;
 
     _status = ThreadContext::Unallocated;
-    cpu->deallocateContext(tid);
+    cpu->deallocateContext(_threadId);
 }
 
 void
@@ -269,7 +270,7 @@ SimpleThread::halt()
         return;
 
     _status = ThreadContext::Halted;
-    cpu->haltContext(tid);
+    cpu->haltContext(_threadId);
 }
 
 

src/cpu/simple_thread.hh

@@ -197,8 +197,6 @@ class SimpleThread : public ThreadState
 
     BaseCPU *getCpuPtr() { return cpu; }
 
-    int getThreadNum() { return tid; }
-
     TheISA::ITB *getITBPtr() { return itb; }
 
     TheISA::DTB *getDTBPtr() { return dtb; }

src/cpu/thread_context.hh

@@ -117,7 +117,9 @@ class ThreadContext
 
     virtual int cpuId() = 0;
 
-    virtual int getThreadNum() = 0;
+    virtual int threadId() = 0;
+
+    virtual void setThreadId(int id) = 0;
 
     virtual int contextId() = 0;
 
@@ -304,7 +306,9 @@ class ProxyThreadContext : public ThreadContext
 
     int cpuId() { return actualTC->cpuId(); }
 
-    int getThreadNum() { return actualTC->getThreadNum(); }
+    int threadId() { return actualTC->threadId(); }
+
+    void setThreadId(int id) { return actualTC->setThreadId(id); }
 
     int contextId() { return actualTC->contextId(); }
 

src/cpu/thread_state.cc

@@ -44,14 +44,14 @@
 
 #if FULL_SYSTEM
 ThreadState::ThreadState(BaseCPU *cpu, int _tid)
-    : baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
+    : baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
       kernelStats(NULL), physPort(NULL), virtPort(NULL),
       microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
 #else
 ThreadState::ThreadState(BaseCPU *cpu, int _tid, Process *_process,
                          short _asid)
-    : baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
+    : baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
       port(NULL), process(_process), asid(_asid),
       microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
 #endif
@@ -129,7 +129,7 @@ ThreadState::connectPhysPort()
         physPort->removeConn();
     else
         physPort = new FunctionalPort(csprintf("%s-%d-funcport",
-                                           baseCpu->name(), tid));
+                                           baseCpu->name(), _threadId));
     connectToMemFunc(physPort);
 }
 
@@ -143,7 +143,7 @@ ThreadState::connectVirtPort(ThreadContext *tc)
         virtPort->removeConn();
     else
         virtPort = new VirtualPort(csprintf("%s-%d-vport",
-                                        baseCpu->name(), tid), tc);
+                                        baseCpu->name(), _threadId), tc);
     connectToMemFunc(virtPort);
 }
 
@@ -169,7 +169,7 @@ ThreadState::getMemPort()
         return port;
 
     /* Use this port to for syscall emulation writes to memory. */
-    port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid),
+    port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), _threadId),
                                process, TranslatingPort::NextPage);
 
     connectToMemFunc(port);

src/cpu/thread_state.hh

@@ -84,9 +84,9 @@ struct ThreadState {
 
     void setContextId(int id) { _contextId = id; }
 
-    void setTid(int id) { tid = id; }
+    void setThreadId(int id) { _threadId = id; }
 
-    int readTid() { return tid; }
+    int threadId() { return _threadId; }
 
     Tick readLastActivate() { return lastActivate; }
 
@@ -177,7 +177,7 @@ struct ThreadState {
     int _contextId;
 
     // Index of hardware thread context on the CPU that this represents.
-    int tid;
+    int _threadId;
 
   public:
     /** Last time activate was called on this thread. */

src/mem/cache/base.hh

@@ -481,7 +481,7 @@ class BaseCache : public MemObject
 
     void incMissCount(PacketPtr pkt)
     {
-        misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+        misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
 
         if (missCount) {
             --missCount;

src/mem/cache/cache_impl.hh

@@ -296,7 +296,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
 
         if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) {
             // OK to satisfy access
-            hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+            hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
             satisfyCpuSideRequest(pkt, blk);
             return true;
         }
@@ -325,7 +325,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
         blk->status |= BlkDirty;
         // nothing else to do; writeback doesn't expect response
         assert(!pkt->needsResponse());
-        hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+        hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
         return true;
     }
 
@@ -467,8 +467,8 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
         if (mshr) {
             // MSHR hit
             //@todo remove hw_pf here
-            mshr_hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+            mshr_hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
-            if (mshr->threadNum != 0/*pkt->req->getThreadNum()*/) {
+            if (mshr->threadNum != 0/*pkt->req->threadId()*/) {
                 mshr->threadNum = -1;
             }
             mshr->allocateTarget(pkt, time, order++);
@@ -482,7 +482,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
             }
         } else {
             // no MSHR
-            mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+            mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
             // always mark as cache fill for now... if we implement
             // no-write-allocate or bypass accesses this will have to
             // be changed.
@@ -740,10 +740,10 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
     PacketList writebacks;
 
     if (pkt->req->isUncacheable()) {
-        mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->getThreadNum()*/] +=
+        mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
             miss_latency;
     } else {
-        mshr_miss_latency[stats_cmd_idx][0/*pkt->req->getThreadNum()*/] +=
+        mshr_miss_latency[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
             miss_latency;
     }
 
@@ -784,7 +784,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
                     (transfer_offset ? pkt->finishTime : pkt->firstWordTime);
 
                 assert(!target->pkt->req->isUncacheable());
-                missLatency[target->pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] +=
+                missLatency[target->pkt->cmdToIndex()][0/*pkt->req->threadId()*/] +=
                     completion_time - target->recvTime;
             } else {
                 // not a cache fill, just forwarding response
@@ -862,7 +862,7 @@ Cache<TagStore>::writebackBlk(BlkType *blk)
 {
     assert(blk && blk->isValid() && blk->isDirty());
 
-    writebacks[0/*pkt->req->getThreadNum()*/]++;
+    writebacks[0/*pkt->req->threadId()*/]++;
 
     Request *writebackReq =
         new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
@@ -1261,7 +1261,7 @@ Cache<TagStore>::getNextMSHR()
         if (pkt) {
             // Update statistic on number of prefetches issued
             // (hwpf_mshr_misses)
-            mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+            mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
             // Don't request bus, since we already have it
             return allocateMissBuffer(pkt, curTick, false);
         }

src/mem/cache/mshr_queue.cc

@@ -230,7 +230,7 @@ MSHRQueue::squash(int threadNum)
         if (mshr->threadNum == threadNum) {
             while (mshr->hasTargets()) {
                 mshr->popTarget();
-                assert(0/*target->req->getThreadNum()*/ == threadNum);
+                assert(0/*target->req->threadId()*/ == threadNum);
             }
             assert(!mshr->hasTargets());
             assert(mshr->ntargets==0);