ARM: Implement the various versions of VMOV.
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Gabe Black
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1f059541d6
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dd1aedc98b
1 changed files with 170 additions and 0 deletions
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@ -56,4 +56,174 @@ let {{
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header_output += RegRegOpDeclare.subst(vmrsIop);
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header_output += RegRegOpDeclare.subst(vmrsIop);
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decoder_output += RegRegOpConstructor.subst(vmrsIop);
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decoder_output += RegRegOpConstructor.subst(vmrsIop);
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exec_output += PredOpExecute.subst(vmrsIop);
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exec_output += PredOpExecute.subst(vmrsIop);
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vmovImmSCode = '''
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FpDest.uw = bits(imm, 31, 0);
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'''
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vmovImmSIop = InstObjParams("vmov", "VmovImmS", "RegImmOp",
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{ "code": vmovImmSCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmOpDeclare.subst(vmovImmSIop);
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decoder_output += RegImmOpConstructor.subst(vmovImmSIop);
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exec_output += PredOpExecute.subst(vmovImmSIop);
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vmovImmDCode = '''
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FpDestP0.uw = bits(imm, 31, 0);
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FpDestP1.uw = bits(imm, 63, 32);
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'''
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vmovImmDIop = InstObjParams("vmov", "VmovImmD", "RegImmOp",
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{ "code": vmovImmDCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmOpDeclare.subst(vmovImmDIop);
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decoder_output += RegImmOpConstructor.subst(vmovImmDIop);
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exec_output += PredOpExecute.subst(vmovImmDIop);
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vmovImmQCode = '''
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FpDestP0.uw = bits(imm, 31, 0);
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FpDestP1.uw = bits(imm, 63, 32);
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FpDestP2.uw = bits(imm, 31, 0);
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FpDestP3.uw = bits(imm, 63, 32);
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'''
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vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "RegImmOp",
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{ "code": vmovImmQCode,
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"predicate_test": predicateTest }, [])
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header_output += RegImmOpDeclare.subst(vmovImmQIop);
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decoder_output += RegImmOpConstructor.subst(vmovImmQIop);
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exec_output += PredOpExecute.subst(vmovImmQIop);
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vmovRegSCode = '''
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FpDest.uw = FpOp1.uw;
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'''
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vmovRegSIop = InstObjParams("vmov", "VmovRegS", "RegRegOp",
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{ "code": vmovRegSCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vmovRegSIop);
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decoder_output += RegRegOpConstructor.subst(vmovRegSIop);
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exec_output += PredOpExecute.subst(vmovRegSIop);
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vmovRegDCode = '''
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FpDestP0.uw = FpOp1P0.uw;
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FpDestP1.uw = FpOp1P1.uw;
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'''
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vmovRegDIop = InstObjParams("vmov", "VmovRegD", "RegRegOp",
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{ "code": vmovRegDCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vmovRegDIop);
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decoder_output += RegRegOpConstructor.subst(vmovRegDIop);
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exec_output += PredOpExecute.subst(vmovRegDIop);
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vmovRegQCode = '''
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FpDestP0.uw = FpOp1P0.uw;
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FpDestP1.uw = FpOp1P1.uw;
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FpDestP2.uw = FpOp1P2.uw;
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FpDestP3.uw = FpOp1P3.uw;
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'''
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vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "RegRegOp",
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{ "code": vmovRegQCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vmovRegQIop);
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decoder_output += RegRegOpConstructor.subst(vmovRegQIop);
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exec_output += PredOpExecute.subst(vmovRegQIop);
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vmovCoreRegBCode = '''
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FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub);
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'''
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vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "RegRegImmOp",
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{ "code": vmovCoreRegBCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegImmOpDeclare.subst(vmovCoreRegBIop);
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decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegBIop);
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exec_output += PredOpExecute.subst(vmovCoreRegBIop);
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vmovCoreRegHCode = '''
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FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh);
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'''
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vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "RegRegImmOp",
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{ "code": vmovCoreRegHCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegImmOpDeclare.subst(vmovCoreRegHIop);
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decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegHIop);
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exec_output += PredOpExecute.subst(vmovCoreRegHIop);
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vmovCoreRegWCode = '''
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FpDest.uw = Op1.uw;
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'''
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vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "RegRegOp",
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{ "code": vmovCoreRegWCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vmovCoreRegWIop);
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decoder_output += RegRegOpConstructor.subst(vmovCoreRegWIop);
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exec_output += PredOpExecute.subst(vmovCoreRegWIop);
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vmovRegCoreUBCode = '''
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Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7);
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'''
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vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "RegRegImmOp",
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{ "code": vmovRegCoreUBCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegImmOpDeclare.subst(vmovRegCoreUBIop);
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decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUBIop);
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exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
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vmovRegCoreUHCode = '''
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Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15);
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'''
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vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "RegRegImmOp",
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{ "code": vmovRegCoreUHCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegImmOpDeclare.subst(vmovRegCoreUHIop);
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decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUHIop);
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exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
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vmovRegCoreSBCode = '''
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Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7));
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'''
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vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "RegRegImmOp",
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{ "code": vmovRegCoreSBCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegImmOpDeclare.subst(vmovRegCoreSBIop);
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decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSBIop);
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exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
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vmovRegCoreSHCode = '''
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Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15));
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'''
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vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "RegRegImmOp",
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{ "code": vmovRegCoreSHCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegImmOpDeclare.subst(vmovRegCoreSHIop);
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decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSHIop);
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exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
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vmovRegCoreWCode = '''
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Dest = FpOp1.uw;
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'''
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vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "RegRegOp",
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{ "code": vmovRegCoreWCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vmovRegCoreWIop);
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decoder_output += RegRegOpConstructor.subst(vmovRegCoreWIop);
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exec_output += PredOpExecute.subst(vmovRegCoreWIop);
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vmov2Reg2CoreCode = '''
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FpDestP0.uw = Op1.uw;
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FpDestP1.uw = Op2.uw;
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'''
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vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "RegRegRegOp",
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{ "code": vmov2Reg2CoreCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
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decoder_output += RegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
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exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
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vmov2Core2RegCode = '''
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Dest.uw = FpOp2P0.uw;
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Op1.uw = FpOp2P1.uw;
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'''
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vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp",
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{ "code": vmov2Core2RegCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop);
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decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop);
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exec_output += PredOpExecute.subst(vmov2Core2RegIop);
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}};
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}};
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