Hand merge
base/traceflags.py: Include new flags --HG-- extra : convert_revision : 8017cbe256860dce8b1efc1b4e1e81e883895b90
This commit is contained in:
commit
dcedd7866e
|
@ -194,6 +194,11 @@ base_sources = Split('''
|
|||
mem/cache/miss/miss_queue.cc
|
||||
mem/cache/miss/mshr.cc
|
||||
mem/cache/miss/mshr_queue.cc
|
||||
mem/cache/prefetch/base_prefetcher.cc
|
||||
mem/cache/prefetch/ghb_prefetcher.cc
|
||||
mem/cache/prefetch/prefetcher.cc
|
||||
mem/cache/prefetch/stride_prefetcher.cc
|
||||
mem/cache/prefetch/tagged_prefetcher.cc
|
||||
mem/cache/tags/base_tags.cc
|
||||
mem/cache/tags/cache_tags.cc
|
||||
mem/cache/tags/fa_lru.cc
|
||||
|
|
|
@ -716,7 +716,7 @@ class Tru64 {
|
|||
TypedBufferArg<Tru64::tbl_sysinfo> elp(xc->getSyscallArg(2));
|
||||
|
||||
const int clk_hz = one_million;
|
||||
elp->si_user = curTick / (ticksPerSecond / clk_hz);
|
||||
elp->si_user = curTick / (Clock::Frequency / clk_hz);
|
||||
elp->si_nice = 0;
|
||||
elp->si_sys = 0;
|
||||
elp->si_idle = 0;
|
||||
|
|
|
@ -95,7 +95,7 @@ namespace AlphaPseudo
|
|||
m5exit(ExecContext *xc)
|
||||
{
|
||||
Tick delay = xc->regs.intRegFile[16];
|
||||
Tick when = curTick + NS2Ticks(delay);
|
||||
Tick when = curTick + delay * Clock::Int::ns;
|
||||
SimExit(when, "m5_exit instruction encountered");
|
||||
}
|
||||
|
||||
|
@ -108,8 +108,8 @@ namespace AlphaPseudo
|
|||
Tick delay = xc->regs.intRegFile[16];
|
||||
Tick period = xc->regs.intRegFile[17];
|
||||
|
||||
Tick when = curTick + NS2Ticks(delay);
|
||||
Tick repeat = NS2Ticks(period);
|
||||
Tick when = curTick + delay * Clock::Int::ns;
|
||||
Tick repeat = period * Clock::Int::ns;
|
||||
|
||||
using namespace Stats;
|
||||
SetupEvent(Reset, when, repeat);
|
||||
|
@ -124,8 +124,8 @@ namespace AlphaPseudo
|
|||
Tick delay = xc->regs.intRegFile[16];
|
||||
Tick period = xc->regs.intRegFile[17];
|
||||
|
||||
Tick when = curTick + NS2Ticks(delay);
|
||||
Tick repeat = NS2Ticks(period);
|
||||
Tick when = curTick + delay * Clock::Int::ns;
|
||||
Tick repeat = period * Clock::Int::ns;
|
||||
|
||||
using namespace Stats;
|
||||
SetupEvent(Dump, when, repeat);
|
||||
|
@ -140,8 +140,8 @@ namespace AlphaPseudo
|
|||
Tick delay = xc->regs.intRegFile[16];
|
||||
Tick period = xc->regs.intRegFile[17];
|
||||
|
||||
Tick when = curTick + NS2Ticks(delay);
|
||||
Tick repeat = NS2Ticks(period);
|
||||
Tick when = curTick + delay * Clock::Int::ns;
|
||||
Tick repeat = period * Clock::Int::ns;
|
||||
|
||||
using namespace Stats;
|
||||
SetupEvent(Dump|Reset, when, repeat);
|
||||
|
@ -156,8 +156,8 @@ namespace AlphaPseudo
|
|||
Tick delay = xc->regs.intRegFile[16];
|
||||
Tick period = xc->regs.intRegFile[17];
|
||||
|
||||
Tick when = curTick + NS2Ticks(delay);
|
||||
Tick repeat = NS2Ticks(period);
|
||||
Tick when = curTick + delay * Clock::Int::ns;
|
||||
Tick repeat = period * Clock::Int::ns;
|
||||
|
||||
Checkpoint::setup(when, repeat);
|
||||
}
|
||||
|
|
|
@ -139,7 +139,8 @@ baseFlags = [
|
|||
'DynInst',
|
||||
'FullCPU',
|
||||
'CommitRate',
|
||||
'OoOCPU'
|
||||
'OoOCPU',
|
||||
'HWPrefetch'
|
||||
]
|
||||
|
||||
#
|
||||
|
|
|
@ -74,9 +74,6 @@ void
|
|||
EtherDump::init()
|
||||
{
|
||||
curtime = time(NULL);
|
||||
s_freq = ticksPerSecond;
|
||||
us_freq = ticksPerSecond / ULL(1000000);
|
||||
|
||||
struct pcap_file_header hdr;
|
||||
hdr.magic = TCPDUMP_MAGIC;
|
||||
hdr.version_major = PCAP_VERSION_MAJOR;
|
||||
|
@ -108,8 +105,8 @@ void
|
|||
EtherDump::dumpPacket(PacketPtr &packet)
|
||||
{
|
||||
pcap_pkthdr pkthdr;
|
||||
pkthdr.seconds = curtime + (curTick / s_freq);
|
||||
pkthdr.microseconds = (curTick / us_freq) % ULL(1000000);
|
||||
pkthdr.seconds = curtime + (curTick / Clock::Int::s);
|
||||
pkthdr.microseconds = (curTick / Clock::Int::us) % ULL(1000000);
|
||||
pkthdr.caplen = std::min(packet->length, maxlen);
|
||||
pkthdr.len = packet->length;
|
||||
stream.write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
|
||||
|
|
|
@ -49,8 +49,6 @@ class EtherDump : public SimObject
|
|||
void init();
|
||||
|
||||
Tick curtime;
|
||||
Tick s_freq;
|
||||
Tick us_freq;
|
||||
|
||||
public:
|
||||
EtherDump(const std::string &name, const std::string &file, int max);
|
||||
|
|
|
@ -52,7 +52,7 @@ EtherLink::EtherLink(const string &name, EtherInt *peer0, EtherInt *peer1,
|
|||
: SimObject(name)
|
||||
{
|
||||
double rate = ((double)ticksPerSecond * 8.0) / (double)speed;
|
||||
Tick delay = US2Ticks(dly);
|
||||
Tick delay = dly * Clock::Int::us;
|
||||
|
||||
link[0] = new Link(name + ".link0", this, 0, rate, delay, dump);
|
||||
link[1] = new Link(name + ".link1", this, 1, rate, delay, dump);
|
||||
|
|
|
@ -289,15 +289,16 @@ IdeController::ReadConfig(int offset, int size, uint8_t *data)
|
|||
memcpy((void *)data, (void *)&pci_regs[offset], size);
|
||||
}
|
||||
|
||||
DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
|
||||
origOffset, offset, size, *(uint32_t *)data);
|
||||
DPRINTF(IdeCtrl, "PCI read offset: %#x (%#x) size: %#x data: %#x\n",
|
||||
origOffset, offset, size,
|
||||
(*(uint32_t *)data) & (0xffffffff >> 8 * (4 - size)));
|
||||
}
|
||||
|
||||
void
|
||||
IdeController::WriteConfig(int offset, int size, uint32_t data)
|
||||
{
|
||||
DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
|
||||
offset, size, data);
|
||||
DPRINTF(IdeCtrl, "PCI write offset: %#x size: %#x data: %#x\n",
|
||||
offset, size, data & (0xffffffff >> 8 * (4 - size)));
|
||||
|
||||
// do standard write stuff if in standard PCI space
|
||||
if (offset < PCI_DEVICE_SPECIFIC) {
|
||||
|
@ -438,8 +439,9 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
|
|||
memcpy((void *)data, &bmi_regs[offset], req->size);
|
||||
}
|
||||
|
||||
DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
|
||||
offset, req->size, *(uint32_t *)data);
|
||||
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
|
||||
offset, req->size,
|
||||
(*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
|
@ -458,8 +460,9 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
|
|||
byte = (req->size == sizeof(uint8_t)) ? true : false;
|
||||
cmdBlk = (type == COMMAND_BLOCK) ? true : false;
|
||||
|
||||
DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
|
||||
offset, req->size, *(uint32_t *)data);
|
||||
DPRINTF(IdeCtrl, "write from offset: %#x size: %#x data: %#x\n",
|
||||
offset, req->size,
|
||||
(*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));
|
||||
|
||||
uint8_t oldVal, newVal;
|
||||
|
||||
|
|
|
@ -336,7 +336,8 @@ IdeDisk::dmaPrdReadDone()
|
|||
physmem->dma_addr(curPrdAddr, sizeof(PrdEntry_t)),
|
||||
sizeof(PrdEntry_t));
|
||||
|
||||
DPRINTF(IdeDisk, "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
|
||||
DPRINTF(IdeDisk,
|
||||
"PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
|
||||
curPrd.getBaseAddr(), pciToDma(curPrd.getBaseAddr()),
|
||||
curPrd.getByteCount(), (cmdBytesLeft/SectorSize),
|
||||
curPrd.getEOT(), curSector);
|
||||
|
@ -609,10 +610,10 @@ void
|
|||
IdeDisk::abortDma()
|
||||
{
|
||||
if (dmaState == Dma_Idle)
|
||||
panic("Inconsistent DMA state, should be in Dma_Start or Dma_Transfer!\n");
|
||||
panic("Inconsistent DMA state, should be Start or Transfer!");
|
||||
|
||||
if (devState != Transfer_Data_Dma && devState != Prepare_Data_Dma)
|
||||
panic("Inconsistent device state, should be in Transfer or Prepare!\n");
|
||||
panic("Inconsistent device state, should be Transfer or Prepare!\n");
|
||||
|
||||
updateState(ACT_CMD_ERROR);
|
||||
}
|
||||
|
@ -732,7 +733,7 @@ IdeDisk::startCommand()
|
|||
void
|
||||
IdeDisk::intrPost()
|
||||
{
|
||||
DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n");
|
||||
DPRINTF(IdeDisk, "Posting Interrupt\n");
|
||||
if (intrPending)
|
||||
panic("Attempt to post an interrupt with one pending\n");
|
||||
|
||||
|
@ -746,7 +747,7 @@ IdeDisk::intrPost()
|
|||
void
|
||||
IdeDisk::intrClear()
|
||||
{
|
||||
DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n");
|
||||
DPRINTF(IdeDisk, "Clearing Interrupt\n");
|
||||
if (!intrPending)
|
||||
panic("Attempt to clear a non-pending interrupt\n");
|
||||
|
||||
|
|
|
@ -138,7 +138,7 @@ NSGigE::NSGigE(Params *p)
|
|||
}
|
||||
|
||||
|
||||
intrDelay = US2Ticks(p->intr_delay);
|
||||
intrDelay = p->intr_delay * Clock::Int::us;
|
||||
dmaReadDelay = p->dma_read_delay;
|
||||
dmaWriteDelay = p->dma_write_delay;
|
||||
dmaReadFactor = p->dma_read_factor;
|
||||
|
|
|
@ -79,7 +79,7 @@ const char *TxStateStrings[] =
|
|||
//
|
||||
Base::Base(Params *p)
|
||||
: PciDev(p), rxEnable(false), txEnable(false),
|
||||
intrDelay(US2Ticks(p->intr_delay)),
|
||||
intrDelay(p->intr_delay * Clock::Int::us),
|
||||
intrTick(0), cpuIntrEnable(false), cpuPendingIntr(false), intrEvent(0),
|
||||
interface(NULL)
|
||||
{
|
||||
|
|
|
@ -95,6 +95,13 @@ TsunamiIO::RTCEvent::unserialize(Checkpoint *cp, const std::string §ion)
|
|||
TsunamiIO::ClockEvent::ClockEvent()
|
||||
: Event(&mainEventQueue)
|
||||
{
|
||||
/* This is the PIT Tick Rate. A constant for the 8254 timer. The
|
||||
* Tsunami platform has one of these cycle counters on the Cypress
|
||||
* South Bridge and it is used by linux for estimating the cycle
|
||||
* frequency of the machine it is running on. --Ali
|
||||
*/
|
||||
interval = (Tick)(Clock::Float::s / 1193180.0);
|
||||
|
||||
DPRINTF(Tsunami, "Clock Event Initilizing\n");
|
||||
mode = 0;
|
||||
}
|
||||
|
@ -113,9 +120,7 @@ void
|
|||
TsunamiIO::ClockEvent::Program(int count)
|
||||
{
|
||||
DPRINTF(Tsunami, "Timer set to curTick + %d\n", count);
|
||||
// should be count * (cpufreq/pitfreq)
|
||||
interval = count * ticksPerSecond/1193180UL;
|
||||
schedule(curTick + interval);
|
||||
schedule(curTick + count * interval);
|
||||
status = 0;
|
||||
}
|
||||
|
||||
|
|
21
dev/uart.cc
21
dev/uart.cc
|
@ -73,17 +73,28 @@ Uart::IntrEvent::process()
|
|||
|
||||
}
|
||||
|
||||
/* The linux serial driver (8250.c about line 1182) loops reading from
|
||||
* the device until the device reports it has no more data to
|
||||
* read. After a maximum of 255 iterations the code prints "serial8250
|
||||
* too much work for irq X," and breaks out of the loop. Since the
|
||||
* simulated system is so much slower than the actual system, if a
|
||||
* user is typing on the keyboard it is very easy for them to provide
|
||||
* input at a fast enough rate to not allow the loop to exit and thus
|
||||
* the error to be printed. This magic number provides a delay between
|
||||
* the time the UART receives a character to send to the simulated
|
||||
* system and the time it actually notifies the system it has a
|
||||
* character to send to alleviate this problem. --Ali
|
||||
*/
|
||||
void
|
||||
Uart::IntrEvent::scheduleIntr()
|
||||
{
|
||||
static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
|
||||
DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
|
||||
curTick + (ticksPerSecond/2000) * 350);
|
||||
curTick + interval);
|
||||
if (!scheduled())
|
||||
/* @todo Make this cleaner, will be much easier with
|
||||
* nanosecond time everywhere. Hint hint Nate. */
|
||||
schedule(curTick + (ticksPerSecond/2000000000) * 450);
|
||||
schedule(curTick + interval);
|
||||
else
|
||||
reschedule(curTick + (ticksPerSecond/2000000000) * 450);
|
||||
reschedule(curTick + interval);
|
||||
}
|
||||
|
||||
Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
|
||||
|
|
|
@ -1142,6 +1142,8 @@ class UInt64(CheckedInt): cppname = 'uint64_t'; size = 64; unsigned = True
|
|||
|
||||
class Counter(CheckedInt): cppname = 'Counter'; size = 64; unsigned = True
|
||||
class Tick(CheckedInt): cppname = 'Tick'; size = 64; unsigned = True
|
||||
class TcpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True
|
||||
class UdpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True
|
||||
|
||||
class Percent(CheckedInt): cppname = 'int'; min = 0; max = 100
|
||||
|
||||
|
@ -1283,7 +1285,7 @@ class NullSimObject(object):
|
|||
pass
|
||||
|
||||
def _convert(cls, value):
|
||||
if value == Nxone:
|
||||
if value == None:
|
||||
return
|
||||
|
||||
if isinstance(value, cls):
|
||||
|
|
|
@ -153,15 +153,15 @@ def toNetworkBandwidth(value):
|
|||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
if value.endswith('Tbps'):
|
||||
return float(value[:-3]) * tera
|
||||
return float(value[:-4]) * tera
|
||||
elif value.endswith('Gbps'):
|
||||
return float(value[:-3]) * giga
|
||||
return float(value[:-4]) * giga
|
||||
elif value.endswith('Mbps'):
|
||||
return float(value[:-3]) * mega
|
||||
return float(value[:-4]) * mega
|
||||
elif value.endswith('kbps'):
|
||||
return float(value[:-3]) * kilo
|
||||
return float(value[:-4]) * kilo
|
||||
elif value.endswith('bps'):
|
||||
return float(value[:-2])
|
||||
return float(value[:-3])
|
||||
else:
|
||||
return float(value)
|
||||
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
from BaseMem import BaseMem
|
||||
|
||||
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
|
||||
|
||||
simobj BaseCache(BaseMem):
|
||||
type = 'BaseCache'
|
||||
adaptive_compression = Param.Bool(False,
|
||||
|
@ -36,3 +38,23 @@ simobj BaseCache(BaseMem):
|
|||
two_queue = Param.Bool(False,
|
||||
"whether the lifo should have two queue replacement")
|
||||
write_buffers = Param.Int(8, "number of write buffers")
|
||||
prefetch_miss = Param.Bool(False,
|
||||
"wheter you are using the hardware prefetcher from Miss stream")
|
||||
prefetch_access = Param.Bool(False,
|
||||
"wheter you are using the hardware prefetcher from Access stream")
|
||||
prefetcher_size = Param.Int(100,
|
||||
"Number of entries in the harware prefetch queue")
|
||||
prefetch_past_page = Param.Bool(False,
|
||||
"Allow prefetches to cross virtual page boundaries")
|
||||
prefetch_serial_squash = Param.Bool(False,
|
||||
"Squash prefetches with a later time on a subsequent miss")
|
||||
prefetch_degree = Param.Int(1,
|
||||
"Degree of the prefetch depth")
|
||||
prefetch_latency = Param.Tick(10,
|
||||
"Latency of the prefetcher")
|
||||
prefetch_policy = Param.Prefetch('none',
|
||||
"Type of prefetcher to use")
|
||||
prefetch_cache_check_push = Param.Bool(True,
|
||||
"Check if in cash on push or pop of prefetch queue")
|
||||
prefetch_use_cpu_id = Param.Bool(True,
|
||||
"Use the CPU ID to seperate calculations of prefetches")
|
||||
|
|
|
@ -7,7 +7,6 @@ simobj Root(SimObject):
|
|||
type = 'Root'
|
||||
frequency = Param.RootFrequency('200MHz', "tick frequency")
|
||||
output_file = Param.String('cout', "file to dump simulator output to")
|
||||
full_system = Param.Bool("Full system simulation?")
|
||||
hier = HierParams(do_data = False, do_events = True)
|
||||
checkpoint = Param.String('', "Checkpoint file")
|
||||
stats = Statistics()
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
simobj ConsoleListener(SimObject):
|
||||
type = 'ConsoleListener'
|
||||
port = Param.UInt16(3456, "listen port")
|
||||
port = Param.TcpPort(3456, "listen port")
|
||||
|
||||
simobj SimConsole(SimObject):
|
||||
type = 'SimConsole'
|
||||
|
|
|
@ -105,7 +105,7 @@ InitSimStats()
|
|||
;
|
||||
|
||||
simFreq
|
||||
.scalar(ticksPerSecond)
|
||||
.scalar(Clock::Frequency)
|
||||
.name("sim_freq")
|
||||
.desc("Frequency of simulated ticks")
|
||||
;
|
||||
|
|
|
@ -222,9 +222,7 @@ template <class T1, class T2>
|
|||
void
|
||||
getElapsedTime(T1 &sec, T2 &usec)
|
||||
{
|
||||
int cycles_per_usec = ticksPerSecond / one_million;
|
||||
|
||||
int elapsed_usecs = curTick / cycles_per_usec;
|
||||
int elapsed_usecs = curTick / Clock::Int::us;
|
||||
sec = elapsed_usecs / one_million;
|
||||
usec = elapsed_usecs % one_million;
|
||||
}
|
||||
|
|
|
@ -42,16 +42,40 @@
|
|||
using namespace std;
|
||||
|
||||
Tick curTick = 0;
|
||||
Tick ticksPerSecond;
|
||||
double __ticksPerMS;
|
||||
double __ticksPerUS;
|
||||
double __ticksPerNS;
|
||||
double __ticksPerPS;
|
||||
|
||||
bool fullSystem;
|
||||
ostream *outputStream;
|
||||
ostream *configStream;
|
||||
|
||||
/// The simulated frequency of curTick. (This is only here for a short time)
|
||||
Tick ticksPerSecond;
|
||||
|
||||
namespace Clock {
|
||||
/// The simulated frequency of curTick. (In ticks per second)
|
||||
Tick Frequency;
|
||||
|
||||
namespace Float {
|
||||
double s;
|
||||
double ms;
|
||||
double us;
|
||||
double ns;
|
||||
double ps;
|
||||
|
||||
double Hz;
|
||||
double kHz;
|
||||
double MHz;
|
||||
double GHZ;
|
||||
/* namespace Float */ }
|
||||
|
||||
namespace Int {
|
||||
Tick s;
|
||||
Tick ms;
|
||||
Tick us;
|
||||
Tick ns;
|
||||
Tick ps;
|
||||
/* namespace Float */ }
|
||||
|
||||
/* namespace Clock */ }
|
||||
|
||||
|
||||
// Dummy Object
|
||||
class Root : public SimObject
|
||||
{
|
||||
|
@ -61,7 +85,6 @@ class Root : public SimObject
|
|||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
|
||||
|
||||
Param<bool> full_system;
|
||||
Param<Tick> frequency;
|
||||
Param<string> output_file;
|
||||
|
||||
|
@ -69,7 +92,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(Root)
|
|||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Root)
|
||||
|
||||
INIT_PARAM(full_system, "full system simulation"),
|
||||
INIT_PARAM(frequency, "tick frequency"),
|
||||
INIT_PARAM(output_file, "file to dump simulator output to")
|
||||
|
||||
|
@ -82,27 +104,32 @@ CREATE_SIM_OBJECT(Root)
|
|||
panic("only one root object allowed!");
|
||||
|
||||
created = true;
|
||||
fullSystem = full_system;
|
||||
|
||||
#ifdef FULL_SYSTEM
|
||||
if (!fullSystem)
|
||||
panic("FULL_SYSTEM compiled and configuration not full_system");
|
||||
#else
|
||||
if (fullSystem)
|
||||
panic("FULL_SYSTEM not compiled but configuration is full_system");
|
||||
#endif
|
||||
|
||||
ticksPerSecond = frequency;
|
||||
double freq = double(ticksPerSecond);
|
||||
__ticksPerMS = freq / 1.0e3;
|
||||
__ticksPerUS = freq / 1.0e6;
|
||||
__ticksPerNS = freq / 1.0e9;
|
||||
__ticksPerPS = freq / 1.0e12;
|
||||
|
||||
outputStream = simout.find(output_file);
|
||||
Root *root = new Root(getInstanceName());
|
||||
|
||||
return new Root(getInstanceName());
|
||||
ticksPerSecond = frequency;
|
||||
|
||||
using namespace Clock;
|
||||
Frequency = frequency;
|
||||
Float::s = static_cast<double>(Frequency);
|
||||
Float::ms = Float::s / 1.0e3;
|
||||
Float::us = Float::s / 1.0e6;
|
||||
Float::ns = Float::s / 1.0e9;
|
||||
Float::ps = Float::s / 1.0e12;
|
||||
|
||||
Float::Hz = 1.0 / Float::s;
|
||||
Float::kHz = 1.0 / Float::ms;
|
||||
Float::MHz = 1.0 / Float::us;
|
||||
Float::GHZ = 1.0 / Float::ns;
|
||||
|
||||
Int::s = Frequency;
|
||||
Int::ms = Int::s / 1000;
|
||||
Int::us = Int::ms / 1000;
|
||||
Int::ns = Int::us / 1000;
|
||||
Int::ps = Int::ns / 1000;
|
||||
|
||||
return root;
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("Root", Root)
|
||||
|
||||
|
|
|
@ -55,14 +55,10 @@ def unique(list):
|
|||
map(set.__setitem__, list, [])
|
||||
return set.keys()
|
||||
|
||||
def graphdata68(runs, options, tag, label, value):
|
||||
import info
|
||||
configs = ['ste', 'hte', 'htd', 'ocm', 'occ', 'ocp' ]
|
||||
benchmarks = [ 'm', 's', 'snt', 'nb1', 'w1', 'w2', 'w3', 'w4', 'nm', 'ns', 'nw1', 'nw2', 'nw3' ]
|
||||
dmas = [ 'x' ]
|
||||
caches = [ '2', '4' ]
|
||||
#benchmarks = [ 'm', 's', 'snt', 'nb1', 'w1', 'w2', 'w3', 'w4', 'nm', 'ns', 'nw1', 'nw2', 'nw3' ]
|
||||
|
||||
names = []
|
||||
def graphdata(runs, options, tag, label, value):
|
||||
import info
|
||||
|
||||
bench_system = {
|
||||
'm' : 'client',
|
||||
|
@ -86,27 +82,42 @@ def graphdata68(runs, options, tag, label, value):
|
|||
'nw3' : 'natbox'
|
||||
}
|
||||
|
||||
system_configs = {
|
||||
's1' : 'Uni 4GHz',
|
||||
'm1' : 'Uni 6GHz',
|
||||
'f1' : 'Uni 8GHz',
|
||||
'q1' : 'Uni 10GHz',
|
||||
's2' : 'Dual 4GHz',
|
||||
'm2' : 'Dual 6GHz',
|
||||
's4' : 'Quad 4GHz',
|
||||
'm4' : 'Quad 6GHz' }
|
||||
|
||||
configs = ['ste', 'hte', 'htd', 'ocm', 'occ', 'ocp' ]
|
||||
benchmarks = [ 'm', 'snt', 'w2', 'nm', 'nw2' ]
|
||||
caches = [ '0', '2', '4' ]
|
||||
|
||||
names = []
|
||||
for bench in benchmarks:
|
||||
if bench_system[bench] != options.system:
|
||||
continue
|
||||
|
||||
for dma in dmas:
|
||||
for cache in caches:
|
||||
names.append([bench, dma, cache])
|
||||
names.append([bench, cache])
|
||||
|
||||
for bench,dma,cache in names:
|
||||
base = '%s.%s.%s' % (bench, dma, cache)
|
||||
fname = 'data/%s.%s.68.dat' % (tag, base)
|
||||
for bench,cache in names:
|
||||
base = '%s.%s' % (bench, cache)
|
||||
fname = 'data/uni.%s.%s.dat' % (tag, base)
|
||||
f = open(fname, 'w')
|
||||
print >>f, '#set TITLE = '
|
||||
print >>f, '#set ylbl = %s' % label
|
||||
#print >>f, '#set sublabels = %s' % ' '.join(configs)
|
||||
print >>f, '#set sublabels = ste hte htd ocm occ ocs'
|
||||
|
||||
for speed,freq in zip(['s', 'm', 'f', 'q'],['4GHz', '6GHz','8GHz', '10GHz']):
|
||||
print >>f, '"%s"' % freq,
|
||||
for speed in ('s1', 'm1', 'f1', 'q1'):
|
||||
label = system_configs[speed]
|
||||
print >>f, '"%s"' % label,
|
||||
for conf in configs:
|
||||
name = '%s.%s.%s.%s.%s' % (conf, bench, dma, cache, speed)
|
||||
name = '%s.%s.%s.%s' % (conf, bench, cache, speed)
|
||||
run = info.source.allRunNames[name]
|
||||
info.display_run = run.run;
|
||||
val = float(value)
|
||||
|
@ -117,65 +128,32 @@ def graphdata68(runs, options, tag, label, value):
|
|||
print >>f
|
||||
f.close()
|
||||
|
||||
def graphdata(runs, options, tag, label, value):
|
||||
if options.graph68:
|
||||
graphdata68(runs, options, tag, label, value)
|
||||
return
|
||||
|
||||
import info
|
||||
configs = ['ste', 'hte', 'htd', 'ocm', 'occ', 'ocp' ]
|
||||
#benchmarks = [ 'm', 's', 'nb1', 'nb2', 'nt1', 'nt2', 'w1', 'w2', 'w3', 'w4', 'ns', 'nm', 'nw1', 'nw2', 'nw3' ]
|
||||
#benchmarks = [ 'm', 's', 'nb1', 'nb2', 'nt1', 'w1', 'w2', 'w3', 'ns', 'nm', 'w1s' ]
|
||||
benchmarks = [ 'm', 's', 'nb1', 'nb2', 'w1', 'w2', 'w3', 'w4', 'ns', 'nm', 'nw1', 'snt' ]
|
||||
#dmas = [ 'x', 'd', 'b' ]
|
||||
dmas = [ 'x' ]
|
||||
caches = [ '2', '4' ]
|
||||
benchmarks = [ 'w2']
|
||||
caches = [ '0', '2', '4' ]
|
||||
|
||||
names = []
|
||||
|
||||
bench_system = {
|
||||
'm' : 'client',
|
||||
's' : 'client',
|
||||
'snt' : 'client',
|
||||
'nb1' : 'server',
|
||||
'nb2' : 'server',
|
||||
'nt1' : 'server',
|
||||
'nt2' : 'server',
|
||||
'w1' : 'server',
|
||||
'w2' : 'server',
|
||||
'w3' : 'server',
|
||||
'w4' : 'server',
|
||||
'w1s' : 'server',
|
||||
'w2s' : 'server',
|
||||
'w3s' : 'server',
|
||||
'ns' : 'natbox',
|
||||
'nm' : 'natbox',
|
||||
'nw1' : 'natbox',
|
||||
'nw2' : 'natbox',
|
||||
'nw3' : 'natbox'
|
||||
}
|
||||
|
||||
for bench in benchmarks:
|
||||
if bench_system[bench] != options.system:
|
||||
continue
|
||||
|
||||
for dma in dmas:
|
||||
for cache in caches:
|
||||
names.append([bench, dma, cache])
|
||||
names.append([bench, cache])
|
||||
|
||||
for bench,dma,cache in names:
|
||||
base = '%s.%s.%s' % (bench, dma, cache)
|
||||
fname = 'data/%s.%s.dat' % (tag, base)
|
||||
for bench,cache in names:
|
||||
base = '%s.%s' % (bench, cache)
|
||||
fname = 'data/mp.%s.%s.dat' % (tag, base)
|
||||
f = open(fname, 'w')
|
||||
print >>f, '#set TITLE = '
|
||||
print >>f, '#set ylbl = %s' % label
|
||||
#print >>f, '#set sublabels = %s' % ' '.join(configs)
|
||||
print >>f, '#set sublabels = ste hte htd ocm occ ocs'
|
||||
|
||||
for speed,freq in zip(['s', 'q'],['4GHz','10GHz']):
|
||||
print >>f, '"%s"' % freq,
|
||||
for speed in ('s2', 'm2', 's4', 'm4'):
|
||||
label = system_configs[speed]
|
||||
print >>f, '"%s"' % label,
|
||||
for conf in configs:
|
||||
name = '%s.%s.%s.%s.%s' % (conf, bench, dma, cache, speed)
|
||||
name = '%s.%s.%s.%s' % (conf, bench, cache, speed)
|
||||
run = info.source.allRunNames[name]
|
||||
info.display_run = run.run;
|
||||
val = float(value)
|
||||
|
@ -744,13 +722,10 @@ if __name__ == '__main__':
|
|||
options.get = None
|
||||
options.binned = False
|
||||
options.graph = False
|
||||
options.graph68 = False
|
||||
options.ticks = False
|
||||
|
||||
opts, args = getopts(sys.argv[1:], '-6BEFGd:g:h:pr:s:u:T:')
|
||||
for o,a in opts:
|
||||
if o == '-6':
|
||||
options.graph68 = True
|
||||
if o == '-B':
|
||||
options.binned = True
|
||||
if o == '-E':
|
||||
|
|
Loading…
Reference in a new issue