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split off fullsystem and se iprs into two functions to remove lots of #ifs

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setup all initialization stuff for UA2005
Setup fullsys build options
Start to make fullsystem compile

src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    RCS to BitKeeper
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Add support for doing virtual to physical translation using the in-memory
    page table
src/arch/sparc/vtophys.cc:
    a tad bit of error checking
src/arch/sparc/vtophys.hh:
    Cleanup of full-system global variables, primarily in simple_cpu.cc,
    to allow multi-system simulations.  (Multiple systems not yet yested
    though.)  Also changes to build sim_smt in full-system mode (though
    with only SimpleCPU and not the full timing CPU for now).

    Still to do: minimize changes in SimpleCPU code between full-system
    and application modes... way too many ifdefs there.  Much of the
    full-system stuff moved into SimpleCPU should be put in a new System
    object to allow multiprocessor simulations.

    Converted last remaining modules from C to C++ (mostly in /old).
    Renamed all .c files to .cc and a few .h files to .hh.

    Renamed architecture-specific files in arch/$TARGET from
    $TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
    intermediate files in object directory.  Split exo-specific
    definitions out of machine.hh into machine_exo.h.

    Specifics:

    In machine.def, null resource descriptors must be FUClamd_NA (and not
    NA) to pass C++ type checking.

    Enhanced error checking/reporting in bas
src/arch/sparc/vtophys.cc:
    - Get rid of my String class, the Vector class, the bitvector class, and my
    doubly linked list class.
    - Convert tokenize, to_number (formerly StringToNumber) and eat_white to
    function on stl strings.
    - Change most cases of char * and const char * to string, or const string &
    - Some formatting and style nits, but not too many.
src/arch/sparc/vtophys.cc:
    simplify
src/arch/sparc/vtophys.cc:

    Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
    write, overloaded on the type of the 'data' argument.  Merged the
    full-system and non-full-system implementations of these eight
    original functions into two common template functions.

    To support this, also renamed (read|write)[1248] on memory_object and
    derivatives to just read & write, again overloaded on the type of the
    'data' argument.  Many of these functions could now be condensed into
    a few template functions (though with a level of indirection so that
    the interface can remain virtual).  I did not do that though.
src/arch/sparc/vtophys.cc:
    First pass at compiling with gcc 3.x.  Lots of "std::" in header files,
    "using namespace std" in source files.  (Note policy of not putting "using"
    statements in headers or before includes in sources.)

    Still not able to compile with gcc 3.2.
    Errors:
    - Can't create an ifstream from a file descriptor anymore (breaks IniFile).
    - "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
    not clear why since it's in the public part of the class declaration.
    - cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
    SimObjectParam<PipeTrace*>& : int' operator")
    - pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
    Warnings:
    - strstream now deprecated... needs some rewriting in sat_counter.hh
    and hybrid_pred.hh (need to get all that code out of the headers anyway)
    - trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
    give a valid preprocessing token'
    - major "implicit typename" issues in base/sized.hh
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Implement some interval statistics for full system mode.
    Create a callpal function that is called when a callpal occurs so it's easier
    to manipulate the statics.
    Rework the vtophys stuff to make it a bit cleaner.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Get rid of almost all old-style object names.  This commit is equivalent
    to running the following script on the current head:

    #! /bin/sh

    find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
    s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
    s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
    s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
    s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
    s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
    s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
    s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
    s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
    s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
    s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
    s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
    s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
    s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
    s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
    s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
    s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
    s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
src/arch/sparc/vtophys.cc:
    since cprintf properly deals with 64-bit types, stop using FMT* as much as
    possible
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Change byte_t etc. to C99 standard int8_t etc.
    Other than old/host.h, all other changes were produced by this script:

    #! /bin/sh

    find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
    s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
    s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
    s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
    s/\bshalf_t\b(?!\.hh)/int16_t/g;\
    s/\bword_t\b(?!\.hh)/uint32_t/g;\
    s/\bsword_t\b(?!\.hh)/int32_t/g;\
    s/\bqword_t\b(?!\.hh)/uint64_t/g;\
    s/\bsqword_t\b(?!\.hh)/int64_t/g;\
    s/\bbool_t\b(?!\.hh)/bool/g;\
    s/\bdfloat_t\b(?!\.hh)/double/g;\
    s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Add CVS Id tags
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Massive renaming to (almost) eliminate all md_* and MD_* names
    in preparation for total exorcism of machine.def.

    Most of the changes in this commit were performed with the
    following perl script (perl -pi <script> <files>).  A small
    amount of manual fixup was needed to (mostly getting rid of
    the Addr typedefs in the various memory objects now that
    the former md_addr_t has that name).

    # rename machine-dependent types and constants (will be moving into ISA traits object)
    s/md_addr_t/Addr/g;
    s/md_intreg_t/IntReg/g;
    s/md_gpr_t/IntRegFile/g;
    s/md_fpreg_t/FloatReg/g;
    s/md_fpr_t/FloatRegFile/g;
    s/md_ctrlreg_t/MiscReg/g;
    s/md_ctrl_t/MiscRegFile/g;
    s/md_ipr_t/InternalProcReg/g;
    s/md_anyreg_t/AnyReg/g;
    s/md_inst_t/MachInst/g;
    s/regs_t/RegFile/g;
    # manually fix declaration in old/regs.h and a few forward decls
    s/struct RegFile/RegFile/g;
    s/MD_NUM_IREGS/NumIntRegs/g;
    s/MD_NUM_FREGS/NumFloatRegs/g;
    s/MD_NUM_CREGS/NumMiscRegs/g;
    s/MD_IPR_NUM/NumInternalProcRegs/g;
    s/MD_TOTAL_REGS/TotalNumRegs/g;
    s/MD_REG_ZERO/ZeroReg/g;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    New ISA description system.  No more machine.def!
    Instructions are now decoded into StaticInst objects, and all static
    instruction properties (including execution behavior) are associated
    with those objects.  Extended documentation in progress.
    Currently supports Alpha only; PISA will not compile.
    Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
src/arch/sparc/vtophys.cc:
    get rid of MD_IPR_foo and call it IPR_foo
    add some comments to describe what the various PALtemp registers do
    formatting
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    license
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    a little style
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Add attribution to license.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Make include paths explicit.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    CopyData and CopyString moved from kernel.cc to vtophys.cc
    kernel.cc and kernel.hh moved to kern/tru64
src/arch/sparc/vtophys.hh:
    Include isa_traits.hh for Addr
src/arch/sparc/vtophys.cc:
    formatting fixes
src/arch/sparc/vtophys.cc:
    fix up vtophys to deal with translations if there
    is no ptbr, and to deal with PAL addresses
    add ptomem which is just a wrapper for dma_addr
src/arch/sparc/vtophys.hh:
    add ptomem which is a wrapper for dma_addr with the
    same usage as vtomem
src/arch/sparc/vtophys.cc:
    Fix to remote debugger while in PAL code
src/arch/sparc/vtophys.cc:
    Remote an old hack that is now unnecessary
src/arch/sparc/vtophys.cc:
    Removed buggy code that tries to fix PAL addresses (may cause problems
    while trying to debug in PAL code, but that should do this fix outside
    of vtophys)
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Updated Copyright
src/arch/sparc/vtophys.cc:
    added back some code andrew removed and couldn't remember why.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    rename CopyData to CopyOut and implement CopyIn to copy data
    from the simulator into the simulatee
src/arch/sparc/vtophys.cc:
    fixed a bad merge from linux<->tru64
src/arch/sparc/vtophys.cc:
    Check max address pal can be at so we don't do the wrong conversion
    if gdb asks for an unaligned access.
src/arch/sparc/vtophys.cc:
    PGOFSET -> ALPHA_PGOFSET to avoid include file problems
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    in the arch/alpha directory we should use arch/alpha, not
    targetarch.  sort includes while we're here.
src/arch/sparc/vtophys.cc:
    use new constants, functions and structs to clean up the
    vtophys code.
src/arch/sparc/vtophys.hh:
    Clean up a little bit and make the protypes match new changes.
src/arch/sparc/vtophys.cc:
    deal with isa addition
src/arch/sparc/vtophys.cc:
    shuffle files around for new directory structure
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Remove RCS Id string
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    Update copyright dates and author list
src/arch/sparc/vtophys.cc:
    Added a using directive for AlphaISA
src/arch/sparc/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
src/arch/sparc/vtophys.hh:
    Made Addr a global type
src/arch/sparc/vtophys.cc:
    Change access to the IPR to go through the XC.
src/arch/sparc/vtophys.cc:
    Avoid directly accessing objects within the XC.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    fixed for new memory system
    put in namespace AlphaISA
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
    Remove authors from copyright.
src/arch/sparc/vtophys.cc:
    bk cp alpha/vtophys.cc sparc/vtophys.cc
src/arch/sparc/vtophys.hh:
    bk cp alpha/vtophys.hh sparc/vtophys.hh
src/arch/sparc/SConscript:
    remove fullsystem files that don't exist
src/arch/sparc/isa_traits.hh:
    split off fullsystem and se iprs into two functions to remove lots of #ifs
src/arch/sparc/regfile.hh:
    split off fullsystem and se iprs into two functions to remove lots of #ifs
    setup all initialization stuff for UA2005
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    Add system level tick storage to make stick be syncronized across multiple processors
src/arch/sparc/vtophys.hh:
    start to create a vtophys for Sparc
src/base/loader/symtab.hh:
    Addr is defined in sim/host.hh

--HG--
extra : convert_revision : ae4658e6bc2e2b51d7fb1c711d069ffe99e1377d
This commit is contained in:
Ali Saidi 2006-05-29 16:53:47 -04:00
parent 82a76d18e1
commit dc29a7c8ae
11 changed files with 504 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
build_opts/SPARC_FS Normal file
View file

@ -0,0 +1,2 @@
TARGET_ISA = 'sparc'
FULL_SYSTEM = 1

7
src/arch/sparc/SConscript
View file

@ -47,12 +47,7 @@ base_sources = Split('''
# Full-system sources
full_system_sources = Split('''
tlb.cc
arguments.cc
ev5.cc
osfpal.cc
stacktrace.cc
vtophys.cc
ua2005.cc
''')
# Syscall emulation (non-full-system) sources

3
src/arch/sparc/isa_traits.hh
View file

@ -80,6 +80,9 @@ class SyscallReturn
#endif
#if FULL_SYSTEM
#include "arch/sparc/isa_fullsys_traits.hh"
#endif
namespace SparcISA
{

57
src/arch/sparc/regfile.hh
View file

@ -29,6 +29,7 @@
#ifndef __ARCH_SPARC_REGFILE_HH__
#define __ARCH_SPARC_REGFILE_HH__
#include "arch/sparc/exceptions.hh"
#include "arch/sparc/faults.hh"
#include "base/trace.hh"
#include "sim/byteswap.hh"
@ -406,7 +407,7 @@ namespace SparcISA
union {
uint64_t stick; // Hardware clock-tick counter
struct {
int64_t counter:63; // Clock-tick count
int64_t :63; // Not used, storage in SparcSystem
uint64_t npt:1; // Non-priveleged trap
} stickFields;
};
@ -572,6 +573,12 @@ namespace SparcISA
&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
HSTickCompareEvent hSTickCompare;
/** Fullsystem only register version of ReadRegWithEffect() */
MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
/** Fullsystem only register version of SetRegWithEffect() */
Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
ExecContext * xc);
public:
void reset()
@ -584,26 +591,30 @@ namespace SparcISA
//Bits that aren't set aren't defined on startup.
tl = MaxTL;
gl = MaxGL;
tt[tl] = PowerOnReset.trapType();
pstateFields.mm = 0; //Total Store Order
pstateFields.red = 1; //Enter RED_State
pstateFields.am = 0; //Address Masking is turned off
pstateFields.priv = 1; //Processor enters privileged mode
pstateFields.ie = 0; //Interrupts are disabled
pstateFields.ag = 1; //Globals are replaced with alternate globals
pstateFields.tle = 0; //Big Endian mode for traps
pstateFields.cle = 0; //Big Endian mode for non-traps
tickFields.counter = 0; //The TICK register is unreadable bya
tickFields.npt = 1; //The TICK register is unreadable by by !priv
tick_cmpr.int_dis = 1; // disable timer compare interrupts
stickFields.counter = 0; //The TICK register is unreadable by
softint = 0; // Clear all the soft interrupt bits
tick_cmprFields.int_dis = 1; // disable timer compare interrupts
tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
stickFields.npt = 1; //The TICK register is unreadable by by !priv
hpstateFields.id = 1;
hpstateFields.ibe = 0;
stick_cmprFields.int_dis = 1; // disable timer compare interrupts
stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
tt[tl] = power_on_reset;
pstate = 0; // fields 0 but pef
pstateFields.pef = 1;
hpstate = 0;
hpstateFields.red = 1;
hpstateFields.hpriv = 1;
hpstateFields.tlz = 0; // this is a guess
hintp = 0; // no interrupts pending
hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
#else
/* //This sets up the initial state of the processor for usermode processes
@ -630,12 +641,30 @@ namespace SparcISA
reset();
}
/** read a value out of an either an SE or FS IPR. No checking is done
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
* register are copied that are necessary for FS. However this prevents
* a bunch of ifdefs and is rarely called so is not performance
* criticial. */
MiscReg readReg(int miscReg);
/** Read a value from an IPR. Only the SE iprs are here and the rest
* are are readFSRegWithEffect (which is called by readRegWithEffect()).
* Checking is done for permission based on state bits in the miscreg
* file. */
MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
/** write a value into an either an SE or FS IPR. No checking is done
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
* register are copied that are necessary for FS. However this prevents
* a bunch of ifdefs and is rarely called so is not performance
* criticial.*/
Fault setReg(int miscReg, const MiscReg &val);
/** Write a value into an IPR. Only the SE iprs are here and the rest
* are are setFSRegWithEffect (which is called by setRegWithEffect()).
* Checking is done for permission based on state bits in the miscreg
* file. */
Fault setRegWithEffect(int miscReg,
const MiscReg &val, ExecContext * xc);

3
src/arch/sparc/system.cc
View file

@ -40,7 +40,8 @@
using namespace BigEndianGuest;
SparcSystem::SparcSystem(Params *p)
: System(p)
: System(p), sysTick(0)
{
resetSymtab = new SymbolTable;
hypervisorSymtab = new SymbolTable;

5
src/arch/sparc/system.hh
View file

@ -53,7 +53,7 @@ class SparcSystem : public System
SparcSystem(Params *p);
~SparcaSystem();
~SparcSystem();
virtual bool breakpoint();
@ -82,6 +82,9 @@ class SparcSystem : public System
/** Object pointer for the openboot code */
ObjectFile *openboot;
/** System Tick for syncronized tick across all cpus. */
Tick sysTick;
protected:
const Params *params() const { return (const Params *)_params; }

35
src/arch/sparc/tlb.hh Normal file
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@ -0,0 +1,35 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
*/
#ifndef __ARCH_SPARC_TLB_HH__
#define __ARCH_SPARC_TLB_HH__
#endif // __ARCH_SPARC_TLB_HH__

199
src/arch/sparc/ua2005.cc Normal file
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@ -0,0 +1,199 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/sparc/regfile.hh"
Fault
SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
ExecContext *xc)
{
int64_t time;
SparcSystem *sys;
switch (miscReg) {
/** Full system only ASRs */
case MISCREG_SOFTINT:
if (isNonPriv())
return new PrivilegedOpcode;
// Check if we are going to interrupt because of something
int oldLevel = InterruptLevel(softint);
int newLevel = InterruptLevel(val);
setReg(miscReg, val);
if (newLevel > oldLevel)
; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
//xc->getCpuPtr()->checkInterrupts = true;
return NoFault;
case MISCREG_SOFTINT_CLR:
return setRegWithEffect(miscReg, ~val & softint, xc);
case MISCREG_SOFTINT_SET:
return setRegWithEffect(miscReg, val | softint, xc);
case MISCREG_TICK_CMPR:
if (isNonPriv())
return new PrivilegedOpcode;
setReg(miscReg, val);
if (tick_cmprFields.int_dis && tickCompare.scheduled())
tickCompare.deschedule();
time = tick_cmprFields.tick_cmpr - tickFields.counter;
if (!tick_cmprFields.int_dis && time > 0)
tickCompare.schedule(time * xc->getCpuPtr()->cycles(1));
return NoFault;
case MISCREG_STICK:
if (isNonPriv())
return new PrivilegedOpcode;
if (isPriv())
return new PrivilegedAction;
sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
assert(sys != NULL);
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
stickFields.npt = val & Bit64 ? 1 : 0;
return NoFault;
case MISCREG_STICK_CMPR:
if (isNonPriv())
return new PrivilegedOpcode;
sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
assert(sys != NULL);
setReg(miscReg, val);
if (stick_cmprFields.int_dis && sTickCompare.scheduled())
sTickCompare.deschedule();
time = stick_cmprFields.tick_cmpr - sys->sysTick;
if (!stick_cmprFields.int_dis && time > 0)
sTickCompare.schedule(time * Clock::Int::ns);
return NoFault;
/** Fullsystem only Priv registers. */
case MISCREG_PIL:
if (FULL_SYSTEM) {
setReg(miscReg, val);
//xc->getCpuPtr()->checkInterrupts;
// MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
return NoFault;
} else
panic("PIL not implemented for syscall emulation\n");
/** Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
setReg(miscReg, val);
return NoFault;
case MISCREG_HTSTATE:
if (tl == 0)
return new IllegalInstruction;
setReg(miscReg, val);
return NoFault;
case MISCREG_HTBA:
// clear lower 7 bits on writes.
setReg(miscReg, val & ULL(~0x7FFF));
return NoFault;
case MISCREG_STRAND_STS_REG:
setReg(miscReg, strandStatusReg);
return NoFault;
case MISCREG_HSTICK_CMPR:
if (isNonPriv())
return new PrivilegedOpcode;
sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
assert(sys != NULL);
setReg(miscReg, val);
if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
hSTickCompare.deschedule();
int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
if (!hstick_cmprFields.int_dis && time > 0)
hSTickCompare.schedule(time * Clock::Int::ns);
return NoFault;
default:
return new IllegalInstruction;
}
}
MiscReg
MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
{
switch (miscReg) {
/** Privileged registers. */
case MISCREG_SOFTINT:
if (isNonPriv()) {
fault = new PrivilegedOpcode;
return 0;
}
return readReg(miscReg);
case MISCREG_TICK_CMPR:
if (isNonPriv()) {
fault = new PrivilegedOpcode;
return 0;
}
return readReg(miscReg);
case MISCREG_STICK:
SparcSystem *sys;
if (stickFields.npt && !isNonPriv()) {
fault = new PrivilegedAction;
return 0;
}
sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
assert(sys != NULL);
return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
case MISCREG_STICK_CMPR:
if (isNonPriv()) {
fault = new PrivilegedOpcode;
return 0;
}
return readReg(miscReg);
/** Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
return readReg(miscReg);
case MISCREG_HTSTATE:
if (tl == 0) {
fault = new IllegalInstruction;
return 0;
}
return readReg(miscReg);
case MISCREG_HTBA:
return readReg(miscReg) & ULL(~0x7FFF);
case MISCREG_HVER:
return NWindows | MaxTL << 8 | MaxGL << 16;
case MISCREG_STRAND_STS_REG:
return strandStatusReg;
case MISCREG_HSTICK_CMPR:
return hstick_cmpr;
default:
fault = new IllegalInstruction;
return 0;
}
}
}; // namespace SparcISA

162
src/arch/sparc/vtophys.cc Normal file
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@ -0,0 +1,162 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <string>
#include "arch/alpha/ev5.hh"
#include "arch/alpha/vtophys.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "mem/vport.hh"
using namespace std;
using namespace AlphaISA;
AlphaISA::PageTableEntry
AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
{
Addr level1_pte = ptbr + vaddr.level1();
AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
if (!level1.valid()) {
DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
return 0;
}
Addr level2_pte = level1.paddr() + vaddr.level2();
AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
if (!level2.valid()) {
DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
return 0;
}
Addr level3_pte = level2.paddr() + vaddr.level3();
AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
if (!level3.valid()) {
DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
return 0;
}
return level3;
}
Addr
AlphaISA::vtophys(Addr vaddr)
{
Addr paddr = 0;
if (AlphaISA::IsUSeg(vaddr))
DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
else if (AlphaISA::IsK0Seg(vaddr))
paddr = AlphaISA::K0Seg2Phys(vaddr);
else
panic("vtophys: ptbr is not set on virtual lookup");
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
}
Addr
AlphaISA::vtophys(ExecContext *xc, Addr addr)
{
AlphaISA::VAddr vaddr = addr;
Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
paddr = vaddr & ~ULL(1);
} else {
if (AlphaISA::IsK0Seg(vaddr)) {
paddr = AlphaISA::K0Seg2Phys(vaddr);
} else if (!ptbr) {
paddr = vaddr;
} else {
AlphaISA::PageTableEntry pte =
kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr);
if (pte.valid())
paddr = pte.paddr() | vaddr.offset();
}
}
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
}
void
AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
{
uint8_t *dst = (uint8_t *)dest;
VirtualPort *vp = xc->getVirtPort(xc);
vp->readBlob(src, dst, cplen);
xc->delVirtPort(vp);
}
void
AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
{
uint8_t *src = (uint8_t *)source;
VirtualPort *vp = xc->getVirtPort(xc);
vp->writeBlob(dest, src, cplen);
xc->delVirtPort(vp);
}
void
AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
{
int len = 0;
VirtualPort *vp = xc->getVirtPort(xc);
do {
vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
len++;
} while (len < maxlen && dst[len] != 0 );
xc->delVirtPort(vp);
dst[len] = 0;
}
void
AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr)
{
VirtualPort *vp = xc->getVirtPort(xc);
for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
gen.next())
{
vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
src += gen.size();
}
xc->delVirtPort(vp);
}

52
src/arch/sparc/vtophys.hh Normal file
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@ -0,0 +1,52 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_SPARC_VTOPHYS_H__
#define __ARCH_SPARC_VTOPHYS_H__
#include "arch/sparc/isa_traits.hh"
class ExecContext;
class FunctionalPort;
namespace SparcISA {
PageTableEntry
kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
Addr vtophys(Addr vaddr);
Addr vtophys(ExecContext *xc, Addr vaddr);
void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
void CopyStringIn(ExecContext *xc, char *src, Addr vaddr);
};
#endif // __ARCH_SPARC_VTOPHYS_H__

2
src/base/loader/symtab.hh
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@ -32,7 +32,7 @@
#include <iosfwd>
#include <map>
#include "arch/isa_traits.hh" // for Addr
#include "sim/host.hh" // for Addr
class Checkpoint;
class SymbolTable