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Add a hack to truncate addresses to 32 bits in SE. Paging should be changed to use the architecture's TLB, at which point this can be removed.

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--HG--
extra : convert_revision : 54f3c18e5aead727d0ac244ed00fd97d3ca8ad75
This commit is contained in:
Gabe Black 2007-05-08 13:02:19 +00:00
parent 6fec6d278a
commit dc1c9e0300
5 changed files with 27 additions and 9 deletions
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6
src/arch/sparc/isa/formats/mem/basicmem.isa
View file

@ -57,10 +57,12 @@ let {{
addrCalcImm = 'EA = Rs1 + imm;'
iop = InstObjParams(name, Name, 'Mem',
{"code": code, "postacc_code" : postacc_code,
"fault_check": faultCode, "ea_code": addrCalcReg}, opt_flags)
"fault_check": faultCode, "ea_code": addrCalcReg,
"EA_trunc": TruncateEA}, opt_flags)
iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
{"code": code, "postacc_code" : postacc_code,
"fault_check": faultCode, "ea_code": addrCalcImm}, opt_flags)
"fault_check": faultCode, "ea_code": addrCalcImm,
"EA_trunc": TruncateEA}, opt_flags)
header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop)

6
src/arch/sparc/isa/formats/mem/blockmem.isa
View file

@ -298,11 +298,13 @@ let {{
iop = InstObjParams(name, Name, 'BlockMem',
{"code": pcedCode, "ea_code": addrCalcReg,
"fault_check": faultCode, "micro_pc": microPc,
"set_flags": flag_code}, opt_flags)
"set_flags": flag_code, "EA_trunc" : TruncateEA},
opt_flags)
iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm',
{"code": pcedCode, "ea_code": addrCalcImm,
"fault_check": faultCode, "micro_pc": microPc,
"set_flags": flag_code}, opt_flags)
"set_flags": flag_code, "EA_trunc" : TruncateEA},
opt_flags)
decoder_output += BlockMemMicroConstructor.subst(iop)
decoder_output += BlockMemMicroConstructor.subst(iop_imm)
exec_output += doDualSplitExecute(

8
src/arch/sparc/isa/formats/mem/swap.isa
View file

@ -51,6 +51,7 @@ def template SwapExecute {{
}
if(storeCond && fault == NoFault)
{
%(EA_trunc)s
fault = xc->write((uint%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, &mem_data);
}
@ -91,6 +92,7 @@ def template SwapInitiateAcc {{
}
if(fault == NoFault)
{
%(EA_trunc)s
fault = xc->write((uint%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, &mem_data);
}
@ -157,12 +159,14 @@ let {{
addrCalcReg = 'EA = Rs1;'
iop = InstObjParams(name, Name, 'Mem',
{"code": code, "postacc_code" : postacc_code,
"fault_check": faultCode, "ea_code": addrCalcReg}, opt_flags)
"fault_check": faultCode, "ea_code": addrCalcReg,
"EA_trunc" : TruncateEA}, opt_flags)
header_output = MemDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
microParams = {"code": code, "postacc_code" : postacc_code,
"ea_code" : addrCalcReg, "fault_check" : faultCode}
"ea_code" : addrCalcReg, "fault_check" : faultCode,
"EA_trunc" : TruncateEA}
exec_output = doSplitExecute(execute, name, Name, asi,
["IsStoreConditional"], microParams);
return (header_output, decoder_output, exec_output, decode_block)

12
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -149,6 +149,7 @@ def template LoadExecute {{
%(fault_check)s;
if(fault == NoFault)
{
%(EA_trunc)s
fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
}
if(fault == NoFault)
@ -179,6 +180,7 @@ def template LoadInitiateAcc {{
%(fault_check)s;
if(fault == NoFault)
{
%(EA_trunc)s
fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
}
return fault;
@ -224,6 +226,7 @@ def template StoreExecute {{
}
if(storeCond && fault == NoFault)
{
%(EA_trunc)s
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
@ -257,6 +260,7 @@ def template StoreInitiateAcc {{
}
if(storeCond && fault == NoFault)
{
%(EA_trunc)s
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
@ -317,6 +321,11 @@ let {{
fault = new PrivilegedAction;
'''
TruncateEA = '''
#if !FULL_SYSTEM
EA = Pstate<3:> ? EA<31:0> : EA;
#endif
'''
}};
//A simple function to generate the name of the macro op of a certain
@ -346,7 +355,8 @@ let {{
(eaRegCode, nameReg, NameReg),
(eaImmCode, nameImm, NameImm)):
microParams = {"code": code, "postacc_code" : postacc_code,
"ea_code": eaCode, "fault_check": faultCode}
"ea_code": eaCode, "fault_check": faultCode,
"EA_trunc" : TruncateEA}
executeCode += doSplitExecute(execute, name, Name,
asi, opt_flags, microParams)
return executeCode

4
src/arch/sparc/process.cc
View file

@ -87,8 +87,8 @@ Sparc32LiveProcess::startup()
//From the SPARC ABI
//The process runs in user mode
threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
//The process runs in user mode with 32 bit addresses
threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x0a);
//Setup default FP state
threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);