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This commit is contained in:
Steve Reinhardt 2013-08-24 12:03:10 -04:00
parent ecfe7dc3ef
commit dc18352e3c
6 changed files with 1238 additions and 1104 deletions
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70
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
View file

@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
clock=1000
cache_line_size=64
clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@ -29,12 +30,17 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clock=500
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@ -62,10 +68,10 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -76,22 +82,31 @@ prefetcher=Null
response_latency=2
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=262144
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -102,12 +117,21 @@ prefetcher=Null
response_latency=2
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
@ -120,10 +144,10 @@ size=48
[system.cpu.l2cache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@ -134,16 +158,24 @@ prefetcher=Null
response_latency=20
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=20
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@ -164,10 +196,14 @@ max_stack_size=67108864
output=cout
system=system
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
block_size=64
clock=1000
clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
@ -178,8 +214,8 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
@ -187,3 +223,7 @@ null=false
range=0:134217727
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
voltage=1.000000

4
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 8 2013 10:00:13
gem5 started Jun 8 2013 10:00:28
gem5 compiled Aug 24 2013 11:53:30
gem5 started Aug 24 2013 12:01:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second

84
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu
sim_ticks 727072000 # Number of ticks simulated
final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1476552 # Simulator instruction rate (inst/s)
host_op_rate 1476467 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2146892777 # Simulator tick rate (ticks/s)
host_mem_usage 226332 # Number of bytes of host memory used
host_seconds 0.34 # Real time elapsed on the host
host_inst_rate 1590478 # Simulator instruction rate (inst/s)
host_op_rate 1590395 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2312543024 # Simulator tick rate (ticks/s)
host_mem_usage 227540 # Number of bytes of host memory used
host_seconds 0.31 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 718 # Tr
system.membus.trans_dist::ReadResp 718 # Transaction distribution
system.membus.trans_dist::ReadExReq 139 # Transaction distribution
system.membus.trans_dist::ReadExResp 139 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 54848 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 1454144 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 718 # Tr
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 806 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 908 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1714 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 25792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 29056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 54848 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)

160
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
View file

@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
clock=1000
cache_line_size=64
clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@ -27,14 +28,19 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
voltage_domain=system.voltage_domain
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@ -62,10 +68,10 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -76,22 +82,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
[system.cpu0.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu0.dtb]
type=AlphaTLB
size=64
[system.cpu0.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -102,12 +117,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
[system.cpu0.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu0.interrupts]
type=AlphaInterrupts
@ -136,7 +160,7 @@ type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
clk_domain=system.cpu_clk_domain
cpu_id=1
do_checkpoint_insts=true
do_quiesce=true
@ -164,10 +188,10 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -178,22 +202,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
[system.cpu1.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu1.dtb]
type=AlphaTLB
size=64
[system.cpu1.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -204,12 +237,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
[system.cpu1.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu1.interrupts]
type=AlphaInterrupts
@ -238,7 +280,7 @@ type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
clk_domain=system.cpu_clk_domain
cpu_id=2
do_checkpoint_insts=true
do_quiesce=true
@ -266,10 +308,10 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -280,22 +322,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu2.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
mem_side=system.toL2Bus.slave[5]
[system.cpu2.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu2.dtb]
type=AlphaTLB
size=64
[system.cpu2.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -306,12 +357,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu2.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.slave[4]
[system.cpu2.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu2.interrupts]
type=AlphaInterrupts
@ -340,7 +400,7 @@ type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
clk_domain=system.cpu_clk_domain
cpu_id=3
do_checkpoint_insts=true
do_quiesce=true
@ -368,10 +428,10 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -382,22 +442,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu3.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
mem_side=system.toL2Bus.slave[7]
[system.cpu3.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu3.dtb]
type=AlphaTLB
size=64
[system.cpu3.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@ -408,12 +477,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu3.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.slave[6]
[system.cpu3.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu3.interrupts]
type=AlphaInterrupts
@ -437,12 +515,17 @@ max_stack_size=67108864
output=cout
system=system
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
voltage_domain=system.voltage_domain
[system.l2c]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@ -453,28 +536,36 @@ prefetcher=Null
response_latency=20
size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
mem_side=system.membus.slave[1]
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=20
size=4194304
[system.membus]
type=CoherentBus
block_size=64
clock=1000
clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.l2c.mem_side system.system_port
slave=system.system_port system.l2c.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
@ -484,8 +575,7 @@ port=system.membus.master[0]
[system.toL2Bus]
type=CoherentBus
block_size=64
clock=500
clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@ -493,3 +583,7 @@ width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
[system.voltage_domain]
type=VoltageDomain
voltage=1.000000

4
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 8 2013 10:00:13
gem5 started Jun 8 2013 10:00:28
gem5 compiled Aug 24 2013 11:53:30
gem5 started Aug 24 2013 12:01:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second

2020
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
View file

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