stats: update eio stats
This commit is contained in:
Steve Reinhardt
parent
ecfe7dc3ef
commit
dc18352e3c
6 changed files with 1238 additions and 1104 deletions
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@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
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[system]
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type=System
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children=cpu membus physmem
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children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
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boot_osflags=a
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clock=1000
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cache_line_size=64
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clk_domain=system.clk_domain
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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@ -29,12 +30,17 @@ work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
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branchPred=Null
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checker=Null
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clock=500
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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do_checkpoint_insts=true
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do_quiesce=true
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@ -62,10 +68,10 @@ icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -76,22 +82,31 @@ prefetcher=Null
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response_latency=2
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size=262144
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=262144
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[system.cpu.dtb]
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type=AlphaTLB
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size=64
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[system.cpu.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -102,12 +117,21 @@ prefetcher=Null
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response_latency=2
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size=131072
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system=system
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tags=system.cpu.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.icache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=131072
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[system.cpu.interrupts]
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type=AlphaInterrupts
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@ -120,10 +144,10 @@ size=48
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[system.cpu.l2cache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=8
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=20
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is_top_level=false
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@ -134,16 +158,24 @@ prefetcher=Null
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response_latency=20
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size=2097152
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system=system
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tags=system.cpu.l2cache.tags
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.master[0]
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mem_side=system.membus.slave[1]
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[system.cpu.l2cache.tags]
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type=LRU
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assoc=8
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=20
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size=2097152
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[system.cpu.toL2Bus]
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type=CoherentBus
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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@ -164,10 +196,14 @@ max_stack_size=67108864
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output=cout
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system=system
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[system.cpu_clk_domain]
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type=SrcClockDomain
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clock=500
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voltage_domain=system.voltage_domain
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[system.membus]
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type=CoherentBus
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block_size=64
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clock=1000
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clk_domain=system.clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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@ -178,8 +214,8 @@ slave=system.system_port system.cpu.l2cache.mem_side
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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clk_domain=system.clk_domain
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conf_table_reported=true
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in_addr_map=true
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latency=30000
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latency_var=0
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@ -187,3 +223,7 @@ null=false
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range=0:134217727
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port=system.membus.master[0]
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[system.voltage_domain]
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type=VoltageDomain
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voltage=1.000000
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@ -1,8 +1,8 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 8 2013 10:00:13
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gem5 started Jun 8 2013 10:00:28
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gem5 compiled Aug 24 2013 11:53:30
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gem5 started Aug 24 2013 12:01:38
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
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Global frequency set at 1000000000000 ticks per second
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@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu
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sim_ticks 727072000 # Number of ticks simulated
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final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1476552 # Simulator instruction rate (inst/s)
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host_op_rate 1476467 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2146892777 # Simulator tick rate (ticks/s)
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host_mem_usage 226332 # Number of bytes of host memory used
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host_seconds 0.34 # Real time elapsed on the host
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host_inst_rate 1590478 # Simulator instruction rate (inst/s)
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host_op_rate 1590395 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2312543024 # Simulator tick rate (ticks/s)
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host_mem_usage 227540 # Number of bytes of host memory used
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host_seconds 0.31 # Real time elapsed on the host
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sim_insts 500001 # Number of instructions simulated
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sim_ops 500001 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
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@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 718 # Tr
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system.membus.trans_dist::ReadResp 718 # Transaction distribution
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system.membus.trans_dist::ReadExReq 139 # Transaction distribution
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system.membus.trans_dist::ReadExResp 139 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 1714 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 54848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 54848 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
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@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 718 # Tr
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system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 806 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 908 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count 1714 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 25792 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 29056 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 54848 # Total data (bytes)
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system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
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@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
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children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
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boot_osflags=a
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clock=1000
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cache_line_size=64
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clk_domain=system.clk_domain
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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@ -27,14 +28,19 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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system_port=system.membus.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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voltage_domain=system.voltage_domain
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[system.cpu0]
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type=TimingSimpleCPU
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children=dcache dtb icache interrupts isa itb tracer workload
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branchPred=Null
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checker=Null
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clock=500
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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do_checkpoint_insts=true
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do_quiesce=true
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@ -62,10 +68,10 @@ icache_port=system.cpu0.icache.cpu_side
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[system.cpu0.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -76,22 +82,31 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu0.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.dcache_port
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mem_side=system.toL2Bus.slave[1]
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[system.cpu0.dcache.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu0.dtb]
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type=AlphaTLB
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size=64
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[system.cpu0.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -102,12 +117,21 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu0.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.icache_port
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mem_side=system.toL2Bus.slave[0]
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[system.cpu0.icache.tags]
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type=LRU
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assoc=1
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu0.interrupts]
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type=AlphaInterrupts
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@ -136,7 +160,7 @@ type=TimingSimpleCPU
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children=dcache dtb icache interrupts isa itb tracer workload
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branchPred=Null
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checker=Null
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clock=500
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clk_domain=system.cpu_clk_domain
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cpu_id=1
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do_checkpoint_insts=true
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do_quiesce=true
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@ -164,10 +188,10 @@ icache_port=system.cpu1.icache.cpu_side
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[system.cpu1.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -178,22 +202,31 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu1.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.dcache_port
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mem_side=system.toL2Bus.slave[3]
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[system.cpu1.dcache.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu1.dtb]
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type=AlphaTLB
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size=64
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[system.cpu1.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -204,12 +237,21 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu1.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.icache_port
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mem_side=system.toL2Bus.slave[2]
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[system.cpu1.icache.tags]
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type=LRU
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assoc=1
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu1.interrupts]
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type=AlphaInterrupts
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@ -238,7 +280,7 @@ type=TimingSimpleCPU
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children=dcache dtb icache interrupts isa itb tracer workload
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branchPred=Null
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checker=Null
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clock=500
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clk_domain=system.cpu_clk_domain
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cpu_id=2
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do_checkpoint_insts=true
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do_quiesce=true
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@ -266,10 +308,10 @@ icache_port=system.cpu2.icache.cpu_side
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[system.cpu2.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -280,22 +322,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu2.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.dcache_port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu2.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu2.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu2.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -306,12 +357,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu2.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.icache_port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu2.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu2.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -340,7 +400,7 @@ type=TimingSimpleCPU
|
|||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=3
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -368,10 +428,10 @@ icache_port=system.cpu3.icache.cpu_side
|
|||
|
||||
[system.cpu3.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -382,22 +442,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu3.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.dcache_port
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu3.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu3.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu3.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -408,12 +477,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu3.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.icache_port
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu3.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu3.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -437,12 +515,17 @@ max_stack_size=67108864
|
|||
output=cout
|
||||
system=system
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -453,28 +536,36 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
slave=system.system_port system.l2c.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
@ -484,8 +575,7 @@ port=system.membus.master[0]
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -493,3 +583,7 @@ width=8
|
|||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 8 2013 10:00:13
|
||||
gem5 started Jun 8 2013 10:00:28
|
||||
gem5 compiled Aug 24 2013 11:53:30
|
||||
gem5 started Aug 24 2013 12:01:38
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000729 # Nu
|
|||
sim_ticks 729024000 # Number of ticks simulated
|
||||
final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1420709 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 517863701 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236964 # Number of bytes of host memory used
|
||||
host_seconds 1.41 # Real time elapsed on the host
|
||||
host_inst_rate 1392779 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1392763 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 507683499 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238176 # Number of bytes of host memory used
|
||||
host_seconds 1.44 # Real time elapsed on the host
|
||||
sim_insts 1999959 # Number of instructions simulated
|
||||
sim_ops 1999959 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
|
||||
|
|
@ -62,40 +62,393 @@ system.membus.trans_dist::ReadReq 2872 # Tr
|
|||
system.membus.trans_dist::ReadResp 2872 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 556 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 556 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side 6856 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6856 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side 219392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 219392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 219392 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 31051500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 4.3 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 116 # number of Writeback hits
|
||||
system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::total 276 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::total 3428 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.toL2Bus.throughput 335352471 # Throughput (bytes/s)
|
||||
system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 7524 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 244480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 244480 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks)
|
||||
|
|
@ -1048,358 +1401,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464
|
|||
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 116 # number of Writeback hits
|
||||
system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::total 276 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
|
||||
system.l2c.overall_misses::total 3428 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 7252500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 7252500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu3.data 7252500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 29010000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.inst 21101500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 21110000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 23662000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 21118500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 23662000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.inst 21129500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.data 23664500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 179110000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.inst 21101500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 21110000 # number of overall miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue