diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/control_transfer/xreturn.py
index aaffa2b92..1e8e0ba55 100644
--- a/src/arch/x86/isa/insts/control_transfer/xreturn.py
+++ b/src/arch/x86/isa/insts/control_transfer/xreturn.py
@@ -53,8 +53,14 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#   class RET(Inst):
-# 	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop RET
+{
+    # Make the default data size of rets 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    wripi t1, 0
+};
+'''