Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/fs.py: Hand merge. --HG-- extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
This commit is contained in:
commit
db5f710a7b
9 changed files with 293 additions and 190 deletions
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@ -279,6 +279,8 @@ sticky_opts.AddOptions(
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# scons 0.96.90 or later.
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# scons 0.96.90 or later.
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ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU',
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ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU',
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env['ALL_CPU_LIST']),
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env['ALL_CPU_LIST']),
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ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '',
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env['ALL_CPU_LIST']),
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BoolOption('ALPHA_TLASER',
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BoolOption('ALPHA_TLASER',
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'Model Alpha TurboLaser platform (vs. Tsunami)', False),
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'Model Alpha TurboLaser platform (vs. Tsunami)', False),
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BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
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BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
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104
configs/common/FSConfig.py
Normal file
104
configs/common/FSConfig.py
Normal file
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@ -0,0 +1,104 @@
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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||||||
|
# notice, this list of conditions and the following disclaimer;
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||||||
|
# redistributions in binary form must reproduce the above copyright
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||||||
|
# notice, this list of conditions and the following disclaimer in the
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|
# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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|
# this software without specific prior written permission.
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||||||
|
#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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||||||
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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|
#
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# Authors: Kevin Lim
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import m5
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from m5.objects import *
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from FullO3Config import *
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from SysPaths import *
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from Util import *
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script.dir = '/z/saidi/work/m5.newmem/configs/boot'
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linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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etherint = NSGigEInt(device=Parent.ethernet)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
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self = LinuxAlphaSystem()
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge()
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self.physmem = PhysicalMemory(range = AddrRange('128MB'))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(linux_image)
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.port
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self.tsunami.ide.dma = self.iobus.port
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self.tsunami.ide.config = self.iobus.port
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self.tsunami.ethernet.pio = self.iobus.port
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self.tsunami.ethernet.dma = self.iobus.port
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self.tsunami.ethernet.config = self.iobus.port
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
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read_only = True))
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self.intrctrl = IntrControl()
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self.cpu = cpu
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connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
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for each_cpu in listWrapper(self.cpu):
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each_cpu.itb = AlphaITB()
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each_cpu.dtb = AlphaDTB()
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self.cpu.clock = '2GHz'
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self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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class TsunamiRoot(Root):
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pass
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def DualRoot(clientSystem, serverSystem):
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self = Root()
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self.client = clientSystem
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self.server = serverSystem
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self.etherdump = EtherDump(file='ethertrace')
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self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
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int2 = Parent.server.tsunami.etherint[0],
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dump = Parent.etherdump)
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self.clock = '1THz'
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return self
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68
configs/common/SysPaths.py
Normal file
68
configs/common/SysPaths.py
Normal file
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@ -0,0 +1,68 @@
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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|
# modification, are permitted provided that the following conditions are
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|
# met: redistributions of source code must retain the above copyright
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||||||
|
# notice, this list of conditions and the following disclaimer;
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|
# redistributions in binary form must reproduce the above copyright
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||||||
|
# notice, this list of conditions and the following disclaimer in the
|
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|
# documentation and/or other materials provided with the distribution;
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|
# neither the name of the copyright holders nor the names of its
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|
# contributors may be used to endorse or promote products derived from
|
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|
# this software without specific prior written permission.
|
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|
#
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|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||||
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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import os, sys
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from os.path import isdir, join as joinpath
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from os import environ as env
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def disk(file):
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system()
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return joinpath(disk.dir, file)
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def binary(file):
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system()
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return joinpath(binary.dir, file)
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def script(file):
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system()
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return joinpath(script.dir, file)
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def system():
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if not system.dir:
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try:
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path = env['M5_PATH'].split(':')
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except KeyError:
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path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
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for system.dir in path:
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if os.path.isdir(system.dir):
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break
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else:
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raise ImportError, "Can't find a path to system files."
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if not binary.dir:
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binary.dir = joinpath(system.dir, 'binaries')
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if not disk.dir:
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disk.dir = joinpath(system.dir, 'disks')
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if not script.dir:
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script.dir = joinpath(system.dir, 'boot')
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system.dir = None
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binary.dir = None
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disk.dir = None
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script.dir = None
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@ -1,40 +0,0 @@
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import os, sys
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from os.path import isdir, join as joinpath
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from os import environ as env
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def disk(file):
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system()
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return joinpath(disk.dir, file)
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def binary(file):
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system()
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return joinpath(binary.dir, file)
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def script(file):
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system()
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return joinpath(script.dir, file)
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def system():
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if not system.dir:
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try:
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path = env['M5_PATH'].split(':')
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except KeyError:
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path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
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for system.dir in path:
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if os.path.isdir(system.dir):
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break
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else:
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raise ImportError, "Can't find a path to system files."
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if not binary.dir:
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binary.dir = joinpath(system.dir, 'binaries')
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if not disk.dir:
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disk.dir = joinpath(system.dir, 'disks')
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if not script.dir:
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script.dir = joinpath(system.dir, 'boot')
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system.dir = None
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binary.dir = None
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disk.dir = None
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script.dir = None
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@ -2,8 +2,10 @@ import optparse, os, sys
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|
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import m5
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import m5
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from m5.objects import *
|
from m5.objects import *
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|
m5.AddToPath('../common')
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|
from FSConfig import *
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from SysPaths import *
|
from SysPaths import *
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from FullO3Config import *
|
from Util import *
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|
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parser = optparse.OptionParser()
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parser = optparse.OptionParser()
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|
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@ -20,90 +22,27 @@ if args:
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print "Error: script doesn't take any positional arguments"
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
|
sys.exit(1)
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|
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# Base for tests is directory containing this file.
|
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test_base = os.path.dirname(__file__)
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|
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script.dir = '/z/saidi/work/m5.newmem/configs/boot'
|
|
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|
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linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
|
|
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|
|
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class CowIdeDisk(IdeDisk):
|
|
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image = CowDiskImage(child=RawDiskImage(read_only=True),
|
|
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read_only=False)
|
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|
|
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def childImage(self, ci):
|
|
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self.image.child.image_file = ci
|
|
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|
|
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class BaseTsunami(Tsunami):
|
|
||||||
ethernet = NSGigE(configdata=NSGigEPciData(),
|
|
||||||
pci_bus=0, pci_dev=1, pci_func=0)
|
|
||||||
etherint = NSGigEInt(device=Parent.ethernet)
|
|
||||||
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
|
|
||||||
pci_func=0, pci_dev=0, pci_bus=0)
|
|
||||||
|
|
||||||
class MyLinuxAlphaSystem(LinuxAlphaSystem):
|
|
||||||
iobus = Bus(bus_id=0)
|
|
||||||
membus = Bus(bus_id=1)
|
|
||||||
bridge = Bridge()
|
|
||||||
physmem = PhysicalMemory(range = AddrRange('128MB'))
|
|
||||||
bridge.side_a = iobus.port
|
|
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bridge.side_b = membus.port
|
|
||||||
physmem.port = membus.port
|
|
||||||
disk0 = CowIdeDisk(driveID='master')
|
|
||||||
disk2 = CowIdeDisk(driveID='master')
|
|
||||||
disk0.childImage(linux_image)
|
|
||||||
disk2.childImage(disk('linux-bigswap2.img'))
|
|
||||||
tsunami = BaseTsunami()
|
|
||||||
tsunami.attachIO(iobus)
|
|
||||||
tsunami.ide.pio = iobus.port
|
|
||||||
tsunami.ide.dma = iobus.port
|
|
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tsunami.ide.config = iobus.port
|
|
||||||
tsunami.ethernet.pio = iobus.port
|
|
||||||
tsunami.ethernet.dma = iobus.port
|
|
||||||
tsunami.ethernet.config = iobus.port
|
|
||||||
simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
|
|
||||||
read_only = True))
|
|
||||||
intrctrl = IntrControl()
|
|
||||||
if options.detailed:
|
if options.detailed:
|
||||||
cpu = DetailedO3CPU()
|
cpu = DetailedO3CPU()
|
||||||
|
cpu2 = DetailedO3CPU()
|
||||||
|
mem_mode = 'Timing'
|
||||||
elif options.timing:
|
elif options.timing:
|
||||||
cpu = TimingSimpleCPU()
|
cpu = TimingSimpleCPU()
|
||||||
mem_mode = 'timing'
|
cpu2 = TimingSimpleCPU()
|
||||||
|
mem_mode = 'Timing'
|
||||||
else:
|
else:
|
||||||
cpu = AtomicSimpleCPU()
|
cpu = AtomicSimpleCPU()
|
||||||
cpu.mem = membus
|
cpu2 = AtomicSimpleCPU()
|
||||||
cpu.icache_port = membus.port
|
mem_mode = 'Atomic'
|
||||||
cpu.dcache_port = membus.port
|
|
||||||
cpu.itb = AlphaITB()
|
|
||||||
cpu.dtb = AlphaDTB()
|
|
||||||
cpu.clock = '2GHz'
|
|
||||||
sim_console = SimConsole(listener=ConsoleListener(port=3456))
|
|
||||||
kernel = binary('vmlinux')
|
|
||||||
pal = binary('ts_osfpal')
|
|
||||||
console = binary('console')
|
|
||||||
boot_osflags = 'root=/dev/hda1 console=ttyS0'
|
|
||||||
|
|
||||||
class TsunamiRoot(Root):
|
|
||||||
pass
|
|
||||||
|
|
||||||
def DualRoot(clientSystem, serverSystem):
|
|
||||||
self = Root()
|
|
||||||
self.client = clientSystem
|
|
||||||
self.server = serverSystem
|
|
||||||
|
|
||||||
self.etherdump = EtherDump(file='ethertrace')
|
|
||||||
self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
|
|
||||||
int2 = Parent.server.tsunami.etherint[0],
|
|
||||||
dump = Parent.etherdump)
|
|
||||||
self.clock = '1THz'
|
|
||||||
return self
|
|
||||||
|
|
||||||
if options.dual:
|
if options.dual:
|
||||||
root = DualRoot(
|
root = DualRoot(
|
||||||
MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
|
MyLinuxAlphaSystem(cpu, mem_mode, linux_image),
|
||||||
MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
|
MyLinuxAlphaSystem(cpu2, mem_mode, linux_image))
|
||||||
|
root.client.readfile = script('netperf-stream-nt-client.rcS')
|
||||||
|
root.server.readfile = script('netperf-server.rcS')
|
||||||
else:
|
else:
|
||||||
root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem())
|
root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem(cpu, mem_mode, linux_image))
|
||||||
|
|
||||||
m5.instantiate(root)
|
m5.instantiate(root)
|
||||||
|
|
||||||
|
|
|
@ -160,7 +160,8 @@ if 'O3CPU' in env['CPU_MODELS']:
|
||||||
''')
|
''')
|
||||||
if env['USE_CHECKER']:
|
if env['USE_CHECKER']:
|
||||||
sources += Split('o3/checker_builder.cc')
|
sources += Split('o3/checker_builder.cc')
|
||||||
env['SMT_CPU_MODELS'].append('O3CPU')
|
else:
|
||||||
|
env['SMT_CPU_MODELS'].append('O3CPU') # Checker doesn't support SMT right now
|
||||||
|
|
||||||
if 'OzoneCPU' in env['CPU_MODELS']:
|
if 'OzoneCPU' in env['CPU_MODELS']:
|
||||||
need_bp_unit = True
|
need_bp_unit = True
|
||||||
|
|
|
@ -1,91 +1,101 @@
|
||||||
from m5 import build_env
|
from m5 import build_env
|
||||||
from m5.config import *
|
from m5.config import *
|
||||||
from BaseCPU import BaseCPU
|
from BaseCPU import BaseCPU
|
||||||
|
from Checker import O3Checker
|
||||||
|
|
||||||
class DerivO3CPU(BaseCPU):
|
class DerivO3CPU(BaseCPU):
|
||||||
type = 'DerivO3CPU'
|
type = 'DerivO3CPU'
|
||||||
activity = Param.Unsigned("Initial count")
|
activity = Param.Unsigned(0, "Initial count")
|
||||||
numThreads = Param.Unsigned("number of HW thread contexts")
|
numThreads = Param.Unsigned(1, "number of HW thread contexts")
|
||||||
|
|
||||||
checker = Param.BaseCPU(NULL, "checker")
|
if build_env['USE_CHECKER']:
|
||||||
|
if not build_env['FULL_SYSTEM']:
|
||||||
|
checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
|
||||||
|
exitOnError=True,
|
||||||
|
warnOnlyOnLoadError=False),
|
||||||
|
"checker")
|
||||||
|
else:
|
||||||
|
checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker")
|
||||||
|
checker.itb = Parent.itb
|
||||||
|
checker.dtb = Parent.dtb
|
||||||
|
|
||||||
cachePorts = Param.Unsigned("Cache Ports")
|
cachePorts = Param.Unsigned("Cache Ports")
|
||||||
icache_port = Port("Instruction Port")
|
icache_port = Port("Instruction Port")
|
||||||
dcache_port = Port("Data Port")
|
dcache_port = Port("Data Port")
|
||||||
|
|
||||||
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
|
decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
|
||||||
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
|
renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
|
||||||
iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
|
iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
|
||||||
"delay")
|
"delay")
|
||||||
commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
|
commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
|
||||||
fetchWidth = Param.Unsigned("Fetch width")
|
fetchWidth = Param.Unsigned(8, "Fetch width")
|
||||||
|
|
||||||
renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
|
renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
|
||||||
iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
|
iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
|
||||||
"delay")
|
"delay")
|
||||||
commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
|
commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
|
||||||
fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
|
fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
|
||||||
decodeWidth = Param.Unsigned("Decode width")
|
decodeWidth = Param.Unsigned(8, "Decode width")
|
||||||
|
|
||||||
iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
|
iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
|
||||||
"delay")
|
"delay")
|
||||||
commitToRenameDelay = Param.Unsigned("Commit to rename delay")
|
commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
|
||||||
decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
|
decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
|
||||||
renameWidth = Param.Unsigned("Rename width")
|
renameWidth = Param.Unsigned(8, "Rename width")
|
||||||
|
|
||||||
commitToIEWDelay = Param.Unsigned("Commit to "
|
commitToIEWDelay = Param.Unsigned(1, "Commit to "
|
||||||
"Issue/Execute/Writeback delay")
|
"Issue/Execute/Writeback delay")
|
||||||
renameToIEWDelay = Param.Unsigned("Rename to "
|
renameToIEWDelay = Param.Unsigned(2, "Rename to "
|
||||||
"Issue/Execute/Writeback delay")
|
"Issue/Execute/Writeback delay")
|
||||||
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
|
issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
|
||||||
"to the IEW stage)")
|
"to the IEW stage)")
|
||||||
dispatchWidth = Param.Unsigned("Dispatch width")
|
dispatchWidth = Param.Unsigned(8, "Dispatch width")
|
||||||
issueWidth = Param.Unsigned("Issue width")
|
issueWidth = Param.Unsigned(8, "Issue width")
|
||||||
wbWidth = Param.Unsigned("Writeback width")
|
wbWidth = Param.Unsigned(8, "Writeback width")
|
||||||
wbDepth = Param.Unsigned("Writeback depth")
|
wbDepth = Param.Unsigned(1, "Writeback depth")
|
||||||
fuPool = Param.FUPool(NULL, "Functional Unit pool")
|
fuPool = Param.FUPool("Functional Unit pool")
|
||||||
|
|
||||||
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
|
iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
|
||||||
"delay")
|
"delay")
|
||||||
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
|
renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
|
||||||
commitWidth = Param.Unsigned("Commit width")
|
commitWidth = Param.Unsigned(8, "Commit width")
|
||||||
squashWidth = Param.Unsigned("Squash width")
|
squashWidth = Param.Unsigned(8, "Squash width")
|
||||||
trapLatency = Param.Tick("Trap latency")
|
trapLatency = Param.Tick(13, "Trap latency")
|
||||||
fetchTrapLatency = Param.Tick("Fetch trap latency")
|
fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
|
||||||
|
|
||||||
backComSize = Param.Unsigned("Time buffer size for backwards communication")
|
backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
|
||||||
forwardComSize = Param.Unsigned("Time buffer size for forward communication")
|
forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
|
||||||
|
|
||||||
predType = Param.String("Branch predictor type ('local', 'tournament')")
|
predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
|
||||||
localPredictorSize = Param.Unsigned("Size of local predictor")
|
localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
|
||||||
localCtrBits = Param.Unsigned("Bits per counter")
|
localCtrBits = Param.Unsigned(2, "Bits per counter")
|
||||||
localHistoryTableSize = Param.Unsigned("Size of local history table")
|
localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
|
||||||
localHistoryBits = Param.Unsigned("Bits for the local history")
|
localHistoryBits = Param.Unsigned(11, "Bits for the local history")
|
||||||
globalPredictorSize = Param.Unsigned("Size of global predictor")
|
globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
|
||||||
globalCtrBits = Param.Unsigned("Bits per counter")
|
globalCtrBits = Param.Unsigned(2, "Bits per counter")
|
||||||
globalHistoryBits = Param.Unsigned("Bits of history")
|
globalHistoryBits = Param.Unsigned(4096, "Bits of history")
|
||||||
choicePredictorSize = Param.Unsigned("Size of choice predictor")
|
choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
|
||||||
choiceCtrBits = Param.Unsigned("Bits of choice counters")
|
choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
|
||||||
|
|
||||||
BTBEntries = Param.Unsigned("Number of BTB entries")
|
BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
|
||||||
BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
|
BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
|
||||||
|
|
||||||
RASSize = Param.Unsigned("RAS size")
|
RASSize = Param.Unsigned(16, "RAS size")
|
||||||
|
|
||||||
LQEntries = Param.Unsigned("Number of load queue entries")
|
LQEntries = Param.Unsigned(32, "Number of load queue entries")
|
||||||
SQEntries = Param.Unsigned("Number of store queue entries")
|
SQEntries = Param.Unsigned(32, "Number of store queue entries")
|
||||||
LFSTSize = Param.Unsigned("Last fetched store table size")
|
LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
|
||||||
SSITSize = Param.Unsigned("Store set ID table size")
|
SSITSize = Param.Unsigned(1024, "Store set ID table size")
|
||||||
|
|
||||||
numRobs = Param.Unsigned("Number of Reorder Buffers");
|
numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
|
||||||
|
|
||||||
numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
|
numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
|
||||||
numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
|
numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
|
||||||
"registers")
|
"registers")
|
||||||
numIQEntries = Param.Unsigned("Number of instruction queue entries")
|
numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
|
||||||
numROBEntries = Param.Unsigned("Number of reorder buffer entries")
|
numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
|
||||||
|
|
||||||
instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
|
instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
|
||||||
|
|
||||||
function_trace = Param.Bool(False, "Enable function trace")
|
function_trace = Param.Bool(False, "Enable function trace")
|
||||||
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
# -*- mode:python -*-
|
# -*- mode:python -*-
|
||||||
|
|
||||||
# Copyright (c) 2004-2005 The Regents of The University of Michigan
|
# Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
# All rights reserved.
|
# All rights reserved.
|
||||||
#
|
#
|
||||||
# Redistribution and use in source and binary forms, with or without
|
# Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -25,6 +25,9 @@
|
||||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
#
|
||||||
|
# Authors: Steve Reinhardt
|
||||||
|
# Kevin Lim
|
||||||
|
|
||||||
import os
|
import os
|
||||||
import sys
|
import sys
|
||||||
|
@ -136,7 +139,8 @@ def update_test_string(target, source, env):
|
||||||
|
|
||||||
updateAction = env.Action(update_test, update_test_string)
|
updateAction = env.Action(update_test, update_test_string)
|
||||||
|
|
||||||
def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=15):
|
def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref',
|
||||||
|
timeout=15):
|
||||||
"""Define a test.
|
"""Define a test.
|
||||||
|
|
||||||
Args:
|
Args:
|
||||||
|
@ -153,12 +157,23 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
|
||||||
default_refdir = True
|
default_refdir = True
|
||||||
if len(cpu_list) == 0:
|
if len(cpu_list) == 0:
|
||||||
cpu_list = env['CPU_MODELS']
|
cpu_list = env['CPU_MODELS']
|
||||||
|
if env['TEST_CPU_MODELS']:
|
||||||
|
temp_cpu_list = []
|
||||||
|
for i in env['TEST_CPU_MODELS']:
|
||||||
|
if i in cpu_list:
|
||||||
|
temp_cpu_list.append(i)
|
||||||
|
cpu_list = temp_cpu_list
|
||||||
|
# Code commented out that shows the general structure if we want to test
|
||||||
|
# different OS's as well.
|
||||||
# if len(os_list) == 0:
|
# if len(os_list) == 0:
|
||||||
# raise RuntimeError, "No OS specified"
|
# for test_cpu in cpu_list:
|
||||||
|
# build_cpu_test(env, category, '', test_cpu, refdir, timeout)
|
||||||
# else:
|
# else:
|
||||||
# for test_os in os_list:
|
# for test_os in os_list:
|
||||||
# build_cpu_test(env, category, test_os, cpu_list, refdir, timeout)
|
# for test_cpu in cpu_list:
|
||||||
# Loop through CPU models and generate proper options, ref directories for each
|
# build_cpu_test(env, category, test_os, test_cpu, refdir,
|
||||||
|
# timeout)
|
||||||
|
# Loop through CPU models and generate proper options, ref directories
|
||||||
for cpu in cpu_list:
|
for cpu in cpu_list:
|
||||||
test_os = ''
|
test_os = ''
|
||||||
if cpu == "AtomicSimpleCPU":
|
if cpu == "AtomicSimpleCPU":
|
||||||
|
@ -171,7 +186,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
|
||||||
raise TypeError, "Unknown CPU model specified"
|
raise TypeError, "Unknown CPU model specified"
|
||||||
|
|
||||||
if default_refdir:
|
if default_refdir:
|
||||||
# Reference stats located in ref/arch/os/cpu or ref/arch/cpu if no OS specified
|
# Reference stats located in ref/arch/os/cpu or ref/arch/cpu
|
||||||
|
# if no OS specified
|
||||||
test_refdir = os.path.join(refdir, env['TARGET_ISA'])
|
test_refdir = os.path.join(refdir, env['TARGET_ISA'])
|
||||||
if test_os != '':
|
if test_os != '':
|
||||||
test_refdir = os.path.join(test_refdir, test_os)
|
test_refdir = os.path.join(test_refdir, test_os)
|
||||||
|
@ -202,8 +218,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
|
||||||
else:
|
else:
|
||||||
cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr]
|
cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr]
|
||||||
|
|
||||||
env.Command([stdout_string, stderr_string, m5stats_string], [env.M5Binary, 'run.py'],
|
env.Command([stdout_string, stderr_string, m5stats_string],
|
||||||
' '.join(cmd))
|
[env.M5Binary, 'run.py'], ' '.join(cmd))
|
||||||
|
|
||||||
# order of targets is important... see check_test
|
# order of targets is important... see check_test
|
||||||
env.Command([outdiff_string, statsdiff_string, status_string],
|
env.Command([outdiff_string, statsdiff_string, status_string],
|
||||||
|
@ -212,10 +228,12 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
|
||||||
|
|
||||||
# phony target to echo status
|
# phony target to echo status
|
||||||
if env['update_ref']:
|
if env['update_ref']:
|
||||||
p = env.Command(cpu_option[1] + '_update', [ref_stats, m5stats_string, status_string],
|
p = env.Command(cpu_option[1] + '_update',
|
||||||
|
[ref_stats, m5stats_string, status_string],
|
||||||
updateAction)
|
updateAction)
|
||||||
else:
|
else:
|
||||||
p = env.Command(cpu_option[1] + '_print', [status_string], printAction)
|
p = env.Command(cpu_option[1] + '_print', [status_string],
|
||||||
|
printAction)
|
||||||
env.AlwaysBuild(p)
|
env.AlwaysBuild(p)
|
||||||
|
|
||||||
env.Tests.setdefault(category, [])
|
env.Tests.setdefault(category, [])
|
||||||
|
|
1
tests/halt.sh
Normal file
1
tests/halt.sh
Normal file
|
@ -0,0 +1 @@
|
||||||
|
m5 exit
|
Loading…
Reference in a new issue