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stats: update and fix e273e86a873d

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This commit is contained in:
Curtis Dunham 2016-05-31 16:55:47 +01:00
parent c661cc75ec
commit dafec4a515
88 changed files with 52940 additions and 3726 deletions
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62
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.847227 # Nu
sim_ticks 2847227406000 # Number of ticks simulated
final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 172654 # Simulator instruction rate (inst/s)
host_op_rate 209070 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3861033235 # Simulator tick rate (ticks/s)
host_mem_usage 617124 # Number of bytes of host memory used
host_seconds 737.43 # Real time elapsed on the host
host_inst_rate 111277 # Simulator instruction rate (inst/s)
host_op_rate 134747 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2488466073 # Simulator tick rate (ticks/s)
host_mem_usage 617520 # Number of bytes of host memory used
host_seconds 1144.17 # Real time elapsed on the host
sim_insts 127319545 # Number of instructions simulated
sim_ops 154173476 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -441,9 +441,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777
system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 17339980 # DTB read hits
system.cpu0.dtb.read_hits 17339981 # DTB read hits
system.cpu0.dtb.read_misses 61941 # DTB read misses
system.cpu0.dtb.write_hits 14540399 # DTB write hits
system.cpu0.dtb.write_hits 14540400 # DTB write hits
system.cpu0.dtb.write_misses 6479 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -454,12 +454,12 @@ system.cpu0.dtb.align_faults 1354 # Nu
system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17401921 # DTB read accesses
system.cpu0.dtb.write_accesses 14546878 # DTB write accesses
system.cpu0.dtb.read_accesses 17401922 # DTB read accesses
system.cpu0.dtb.write_accesses 14546879 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 31880379 # DTB hits
system.cpu0.dtb.hits 31880381 # DTB hits
system.cpu0.dtb.misses 68420 # DTB misses
system.cpu0.dtb.accesses 31948799 # DTB accesses
system.cpu0.dtb.accesses 31948801 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -593,9 +593,9 @@ system.cpu0.tickCycles 128530134 # Nu
system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 715130 # number of replacements
system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 30394668 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 42.471890 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy
@ -605,22 +605,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63780149 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63780149 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15810331 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15810331 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 13424811 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 13424811 # number of WriteReq hits
system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 29235142 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 29235142 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 29555582 # number of overall hits
system.cpu0.dcache.overall_hits::total 29555582 # number of overall hits
system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits
system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses
@ -649,20 +649,20 @@ system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500
system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274054 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16274054 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005712 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 14005712 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 30279766 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30279766 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30736689 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30736689 # number of overall (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses

62
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu
sim_ticks 2858505242500 # Number of ticks simulated
final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 171882 # Simulator instruction rate (inst/s)
host_op_rate 207819 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4390877747 # Simulator tick rate (ticks/s)
host_mem_usage 578076 # Number of bytes of host memory used
host_seconds 651.01 # Real time elapsed on the host
host_inst_rate 125507 # Simulator instruction rate (inst/s)
host_op_rate 151748 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3206183180 # Simulator tick rate (ticks/s)
host_mem_usage 578080 # Number of bytes of host memory used
host_seconds 891.56 # Real time elapsed on the host
sim_insts 111897168 # Number of instructions simulated
sim_ops 135292215 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -403,9 +403,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866
system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 24710832 # DTB read hits
system.cpu.dtb.read_hits 24710833 # DTB read hits
system.cpu.dtb.read_misses 59358 # DTB read misses
system.cpu.dtb.write_hits 19424403 # DTB write hits
system.cpu.dtb.write_hits 19424404 # DTB write hits
system.cpu.dtb.write_misses 6793 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -416,12 +416,12 @@ system.cpu.dtb.align_faults 1526 # Nu
system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 24770190 # DTB read accesses
system.cpu.dtb.write_accesses 19431196 # DTB write accesses
system.cpu.dtb.read_accesses 24770191 # DTB read accesses
system.cpu.dtb.write_accesses 19431197 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 44135235 # DTB hits
system.cpu.dtb.hits 44135237 # DTB hits
system.cpu.dtb.misses 66151 # DTB misses
system.cpu.dtb.accesses 44201386 # DTB accesses
system.cpu.dtb.accesses 44201388 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -551,9 +551,9 @@ system.cpu.tickCycles 228131430 # Nu
system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 842468 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42541757 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 50.465915 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 102
system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 175934547 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 175934547 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23016254 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23016254 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18262412 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18262412 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41278666 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41278666 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 41634968 # number of overall hits
system.cpu.dcache.overall_hits::total 41634968 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 41278668 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41278668 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 41634970 # number of overall hits
system.cpu.dcache.overall_hits::total 41634970 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses
@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 43652936479
system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23510096 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23510096 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 18810393 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 18810393 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 23510097 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23510097 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 18810394 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 18810394 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42320489 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42320489 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42846661 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42846661 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 42320491 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42320491 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42846663 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42846663 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses

126
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu
sim_ticks 2832862976500 # Number of ticks simulated
final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 92547 # Simulator instruction rate (inst/s)
host_op_rate 112251 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2318051416 # Simulator tick rate (ticks/s)
host_inst_rate 63021 # Simulator instruction rate (inst/s)
host_op_rate 76439 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1578508192 # Simulator tick rate (ticks/s)
host_mem_usage 579360 # Number of bytes of host memory used
host_seconds 1222.09 # Real time elapsed on the host
host_seconds 1794.65 # Real time elapsed on the host
sim_insts 113100501 # Number of instructions simulated
sim_ops 137180951 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -395,9 +395,9 @@ system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7544
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17252 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 24576303 # DTB read hits
system.cpu.checker.dtb.read_hits 24576304 # DTB read hits
system.cpu.checker.dtb.read_misses 8296 # DTB read misses
system.cpu.checker.dtb.write_hits 19632669 # DTB write hits
system.cpu.checker.dtb.write_hits 19632670 # DTB write hits
system.cpu.checker.dtb.write_misses 1412 # DTB write misses
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
@ -408,12 +408,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu
system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 24584599 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19634081 # DTB write accesses
system.cpu.checker.dtb.read_accesses 24584600 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19634082 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 44208972 # DTB hits
system.cpu.checker.dtb.hits 44208974 # DTB hits
system.cpu.checker.dtb.misses 9708 # DTB misses
system.cpu.checker.dtb.accesses 44218680 # DTB accesses
system.cpu.checker.dtb.accesses 44218682 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -568,9 +568,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718
system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 25410889 # DTB read hits
system.cpu.dtb.read_hits 25410890 # DTB read hits
system.cpu.dtb.read_misses 62740 # DTB read misses
system.cpu.dtb.write_hits 19865162 # DTB write hits
system.cpu.dtb.write_hits 19865163 # DTB write hits
system.cpu.dtb.write_misses 9628 # DTB write misses
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
@ -581,12 +581,12 @@ system.cpu.dtb.align_faults 362 # Nu
system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25473629 # DTB read accesses
system.cpu.dtb.write_accesses 19874790 # DTB write accesses
system.cpu.dtb.read_accesses 25473630 # DTB read accesses
system.cpu.dtb.write_accesses 19874791 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 45276051 # DTB hits
system.cpu.dtb.hits 45276053 # DTB hits
system.cpu.dtb.misses 72368 # DTB misses
system.cpu.dtb.accesses 45348419 # DTB accesses
system.cpu.dtb.accesses 45348421 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -690,7 +690,7 @@ system.cpu.itb.accesses 66008446 # DT
system.cpu.numCycles 278423951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken
@ -704,21 +704,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 188 #
system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle
system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking
@ -728,7 +728,7 @@ system.cpu.decode.BranchMispred 467954 # Nu
system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle
system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running
@ -759,14 +759,14 @@ system.cpu.iq.iqSquashedInstsIssued 260968 # Nu
system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
@ -775,7 +775,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
@ -848,7 +848,7 @@ system.cpu.iq.FU_type_0::total 143038678 # Ty
system.cpu.iq.rate 0.513744 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads
@ -892,30 +892,30 @@ system.cpu.iew.exec_stores 20827406 # Nu
system.cpu.iew.exec_rate 0.510511 # Inst execution rate
system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63237138 # num instructions producing a value
system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value
system.cpu.iew.wb_producers 63237137 # num instructions producing a value
system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113255406 # Number of instructions committed
system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -961,11 +961,11 @@ system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction
system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389119867 # The number of ROB reads
system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389119868 # The number of ROB reads
system.cpu.rob.rob_writes 292294903 # The number of ROB writes
system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113100501 # Number of Instructions Simulated
system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated
@ -973,19 +973,19 @@ system.cpu.cpi 2.461739 # CP
system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads
system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155524958 # number of integer regfile reads
system.cpu.int_regfile_reads 155524954 # number of integer regfile reads
system.cpu.int_regfile_writes 88488763 # number of integer regfile writes
system.cpu.fp_regfile_reads 9529 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu.cc_regfile_reads 502156064 # number of cc regfile reads
system.cpu.cc_regfile_reads 502156067 # number of cc regfile reads
system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes
system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads
system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes
system.cpu.dcache.tags.replacements 838747 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
@ -995,22 +995,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 131
system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits
system.cpu.dcache.overall_hits::total 39152130 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits
system.cpu.dcache.overall_hits::total 39152132 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses
@ -1037,20 +1037,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 244199157697
system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses

5987
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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File diff suppressed because it is too large Load diff

116
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu
sim_ticks 2832862976500 # Number of ticks simulated
final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 116306 # Simulator instruction rate (inst/s)
host_op_rate 141069 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2913147103 # Simulator tick rate (ticks/s)
host_mem_usage 578076 # Number of bytes of host memory used
host_seconds 972.44 # Real time elapsed on the host
host_inst_rate 70501 # Simulator instruction rate (inst/s)
host_op_rate 85511 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1765850548 # Simulator tick rate (ticks/s)
host_mem_usage 578080 # Number of bytes of host memory used
host_seconds 1604.25 # Real time elapsed on the host
sim_insts 113100501 # Number of instructions simulated
sim_ops 137180951 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -429,9 +429,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718
system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 25410889 # DTB read hits
system.cpu.dtb.read_hits 25410890 # DTB read hits
system.cpu.dtb.read_misses 62740 # DTB read misses
system.cpu.dtb.write_hits 19865162 # DTB write hits
system.cpu.dtb.write_hits 19865163 # DTB write hits
system.cpu.dtb.write_misses 9628 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -442,12 +442,12 @@ system.cpu.dtb.align_faults 362 # Nu
system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25473629 # DTB read accesses
system.cpu.dtb.write_accesses 19874790 # DTB write accesses
system.cpu.dtb.read_accesses 25473630 # DTB read accesses
system.cpu.dtb.write_accesses 19874791 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 45276051 # DTB hits
system.cpu.dtb.hits 45276053 # DTB hits
system.cpu.dtb.misses 72368 # DTB misses
system.cpu.dtb.accesses 45348419 # DTB accesses
system.cpu.dtb.accesses 45348421 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -551,7 +551,7 @@ system.cpu.itb.accesses 66008446 # DT
system.cpu.numCycles 278423951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken
@ -565,21 +565,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 188 #
system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle
system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking
@ -589,7 +589,7 @@ system.cpu.decode.BranchMispred 467954 # Nu
system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle
system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running
@ -620,14 +620,14 @@ system.cpu.iq.iqSquashedInstsIssued 260968 # Nu
system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
@ -636,7 +636,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
@ -709,7 +709,7 @@ system.cpu.iq.FU_type_0::total 143038678 # Ty
system.cpu.iq.rate 0.513744 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads
@ -753,30 +753,30 @@ system.cpu.iew.exec_stores 20827406 # Nu
system.cpu.iew.exec_rate 0.510511 # Inst execution rate
system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63237138 # num instructions producing a value
system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value
system.cpu.iew.wb_producers 63237137 # num instructions producing a value
system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113255406 # Number of instructions committed
system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -822,11 +822,11 @@ system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction
system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389119867 # The number of ROB reads
system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389119868 # The number of ROB reads
system.cpu.rob.rob_writes 292294903 # The number of ROB writes
system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113100501 # Number of Instructions Simulated
system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated
@ -834,19 +834,19 @@ system.cpu.cpi 2.461739 # CP
system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads
system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155524958 # number of integer regfile reads
system.cpu.int_regfile_reads 155524954 # number of integer regfile reads
system.cpu.int_regfile_writes 88488761 # number of integer regfile writes
system.cpu.fp_regfile_reads 9529 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu.cc_regfile_reads 502156058 # number of cc regfile reads
system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads
system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes
system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads
system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes
system.cpu.dcache.tags.replacements 838747 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
@ -856,22 +856,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 131
system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits
system.cpu.dcache.overall_hits::total 39152130 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits
system.cpu.dcache.overall_hits::total 39152132 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses
@ -898,20 +898,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 244199157697
system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses

64
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.823729 # Nu
sim_ticks 2823728611500 # Number of ticks simulated
final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 263665 # Simulator instruction rate (inst/s)
host_op_rate 319829 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6058824639 # Simulator tick rate (ticks/s)
host_mem_usage 584988 # Number of bytes of host memory used
host_seconds 466.05 # Real time elapsed on the host
host_inst_rate 192143 # Simulator instruction rate (inst/s)
host_op_rate 233071 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4415299854 # Simulator tick rate (ticks/s)
host_mem_usage 584992 # Number of bytes of host memory used
host_seconds 639.53 # Real time elapsed on the host
sim_insts 122881667 # Number of instructions simulated
sim_ops 149056790 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -432,9 +432,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4099
system.cpu0.dtb.walker.walkRequestOrigin::total 9070 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 12098970 # DTB read hits
system.cpu0.dtb.read_hits 12098971 # DTB read hits
system.cpu0.dtb.read_misses 4249 # DTB read misses
system.cpu0.dtb.write_hits 9143698 # DTB write hits
system.cpu0.dtb.write_hits 9143699 # DTB write hits
system.cpu0.dtb.write_misses 722 # DTB write misses
system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA
@ -445,12 +445,12 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 12103219 # DTB read accesses
system.cpu0.dtb.write_accesses 9144420 # DTB write accesses
system.cpu0.dtb.read_accesses 12103220 # DTB read accesses
system.cpu0.dtb.write_accesses 9144421 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 21242668 # DTB hits
system.cpu0.dtb.hits 21242670 # DTB hits
system.cpu0.dtb.misses 4971 # DTB misses
system.cpu0.dtb.accesses 21247639 # DTB accesses
system.cpu0.dtb.accesses 21247641 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -535,7 +535,7 @@ system.cpu0.num_conditional_control_insts 7357632 # n
system.cpu0.num_int_insts 58995481 # number of integer instructions
system.cpu0.num_fp_insts 4380 # number of float instructions
system.cpu0.num_int_register_reads 108779991 # number of times the integer registers were read
system.cpu0.num_int_register_writes 41129871 # number of times the integer registers were written
system.cpu0.num_int_register_writes 41129875 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 204568240 # number of times the CC registers were read
@ -585,9 +585,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu0.op_class::total 68312506 # Class of executed instruction
system.cpu0.dcache.tags.replacements 833701 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 45908567 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 45908569 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 834213 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 55.032188 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 55.032191 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.062806 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor
@ -603,18 +603,18 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 193086181 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 193086181 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11466813 # number of ReadReq hits
system.cpu0.dcache.tags.tag_accesses 193086189 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 193086189 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 6693194 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25812081 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 8805126 # number of WriteReq hits
system.cpu0.dcache.ReadReq_hits::total 25812082 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 8805127 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 4155645 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18793363 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18793364 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178315 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56771 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67457 # number of SoftPFReq hits
@ -630,16 +630,16 @@ system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76661
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73616 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92634 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20271939 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu0.data 20271941 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 6285887 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7198779 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 10848839 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 44605444 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20450254 # number of overall hits
system.cpu0.dcache.demand_hits::total 44605446 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20450256 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 6342658 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7266236 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 10934832 # number of overall hits
system.cpu0.dcache.overall_hits::total 44993980 # number of overall hits
system.cpu0.dcache.overall_hits::total 44993982 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 170779 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 51895 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses
@ -695,16 +695,16 @@ system.cpu0.dcache.overall_miss_latency::cpu1.data 2109020500
system.cpu0.dcache.overall_miss_latency::cpu2.data 6256851496 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 64471692312 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 72837564308 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637592 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637593 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 3655910 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4131919 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 6912790 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26338211 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917441 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26338212 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917442 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 2716710 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3254660 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 5382372 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 20271183 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 20271184 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232245 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76230 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86787 # number of SoftPFReq accesses(hits+misses)
@ -720,16 +720,16 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76661
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73616 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92661 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 460703 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 20555033 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu0.data 20555035 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 6372620 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7386579 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 12295162 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 46609394 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 20787278 # number of overall (read+write) accesses
system.cpu0.dcache.demand_accesses::total 46609396 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 20787280 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 6448850 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7473366 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 12423880 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 47133374 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 47133376 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014675 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014195 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020296 # miss rate for ReadReq accesses

98
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.804583 # Nu
sim_ticks 2804582834000 # Number of ticks simulated
final_tick 2804582834000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 128680 # Simulator instruction rate (inst/s)
host_op_rate 156182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3087037891 # Simulator tick rate (ticks/s)
host_mem_usage 586780 # Number of bytes of host memory used
host_seconds 908.50 # Real time elapsed on the host
host_inst_rate 77550 # Simulator instruction rate (inst/s)
host_op_rate 94124 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1860425573 # Simulator tick rate (ticks/s)
host_mem_usage 586788 # Number of bytes of host memory used
host_seconds 1507.50 # Real time elapsed on the host
sim_insts 116905819 # Number of instructions simulated
sim_ops 141891765 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -459,9 +459,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5107
system.cpu0.dtb.walker.walkRequestOrigin::total 64239 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 13759363 # DTB read hits
system.cpu0.dtb.read_hits 13759364 # DTB read hits
system.cpu0.dtb.read_misses 49716 # DTB read misses
system.cpu0.dtb.write_hits 10256386 # DTB write hits
system.cpu0.dtb.write_hits 10256387 # DTB write hits
system.cpu0.dtb.write_misses 9416 # DTB write misses
system.cpu0.dtb.flush_tlb 182 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA
@ -472,12 +472,12 @@ system.cpu0.dtb.align_faults 822 # Nu
system.cpu0.dtb.prefetch_faults 1317 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 13809079 # DTB read accesses
system.cpu0.dtb.write_accesses 10265802 # DTB write accesses
system.cpu0.dtb.read_accesses 13809080 # DTB read accesses
system.cpu0.dtb.write_accesses 10265803 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 24015749 # DTB hits
system.cpu0.dtb.hits 24015751 # DTB hits
system.cpu0.dtb.misses 59132 # DTB misses
system.cpu0.dtb.accesses 24074881 # DTB accesses
system.cpu0.dtb.accesses 24074883 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -584,7 +584,7 @@ system.cpu0.itb.accesses 19913313 # DT
system.cpu0.numCycles 106457732 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 39778101 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.icacheStallCycles 39778104 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 102329331 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 26563319 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 19038002 # Number of branches that fetch has predicted taken
@ -599,11 +599,11 @@ system.cpu0.fetch.IcacheWaitRetryStallCycles 483
system.cpu0.fetch.CacheLines 19903626 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 349456 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 4039 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 103827958 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::samples 103827961 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.185750 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.289369 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 75543670 72.76% 72.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 75543673 72.76% 72.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 3812816 3.67% 76.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 2351525 2.26% 78.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 7978907 7.68% 86.38% # Number of instructions fetched each cycle (Total)
@ -615,10 +615,10 @@ system.cpu0.fetch.rateDist::8 4481059 4.32% 100.00% # Nu
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 103827958 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 103827961 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.249520 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.961220 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 27448347 # Number of cycles decode is idle
system.cpu0.decode.IdleCycles 27448350 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 58255743 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 15281337 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1431455 # Number of cycles decode is unblocking
@ -628,7 +628,7 @@ system.cpu0.decode.BranchMispred 143809 # Nu
system.cpu0.decode.DecodedInsts 84464795 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 475260 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1410775 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 28253862 # Number of cycles rename is idle
system.cpu0.rename.IdleCycles 28253865 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 6710507 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 43964237 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 15899574 # Number of cycles rename is running
@ -658,11 +658,11 @@ system.cpu0.iq.iqSquashedInstsIssued 90659 # Nu
system.cpu0.iq.iqSquashedInstsExamined 10605329 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 23154537 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 112514 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 103827958 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::samples 103827961 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.719932 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.414021 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 73906108 71.18% 71.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 73906111 71.18% 71.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10009384 9.64% 80.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 7640879 7.36% 88.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 6355260 6.12% 94.30% # Number of insts issued each cycle
@ -674,7 +674,7 @@ system.cpu0.iq.issued_per_cycle::8 217363 0.21% 100.00% # Nu
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 103827958 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 103827961 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 96059 8.82% 8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 1 0.00% 8.82% # attempts to use FU when none available
@ -747,7 +747,7 @@ system.cpu0.iq.FU_type_0::total 74749052 # Ty
system.cpu0.iq.rate 0.702148 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1089511 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.014576 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 254491356 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_reads 254491359 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 89595521 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 72529451 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 14876 # Number of floating instruction queue reads
@ -798,11 +798,11 @@ system.cpu0.iew.wb_fanout 0.574308 # av
system.cpu0.commit.commitSquashedInsts 10562082 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 945273 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 353712 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 101401285 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::samples 101401288 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.674752 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.564672 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 74703088 73.67% 73.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 74703091 73.67% 73.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 12065534 11.90% 85.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 6043146 5.96% 91.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2565114 2.53% 94.06% # Number of insts commited each cycle
@ -814,7 +814,7 @@ system.cpu0.commit.committed_per_cycle::8 1700075 1.68% 100.00% # N
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 101401285 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 101401288 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 56174796 # Number of instructions committed
system.cpu0.commit.committedOps 68420730 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
@ -861,10 +861,10 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 68420730 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1700075 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 166296825 # The number of ROB reads
system.cpu0.rob.rob_reads 166296828 # The number of ROB reads
system.cpu0.rob.rob_writes 160391499 # The number of ROB writes
system.cpu0.timesIdled 400345 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 2629774 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.idleCycles 2629771 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2956130676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 56094495 # Number of Instructions Simulated
system.cpu0.committedOps 68340429 # Number of Ops (including micro ops) Simulated
@ -872,19 +872,19 @@ system.cpu0.cpi 1.897829 # CP
system.cpu0.cpi_total 1.897829 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.526918 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.526918 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 80764366 # number of integer regfile reads
system.cpu0.int_regfile_reads 80764362 # number of integer regfile reads
system.cpu0.int_regfile_writes 46165163 # number of integer regfile writes
system.cpu0.fp_regfile_reads 17106 # number of floating regfile reads
system.cpu0.fp_regfile_writes 13230 # number of floating regfile writes
system.cpu0.cc_regfile_reads 262463332 # number of cc regfile reads
system.cpu0.cc_regfile_reads 262463335 # number of cc regfile reads
system.cpu0.cc_regfile_writes 27226302 # number of cc regfile writes
system.cpu0.misc_regfile_reads 143950426 # number of misc regfile reads
system.cpu0.misc_regfile_reads 143950430 # number of misc regfile reads
system.cpu0.misc_regfile_writes 725062 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 852281 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.984445 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 42339306 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 42339308 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 852793 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 49.647811 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 49.647814 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.071418 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.913027 # Average occupied blocks per requestor
@ -896,14 +896,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 189174347 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189174347 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 12233621 # number of ReadReq hits
system.cpu0.dcache.tags.tag_accesses 189174355 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189174355 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 12233622 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 12935174 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25168795 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 7652788 # number of WriteReq hits
system.cpu0.dcache.ReadReq_hits::total 25168796 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 7652789 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 8245651 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15898439 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15898440 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177697 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185293 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 362990 # number of SoftPFReq hits
@ -913,12 +913,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 446465
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216319 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243020 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459339 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 19886409 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu0.data 19886411 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 21180825 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41067234 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20064106 # number of overall hits
system.cpu0.dcache.demand_hits::total 41067236 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20064108 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21366118 # number of overall hits
system.cpu0.dcache.overall_hits::total 41430224 # number of overall hits
system.cpu0.dcache.overall_hits::total 41430226 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 399335 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 433156 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 832491 # number of ReadReq misses
@ -958,12 +958,12 @@ system.cpu0.dcache.demand_miss_latency::total 178403907084
system.cpu0.dcache.overall_miss_latency::cpu0.data 93671976214 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 84731930870 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 178403907084 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 12632956 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu0.data 12632957 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 13368330 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26001286 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9606512 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26001287 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9606513 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9991986 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19598498 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19598499 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257155 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 289787 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 546942 # number of SoftPFReq accesses(hits+misses)
@ -973,12 +973,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 474225
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216369 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243063 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459432 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 22239468 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu0.data 22239470 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 23360316 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 45599784 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 22496623 # number of overall (read+write) accesses
system.cpu0.dcache.demand_accesses::total 45599786 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 22496625 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 23650103 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 46146726 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 46146728 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031611 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032402 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.032017 # miss rate for ReadReq accesses

879
tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
View file

@ -0,0 +1,879 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.061235 # Number of seconds simulated
sim_ticks 61234797500 # Number of ticks simulated
final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 196562 # Simulator instruction rate (inst/s)
host_op_rate 197541 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 132848546 # Simulator tick rate (ticks/s)
host_mem_usage 399976 # Number of bytes of host memory used
host_seconds 460.94 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15573 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
system.physmem.perBankRdBursts::1 890 # Per bank write bursts
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
system.physmem.perBankRdBursts::3 1027 # Per bank write bursts
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
system.physmem.perBankRdBursts::6 1087 # Per bank write bursts
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
system.physmem.perBankRdBursts::10 938 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
system.physmem.perBankRdBursts::13 867 # Per bank write bursts
system.physmem.perBankRdBursts::14 876 # Per bank write bursts
system.physmem.perBankRdBursts::15 906 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61234703000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15573 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation
system.physmem.totQLat 72594750 # Total ticks spent queuing
system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14028 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 3932107.04 # Average gap between requests
system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.567381 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.499745 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states
system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20750031 # Number of BP lookups
system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 122469595 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.351719 # CPI: cycles per instruction
system.cpu.ipc 0.739799 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91054081 # Class of committed instruction
system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946097 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits
system.cpu.dcache.overall_hits::total 26254912 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses
system.cpu.dcache.overall_misses::total 989219 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks
system.cpu.dcache.writebacks::total 943278 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
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system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 27766889 # number of overall hits
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system.cpu.icache.overall_misses::total 801 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60228000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60228000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 60228000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60228000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60228000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27767690 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27767690 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 27767690 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27767690 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27767690 # number of overall (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::total 75191.011236 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
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system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_miss_latency::total 59427000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
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system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.453494 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
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system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
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system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits
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system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1029 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15573 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15573 # Request fanout histogram
system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.361598 # Number of seconds simulated
sim_ticks 361597758500 # Number of ticks simulated
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 779266 # Simulator instruction rate (inst/s)
host_op_rate 779298 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1155667536 # Simulator tick rate (ticks/s)
host_mem_usage 379236 # Number of bytes of host memory used
host_seconds 312.89 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 723195517 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29302884 # Number of branches fetched
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
system.cpu.dcache.tags.replacements 935475 # number of replacements
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
system.cpu.dcache.writebacks::total 935266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
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system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
system.cpu.icache.overall_misses::total 882 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 25 # number of writebacks
system.cpu.icache.writebacks::total 25 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
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system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
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system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15603 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15603 # Request fanout histogram
system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.366199 # Number of seconds simulated
sim_ticks 366199170500 # Number of ticks simulated
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 433838 # Simulator instruction rate (inst/s)
host_op_rate 763918 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1005585249 # Simulator tick rate (ticks/s)
host_mem_usage 405532 # Number of bytes of host memory used
host_seconds 364.17 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory
system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory
system.physmem.bytes_written::total 6528 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory
system.physmem.num_writes::total 102 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 732398341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278169482 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29309705 # Number of branches fetched
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
system.cpu.dcache.tags.replacements 2062733 # number of replacements
system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks
system.cpu.dcache.writebacks::total 2062482 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
system.cpu.icache.tags.replacements 24 # number of replacements
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits
system.cpu.icache.overall_hits::total 217695356 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 24 # number of writebacks
system.cpu.icache.writebacks::total 24 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 313 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits
system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses
system.cpu.l2cache.overall_misses::total 30044 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks
system.cpu.l2cache.writebacks::total 102 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 313 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1020 # Transaction distribution
system.membus.trans_dist::WritebackDirty 102 # Transaction distribution
system.membus.trans_dist::CleanEvict 14 # Transaction distribution
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 30160 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 30160 # Request fanout histogram
system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

803
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -0,0 +1,803 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.412080 # Number of seconds simulated
sim_ticks 412079966500 # Number of ticks simulated
final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 240872 # Simulator instruction rate (inst/s)
host_op_rate 240872 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 162212982 # Simulator tick rate (ticks/s)
host_mem_usage 251076 # Number of bytes of host memory used
host_seconds 2540.36 # Real time elapsed on the host
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory
system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 156608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 156608 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory
system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2447 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 377239 # Number of read requests responded to by this memory
system.physmem.num_reads::total 379686 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 380043 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 58588861 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 58968904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 380043 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 380043 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 45600004 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 45600004 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 45600004 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 380043 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 58588861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 104568908 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 379686 # Number of read requests accepted
system.physmem.writeReqs 293607 # Number of write requests accepted
system.physmem.readBursts 379686 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24278080 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 21824 # Total number of bytes read from write queue
system.physmem.bytesWritten 18789376 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24299904 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 341 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 23685 # Per bank write bursts
system.physmem.perBankRdBursts::1 23156 # Per bank write bursts
system.physmem.perBankRdBursts::2 23444 # Per bank write bursts
system.physmem.perBankRdBursts::3 24498 # Per bank write bursts
system.physmem.perBankRdBursts::4 25450 # Per bank write bursts
system.physmem.perBankRdBursts::5 23569 # Per bank write bursts
system.physmem.perBankRdBursts::6 23652 # Per bank write bursts
system.physmem.perBankRdBursts::7 23913 # Per bank write bursts
system.physmem.perBankRdBursts::8 23182 # Per bank write bursts
system.physmem.perBankRdBursts::9 23988 # Per bank write bursts
system.physmem.perBankRdBursts::10 24719 # Per bank write bursts
system.physmem.perBankRdBursts::11 22783 # Per bank write bursts
system.physmem.perBankRdBursts::12 23722 # Per bank write bursts
system.physmem.perBankRdBursts::13 24391 # Per bank write bursts
system.physmem.perBankRdBursts::14 22743 # Per bank write bursts
system.physmem.perBankRdBursts::15 22450 # Per bank write bursts
system.physmem.perBankWrBursts::0 17782 # Per bank write bursts
system.physmem.perBankWrBursts::1 17456 # Per bank write bursts
system.physmem.perBankWrBursts::2 17945 # Per bank write bursts
system.physmem.perBankWrBursts::3 18853 # Per bank write bursts
system.physmem.perBankWrBursts::4 19514 # Per bank write bursts
system.physmem.perBankWrBursts::5 18590 # Per bank write bursts
system.physmem.perBankWrBursts::6 18778 # Per bank write bursts
system.physmem.perBankWrBursts::7 18659 # Per bank write bursts
system.physmem.perBankWrBursts::8 18440 # Per bank write bursts
system.physmem.perBankWrBursts::9 18941 # Per bank write bursts
system.physmem.perBankWrBursts::10 19257 # Per bank write bursts
system.physmem.perBankWrBursts::11 18049 # Per bank write bursts
system.physmem.perBankWrBursts::12 18261 # Per bank write bursts
system.physmem.perBankWrBursts::13 18732 # Per bank write bursts
system.physmem.perBankWrBursts::14 17196 # Per bank write bursts
system.physmem.perBankWrBursts::15 17131 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 412079864500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 379686 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 293607 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 377956 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1374 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6977 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 7349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16982 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17515 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17450 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17545 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17504 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17405 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17352 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 142401 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 302.436977 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.883041 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 323.731419 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 50699 35.60% 35.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 38890 27.31% 62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13190 9.26% 72.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8518 5.98% 78.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5731 4.02% 82.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3813 2.68% 84.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2946 2.07% 86.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2544 1.79% 88.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16070 11.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 142401 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17327 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.892595 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 236.629202 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 17327 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17327 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.943729 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.871773 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 3.342990 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 17278 99.72% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 33 0.19% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 6 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 2 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 2 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 2 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 1 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::392-399 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17327 # Writes before turning the bus around for reads
system.physmem.totQLat 4062204500 # Total ticks spent queuing
system.physmem.totMemAccLat 11174923250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1896725000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10708.47 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29458.47 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 58.92 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 45.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 58.97 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 45.60 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.82 # Data bus utilization in percentage
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing
system.physmem.readRowHits 314203 # Number of row buffer hits during reads
system.physmem.writeRowHits 216323 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes
system.physmem.avgGap 612036.46 # Average gap between requests
system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 547933680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 298971750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1492662600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 956298960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 62025350850 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 192839650500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 285075897780 # Total energy per rank (pJ)
system.physmem_0.averagePower 691.797872 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 320257941500 # Time in different power states
system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 78061587250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 528617880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 288432375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1466212800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 946125360 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 58968919935 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 195520730250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 284634068040 # Total energy per rank (pJ)
system.physmem_1.averagePower 690.725678 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 324739070000 # Time in different power states
system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 123917421 # Number of BP lookups
system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 71578372 # Number of BTB lookups
system.cpu.branchPred.BTBHits 67267052 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 93.976784 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15041989 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1126026 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7056 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 4451 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2605 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 734 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 149344684 # DTB read hits
system.cpu.dtb.read_misses 549067 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 149893751 # DTB read accesses
system.cpu.dtb.write_hits 57319581 # DTB write hits
system.cpu.dtb.write_misses 63710 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 57383291 # DTB write accesses
system.cpu.dtb.data_hits 206664265 # DTB hits
system.cpu.dtb.data_misses 612777 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 207277042 # DTB accesses
system.cpu.itb.fetch_hits 226050668 # ITB hits
system.cpu.itb.fetch_misses 48 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 226050716 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
system.cpu.numCycles 824159933 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 611901617 # Number of instructions committed
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
system.cpu.discardedOps 12834895 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.346883 # CPI: cycles per instruction
system.cpu.ipc 0.742455 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction
system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction
system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::MemRead 146565535 23.95% 90.65% # Class of committed instruction
system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 611901617 # Class of committed instruction
system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked
system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 2535268 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2539364 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 79.772111 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1636792500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.644038 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997960 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997960 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 55666159 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 202570428 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 202570428 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 202570428 # number of overall hits
system.cpu.dcache.overall_hits::total 202570428 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1908498 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1908498 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1543875 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1543875 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3452373 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3452373 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3452373 # number of overall misses
system.cpu.dcache.overall_misses::total 3452373 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37718879500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 37718879500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 47736374000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 47736374000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 85455253500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 85455253500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 85455253500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 85455253500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 148812767 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 148812767 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 206022801 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 206022801 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 206022801 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 206022801 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19763.646333 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19763.646333 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30919.843899 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30919.843899 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24752.613203 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24752.613203 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 2339413 # number of writebacks
system.cpu.dcache.writebacks::total 2339413 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143957 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 143957 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769052 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 769052 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 913009 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 913009 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 913009 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 913009 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764541 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1764541 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774823 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 774823 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2539364 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2539364 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2539364 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2539364 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33202779000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33202779000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23350926000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 23350926000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56553705000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 56553705000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56553705000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 56553705000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18816.666204 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18816.666204 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30137.110024 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30137.110024 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
system.cpu.icache.tags.replacements 3158 # number of replacements
system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4986 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 45336.077417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1117.678366 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.545741 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.545741 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1828 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses
system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 226045682 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 226045682 # number of overall hits
system.cpu.icache.overall_hits::total 226045682 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4986 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4986 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4986 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4986 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4986 # number of overall misses
system.cpu.icache.overall_misses::total 4986 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 233628500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 233628500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 233628500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 233628500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 233628500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 233628500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 226050668 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 226050668 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 226050668 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 226050668 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 226050668 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 226050668 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46856.899318 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 46856.899318 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 46856.899318 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 46856.899318 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3158 # number of writebacks
system.cpu.icache.writebacks::total 3158 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4986 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4986 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4986 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4986 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4986 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4986 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228642500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 228642500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228642500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 228642500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228642500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 228642500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45856.899318 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45856.899318 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 347705 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380135 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.282526 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 189119343500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21322.016390 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.931124 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8022.029650 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.650696 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.244813 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.900420 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32430 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3158 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 571852 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 571852 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2539 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2539 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590273 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1590273 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2539 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2162125 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2164664 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2539 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2162125 # number of overall hits
system.cpu.l2cache.overall_hits::total 2164664 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 206308 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206308 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2447 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2447 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 170931 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 170931 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2447 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 377239 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 379686 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2447 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 377239 # number of overall misses
system.cpu.l2cache.overall_misses::total 379686 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16226611500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16226611500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194481500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 194481500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13777909500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13777909500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 194481500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 30004521000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30199002500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 194481500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 30004521000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30199002500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339413 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2339413 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3158 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3158 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 778160 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 778160 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4986 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 4986 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761204 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1761204 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4986 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2539364 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2544350 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4986 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2539364 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2544350 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265123 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265123 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.490774 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.490774 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097053 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097053 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490774 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.148556 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.149227 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490774 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.148556 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.149227 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78652.362002 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78652.362002 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79477.523498 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79477.523498 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80605.095038 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80605.095038 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79477.523498 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79537.166094 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79536.781709 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79477.523498 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79537.166094 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79536.781709 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 293607 # number of writebacks
system.cpu.l2cache.writebacks::total 293607 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206308 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206308 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2447 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2447 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170931 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170931 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2447 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 377239 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 379686 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2447 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 377239 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 379686 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14163531500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14163531500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170011500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170011500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12068599500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12068599500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170011500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26232131000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26402142500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170011500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26232131000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26402142500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265123 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265123 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490774 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097053 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097053 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.149227 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.149227 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68652.362002 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68652.362002 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69477.523498 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69477.523498 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70605.095038 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70605.095038 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5082776 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538426 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 249953 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4986 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761204 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13130 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613996 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7627126 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 521216 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241728 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312762944 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 347705 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2892055 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.028759 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2889661 99.92% 99.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2394 0.08% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2892055 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4883959000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7479000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.membus.trans_dist::ReadResp 173378 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution
system.membus.trans_dist::CleanEvict 51709 # Transaction distribution
system.membus.trans_dist::ReadExReq 206308 # Transaction distribution
system.membus.trans_dist::ReadExResp 206308 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 173378 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104688 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1104688 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43090752 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 725002 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 725002 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 725002 # Request fanout histogram
system.membus.reqLayer0.occupancy 2021006000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 2009290500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

921
tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
View file

@ -0,0 +1,921 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.362632 # Number of seconds simulated
sim_ticks 362631828500 # Number of ticks simulated
final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 177215 # Simulator instruction rate (inst/s)
host_op_rate 191948 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 126858592 # Simulator tick rate (ticks/s)
host_mem_usage 271160 # Number of bytes of host memory used
host_seconds 2858.55 # Real time elapsed on the host
sim_insts 506579366 # Number of instructions simulated
sim_ops 548692589 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory
system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory
system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory
system.physmem.num_reads::total 143930 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory
system.physmem.num_writes::total 97210 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 143930 # Number of read requests accepted
system.physmem.writeReqs 97210 # Number of write requests accepted
system.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
system.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9406 # Per bank write bursts
system.physmem.perBankRdBursts::1 8921 # Per bank write bursts
system.physmem.perBankRdBursts::2 8949 # Per bank write bursts
system.physmem.perBankRdBursts::3 8657 # Per bank write bursts
system.physmem.perBankRdBursts::4 9384 # Per bank write bursts
system.physmem.perBankRdBursts::5 9355 # Per bank write bursts
system.physmem.perBankRdBursts::6 8962 # Per bank write bursts
system.physmem.perBankRdBursts::7 8101 # Per bank write bursts
system.physmem.perBankRdBursts::8 8596 # Per bank write bursts
system.physmem.perBankRdBursts::9 8628 # Per bank write bursts
system.physmem.perBankRdBursts::10 8740 # Per bank write bursts
system.physmem.perBankRdBursts::11 9454 # Per bank write bursts
system.physmem.perBankRdBursts::12 9340 # Per bank write bursts
system.physmem.perBankRdBursts::13 9510 # Per bank write bursts
system.physmem.perBankRdBursts::14 8709 # Per bank write bursts
system.physmem.perBankRdBursts::15 9112 # Per bank write bursts
system.physmem.perBankWrBursts::0 6249 # Per bank write bursts
system.physmem.perBankWrBursts::1 6105 # Per bank write bursts
system.physmem.perBankWrBursts::2 6032 # Per bank write bursts
system.physmem.perBankWrBursts::3 5882 # Per bank write bursts
system.physmem.perBankWrBursts::4 6237 # Per bank write bursts
system.physmem.perBankWrBursts::5 6240 # Per bank write bursts
system.physmem.perBankWrBursts::6 6051 # Per bank write bursts
system.physmem.perBankWrBursts::7 5508 # Per bank write bursts
system.physmem.perBankWrBursts::8 5781 # Per bank write bursts
system.physmem.perBankWrBursts::9 5861 # Per bank write bursts
system.physmem.perBankWrBursts::10 5978 # Per bank write bursts
system.physmem.perBankWrBursts::11 6494 # Per bank write bursts
system.physmem.perBankWrBursts::12 6355 # Per bank write bursts
system.physmem.perBankWrBursts::13 6320 # Per bank write bursts
system.physmem.perBankWrBursts::14 6000 # Per bank write bursts
system.physmem.perBankWrBursts::15 6086 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 362631802500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 143930 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 97210 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads
system.physmem.totQLat 1538291500 # Total ticks spent queuing
system.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 719120000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing
system.physmem.readRowHits 110801 # Number of row buffer hits during reads
system.physmem.writeRowHits 64737 # Number of row buffer hits during writes
system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes
system.physmem.avgGap 1503822.69 # Average gap between requests
system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ)
system.physmem_0.averagePower 684.841129 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states
system.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ)
system.physmem_1.averagePower 684.623774 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states
system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 131880511 # Number of BP lookups
system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups
system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 725263657 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506579366 # Number of instructions committed
system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.431688 # CPI: cycles per instruction
system.cpu.ipc 0.698476 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction
system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 548692589 # Class of committed instruction
system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1141477 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits
system.cpu.dcache.overall_hits::total 168015632 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses
system.cpu.dcache.overall_misses::total 1557007 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks
system.cpu.dcache.writebacks::total 1069336 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
system.cpu.icache.tags.replacements 18130 # number of replacements
system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses
system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits
system.cpu.icache.overall_hits::total 198770599 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses
system.cpu.icache.overall_misses::total 20001 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 455038500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 18130 # number of writebacks
system.cpu.icache.writebacks::total 18130 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435037500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 112376 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.717181 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.116564 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1004433 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1021629 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 17196 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits
system.cpu.l2cache.overall_hits::total 1021629 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 100949 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40191 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2805 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 141140 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 143945 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2805 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses
system.cpu.l2cache.overall_misses::total 143945 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305085000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 223778500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11222625500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11446404000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 223778500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11222625500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069336 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356691 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 356691 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20001 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 20001 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788882 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 788882 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 20001 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1145573 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1165574 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 20001 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1145573 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1165574 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283015 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283015 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140243 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140243 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050947 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050947 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140243 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123205 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.123497 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123205 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.123497 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks
system.cpu.l2cache.writebacks::total 97210 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 112376 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 42981 # Transaction distribution
system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution
system.membus.trans_dist::CleanEvict 12558 # Transaction distribution
system.membus.trans_dist::ReadExReq 100949 # Transaction distribution
system.membus.trans_dist::ReadExResp 100949 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 253698 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 253698 # Request fanout histogram
system.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------

1238
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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243
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.279361 # Number of seconds simulated
sim_ticks 279360903000 # Number of ticks simulated
final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1080925 # Simulator instruction rate (inst/s)
host_op_rate 1170785 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 596093333 # Simulator tick rate (ticks/s)
host_mem_usage 259884 # Number of bytes of host memory used
host_seconds 468.65 # Real time elapsed on the host
sim_insts 506578818 # Number of instructions simulated
sim_ops 548692039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory
system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory
system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 558721807 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506578818 # Number of instructions committed
system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
system.cpu.num_int_insts 448447005 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 749023756 # number of times the integer registers were read
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
system.cpu.num_mem_refs 172743505 # number of memory refs
system.cpu.num_load_insts 115883283 # Number of load instructions
system.cpu.num_store_insts 56860222 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121552863 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548692589 # Class of executed instruction
system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
system.membus.trans_dist::WriteReq 54239049 # Transaction distribution
system.membus.trans_dist::WriteResp 54239049 # Transaction distribution
system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 687926230 # Request fanout histogram
system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram
system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 687926230 # Request fanout histogram
---------- End Simulation Statistics ----------

658
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -0,0 +1,658 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.708539 # Number of seconds simulated
sim_ticks 708539449500 # Number of ticks simulated
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 670051 # Simulator instruction rate (inst/s)
host_op_rate 725636 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 940143705 # Simulator tick rate (ticks/s)
host_mem_usage 269876 # Number of bytes of host memory used
host_seconds 753.65 # Real time elapsed on the host
sim_insts 504984064 # Number of instructions simulated
sim_ops 546875315 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 1417078899 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 504984064 # Number of instructions committed
system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
system.cpu.num_int_insts 448447005 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
system.cpu.num_mem_refs 172743505 # number of memory refs
system.cpu.num_load_insts 115883283 # Number of load instructions
system.cpu.num_store_insts 56860222 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121552863 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548692589 # Class of executed instruction
system.cpu.dcache.tags.replacements 1136276 # number of replacements
system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits
system.cpu.dcache.overall_hits::total 167200190 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses
system.cpu.dcache.overall_misses::total 1140372 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
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system.cpu.icache.overall_misses::total 11521 # number of overall misses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
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system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 250615 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 250615 # Request fanout histogram
system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

1053
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
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127
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.885773 # Number of seconds simulated
sim_ticks 885772926000 # Number of ticks simulated
final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 772132 # Simulator instruction rate (inst/s)
host_op_rate 1428832 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 827158459 # Simulator tick rate (ticks/s)
host_mem_usage 268696 # Number of bytes of host memory used
host_seconds 1070.86 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory
system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1771545853 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826847304 # Number of instructions committed
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
system.cpu.num_mem_refs 533241508 # number of memory refs
system.cpu.num_load_insts 384083313 # Number of load instructions
system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149981740 # Number of branches fetched
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1530082521 # Class of executed instruction
system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
system.membus.trans_dist::WriteResp 149158211 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram
system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
---------- End Simulation Statistics ----------

521
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
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@ -0,0 +1,521 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.650501 # Number of seconds simulated
sim_ticks 1650501252500 # Number of ticks simulated
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 482495 # Simulator instruction rate (inst/s)
host_op_rate 892859 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 963127288 # Simulator tick rate (ticks/s)
host_mem_usage 277668 # Number of bytes of host memory used
host_seconds 1713.69 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3301002505 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826847304 # Number of instructions committed
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
system.cpu.num_mem_refs 533241508 # number of memory refs
system.cpu.num_load_insts 384083313 # Number of load instructions
system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149981740 # Number of branches fetched
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1530082521 # Class of executed instruction
system.cpu.dcache.tags.replacements 2517016 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits
system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
system.cpu.dcache.writebacks::total 2325221 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.icache.tags.replacements 1253 # number of replacements
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits
system.cpu.icache.overall_hits::total 1068307822 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 348438 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits
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system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits
system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits
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system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
system.cpu.l2cache.writebacks::total 293208 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 727569 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

762
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -0,0 +1,762 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.223533 # Number of seconds simulated
sim_ticks 223532962500 # Number of ticks simulated
final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 234970 # Simulator instruction rate (inst/s)
host_op_rate 234970 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 131748654 # Simulator tick rate (ticks/s)
host_mem_usage 255168 # Number of bytes of host memory used
host_seconds 1696.66 # Real time elapsed on the host
sim_insts 398664665 # Number of instructions simulated
sim_ops 398664665 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1114323 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1138946 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2253269 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1114323 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1114323 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1114323 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1138946 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2253269 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7870 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 548 # Per bank write bursts
system.physmem.perBankRdBursts::1 675 # Per bank write bursts
system.physmem.perBankRdBursts::2 473 # Per bank write bursts
system.physmem.perBankRdBursts::3 633 # Per bank write bursts
system.physmem.perBankRdBursts::4 474 # Per bank write bursts
system.physmem.perBankRdBursts::5 477 # Per bank write bursts
system.physmem.perBankRdBursts::6 562 # Per bank write bursts
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
system.physmem.perBankRdBursts::8 471 # Per bank write bursts
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
system.physmem.perBankRdBursts::12 430 # Per bank write bursts
system.physmem.perBankRdBursts::13 556 # Per bank write bursts
system.physmem.perBankRdBursts::14 473 # Per bank write bursts
system.physmem.perBankRdBursts::15 424 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 223532875000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7870 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 325.149903 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 194.496255 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.966466 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 538 34.91% 34.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 340 22.06% 56.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 192 12.46% 69.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 106 6.88% 76.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 56 3.63% 79.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 49 3.18% 83.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 40 2.60% 85.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.34% 88.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 184 11.94% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation
system.physmem.totQLat 51693000 # Total ticks spent queuing
system.physmem.totMemAccLat 199255500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6568.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25318.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6320 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.30 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 28403160.74 # Average gap between requests
system.physmem.pageHitRate 80.30 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6751080 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3683625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 34125000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5792542920 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 129035577000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 149472420105 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.696853 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 214662823500 # Time in different power states
system.physmem_0.memoryStateTime::REF 7464080000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1403552000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 26933400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5529545775 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 129266276250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 149430056100 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.507329 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 215046035000 # Time in different power states
system.physmem_1.memoryStateTime::REF 7464080000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 45898041 # Number of BP lookups
system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 25194489 # Number of BTB lookups
system.cpu.branchPred.BTBHits 18810772 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 74.662249 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8282157 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 2248490 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2235007 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 13483 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 95357145 # DTB read hits
system.cpu.dtb.read_misses 114 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 95357259 # DTB read accesses
system.cpu.dtb.write_hits 73594596 # DTB write hits
system.cpu.dtb.write_misses 852 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73595448 # DTB write accesses
system.cpu.dtb.data_hits 168951741 # DTB hits
system.cpu.dtb.data_misses 966 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168952707 # DTB accesses
system.cpu.itb.fetch_hits 96790867 # ITB hits
system.cpu.itb.fetch_misses 1237 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 96792104 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 447065925 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664665 # Number of instructions committed
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2363843 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.121408 # CPI: cycles per instruction
system.cpu.ipc 0.891736 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
system.cpu.op_class_0::IntAlu 141652567 35.53% 41.33% # Class of committed instruction
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::MemRead 94754511 23.77% 81.56% # Class of committed instruction
system.cpu.op_class_0::MemWrite 73520765 18.44% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 398664665 # Class of committed instruction
system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 771 # number of replacements
system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40294.593037 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.617120 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.803617 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.803617 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 167826980 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167826980 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167826980 # number of overall hits
system.cpu.dcache.overall_hits::total 167826980 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 7114 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7114 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7114 # number of overall misses
system.cpu.dcache.overall_misses::total 7114 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88520000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88520000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 429316500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 429316500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 517836500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 517836500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 517836500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 517836500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94313364 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94313364 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 167834094 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167834094 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 167834094 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167834094 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72791.186393 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72791.186393 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
system.cpu.dcache.writebacks::total 654 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2949 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2949 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2949 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2949 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843244 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5168 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13526 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 22627 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 843328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9333 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 9333 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 9333 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10491000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7752000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 4733 # Transaction distribution
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7870 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7870 # Request fanout histogram
system.membus.reqLayer0.occupancy 9176500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 41781750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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---------- Begin Simulation Statistics ----------
sim_seconds 0.567385 # Number of seconds simulated
sim_ticks 567385356500 # Number of ticks simulated
final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 857568 # Simulator instruction rate (inst/s)
host_op_rate 857568 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1220503073 # Simulator tick rate (ticks/s)
host_mem_usage 253440 # Number of bytes of host memory used
host_seconds 464.88 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754490 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.write_hits 73520730 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520765 # DTB write accesses
system.cpu.dtb.data_hits 168275220 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275276 # DTB accesses
system.cpu.itb.fetch_hits 398664666 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664839 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 1134770713 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664609 # Number of instructions committed
system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365921 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275276 # number of memory refs
system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1134770713 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 44587535 # Number of branches fetched
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::MemRead 94754511 23.77% 81.56% # Class of executed instruction
system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664665 # Class of executed instruction
system.cpu.dcache.tags.replacements 764 # number of replacements
system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
system.cpu.icache.tags.replacements 1769 # number of replacements
system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
system.cpu.icache.overall_misses::total 3673 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1769 # number of writebacks
system.cpu.icache.writebacks::total 1769 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses
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system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7174 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7174 # Request fanout histogram
system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

882
tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
View file

@ -0,0 +1,882 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.211715 # Number of seconds simulated
sim_ticks 211714953000 # Number of ticks simulated
final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 119593 # Simulator instruction rate (inst/s)
host_op_rate 143584 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 92732901 # Simulator tick rate (ticks/s)
host_mem_usage 275300 # Number of bytes of host memory used
host_seconds 2283.06 # Real time elapsed on the host
sim_insts 273037857 # Number of instructions simulated
sim_ops 327812214 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1034750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1258447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2293197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1034750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1034750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1034750 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1258447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2293197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7586 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 630 # Per bank write bursts
system.physmem.perBankRdBursts::1 846 # Per bank write bursts
system.physmem.perBankRdBursts::2 628 # Per bank write bursts
system.physmem.perBankRdBursts::3 541 # Per bank write bursts
system.physmem.perBankRdBursts::4 466 # Per bank write bursts
system.physmem.perBankRdBursts::5 349 # Per bank write bursts
system.physmem.perBankRdBursts::6 171 # Per bank write bursts
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
system.physmem.perBankRdBursts::8 208 # Per bank write bursts
system.physmem.perBankRdBursts::9 310 # Per bank write bursts
system.physmem.perBankRdBursts::10 343 # Per bank write bursts
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
system.physmem.perBankRdBursts::12 553 # Per bank write bursts
system.physmem.perBankRdBursts::13 705 # Per bank write bursts
system.physmem.perBankRdBursts::14 638 # Per bank write bursts
system.physmem.perBankRdBursts::15 542 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 211714708500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7586 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1530 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 316.067974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 186.296863 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.878934 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 560 36.60% 36.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 363 23.73% 60.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 160 10.46% 70.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 74 4.84% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 70 4.58% 80.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 59 3.86% 84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 34 2.22% 86.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 28 1.83% 88.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 182 11.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1530 # Bytes accessed per row activation
system.physmem.totQLat 52630500 # Total ticks spent queuing
system.physmem.totMemAccLat 194868000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6937.85 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25687.85 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6048 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 27908609.08 # Average gap between requests
system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5080320 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2772000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5529396150 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 122174691000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 141569591070 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.700877 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 203247000500 # Time in different power states
system.physmem_0.memoryStateTime::REF 7069400000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1392729000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5726317185 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 122001953250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 141595000110 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.820896 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 202960400000 # Time in different power states
system.physmem_1.memoryStateTime::REF 7069400000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 32413931 # Number of BP lookups
system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17496692 # Number of BTB lookups
system.cpu.branchPred.BTBHits 12856502 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 73.479615 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6512761 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 2303892 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2264485 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 423429906 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037857 # Number of instructions committed
system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.550810 # CPI: cycles per instruction
system.cpu.ipc 0.644824 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction
system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction
system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 327812214 # Class of committed instruction
system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1355 # number of replacements
system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits
system.cpu.dcache.overall_hits::total 168633091 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses
system.cpu.dcache.overall_misses::total 7291 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
system.cpu.dcache.writebacks::total 1010 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles
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system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency
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system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id
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system.cpu.icache.ReadReq_miss_latency::total 757528000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 757528000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 757528000 # number of overall miss cycles
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
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system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id
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system.cpu.l2cache.WritebackClean_hits::total 23251 # number of WritebackClean hits
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system.cpu.l2cache.ReadCleanReq_hits::total 36680 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.170025 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170025 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 44617 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.339243 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.473458 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 29481 66.08% 66.08% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 15136 33.92% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 44617 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 81248000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 60156998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 4732 # Transaction distribution
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7586 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7586 # Request fanout histogram
system.membus.reqLayer0.occupancy 8883500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 40266000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.201717 # Number of seconds simulated
sim_ticks 201717314000 # Number of ticks simulated
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 686314 # Simulator instruction rate (inst/s)
host_op_rate 823996 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 507041348 # Simulator tick rate (ticks/s)
host_mem_usage 264028 # Number of bytes of host memory used
host_seconds 397.83 # Real time elapsed on the host
sim_insts 273037595 # Number of instructions simulated
sim_ops 327811950 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 403434629 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037595 # Number of instructions committed
system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls
system.cpu.num_int_insts 258331481 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
system.cpu.num_mem_refs 168107829 # number of memory refs
system.cpu.num_load_insts 85732235 # Number of load instructions
system.cpu.num_store_insts 82375594 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563491 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812145 # Class of executed instruction
system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram
system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
---------- End Simulation Statistics ----------

650
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
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@ -0,0 +1,650 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.517291 # Number of seconds simulated
sim_ticks 517291025500 # Number of ticks simulated
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 454164 # Simulator instruction rate (inst/s)
host_op_rate 545241 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 861389873 # Simulator tick rate (ticks/s)
host_mem_usage 274016 # Number of bytes of host memory used
host_seconds 600.53 # Real time elapsed on the host
sim_insts 272739286 # Number of instructions simulated
sim_ops 327433744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 272739286 # Number of instructions committed
system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
system.cpu.num_int_insts 258331537 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
system.cpu.num_mem_refs 168107847 # number of memory refs
system.cpu.num_load_insts 85732248 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563503 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812214 # Class of executed instruction
system.cpu.dcache.tags.replacements 1332 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
system.cpu.dcache.writebacks::total 998 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
system.cpu.icache.tags.replacements 13796 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
system.cpu.icache.overall_hits::total 348644750 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
system.cpu.icache.overall_misses::total 15603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
system.cpu.icache.writebacks::total 13796 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
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system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
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system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6833 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 6833 # Request fanout histogram
system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

800
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -0,0 +1,800 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.504258 # Number of seconds simulated
sim_ticks 504258263000 # Number of ticks simulated
final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 254365 # Simulator instruction rate (inst/s)
host_op_rate 254365 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 138099861 # Simulator tick rate (ticks/s)
host_mem_usage 257972 # Number of bytes of host memory used
host_seconds 3651.40 # Real time elapsed on the host
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory
system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory
system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 292267 # Number of read requests accepted
system.physmem.writeReqs 66683 # Number of write requests accepted
system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue
system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 18033 # Per bank write bursts
system.physmem.perBankRdBursts::1 18363 # Per bank write bursts
system.physmem.perBankRdBursts::2 18394 # Per bank write bursts
system.physmem.perBankRdBursts::3 18341 # Per bank write bursts
system.physmem.perBankRdBursts::4 18245 # Per bank write bursts
system.physmem.perBankRdBursts::5 18249 # Per bank write bursts
system.physmem.perBankRdBursts::6 18313 # Per bank write bursts
system.physmem.perBankRdBursts::7 18290 # Per bank write bursts
system.physmem.perBankRdBursts::8 18231 # Per bank write bursts
system.physmem.perBankRdBursts::9 18232 # Per bank write bursts
system.physmem.perBankRdBursts::10 18229 # Per bank write bursts
system.physmem.perBankRdBursts::11 18376 # Per bank write bursts
system.physmem.perBankRdBursts::12 18272 # Per bank write bursts
system.physmem.perBankRdBursts::13 18137 # Per bank write bursts
system.physmem.perBankRdBursts::14 18064 # Per bank write bursts
system.physmem.perBankRdBursts::15 18188 # Per bank write bursts
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
system.physmem.perBankWrBursts::9 4183 # Per bank write bursts
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 504258181000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 292267 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads
system.physmem.totQLat 3567632750 # Total ticks spent queuing
system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.36 # Data bus utilization in percentage
system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
system.physmem.readRowHits 203404 # Number of row buffer hits during reads
system.physmem.writeRowHits 52048 # Number of row buffer hits during writes
system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes
system.physmem.avgGap 1404814.55 # Average gap between requests
system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ)
system.physmem_0.averagePower 694.703966 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states
system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ)
system.physmem_1.averagePower 694.875219 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states
system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 123840342 # Number of BP lookups
system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups
system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 237538322 # DTB read hits
system.cpu.dtb.read_misses 198467 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 237736789 # DTB read accesses
system.cpu.dtb.write_hits 98305180 # DTB write hits
system.cpu.dtb.write_misses 7178 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 98312358 # DTB write accesses
system.cpu.dtb.data_hits 335843502 # DTB hits
system.cpu.dtb.data_misses 205645 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336049147 # DTB accesses
system.cpu.itb.fetch_hits 285763790 # ITB hits
system.cpu.itb.fetch_misses 119 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 285763909 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.numCycles 1008516526 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928789150 # Number of instructions committed
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.085840 # CPI: cycles per instruction
system.cpu.ipc 0.920946 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction
system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction
system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction
system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 928789150 # Class of committed instruction
system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked
system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 776530 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits
system.cpu.dcache.overall_hits::total 321596153 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses
system.cpu.dcache.overall_misses::total 849082 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks
system.cpu.dcache.writebacks::total 88489 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
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system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks.
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system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses
system.cpu.icache.overall_misses::total 12310 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles
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system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
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system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id
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system.cpu.l2cache.WritebackClean_hits::total 10567 # number of WritebackClean hits
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 259940 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1052876 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001976 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.044414 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1050795 99.80% 99.80% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2081 0.20% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 889072500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 225622 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
system.membus.trans_dist::CleanEvict 191176 # Transaction distribution
system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 550126 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 550126 # Request fanout histogram
system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

1055
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
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152
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.464395 # Number of seconds simulated
sim_ticks 464394627000 # Number of ticks simulated
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1449486 # Simulator instruction rate (inst/s)
host_op_rate 1449486 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 724900195 # Simulator tick rate (ticks/s)
host_mem_usage 247720 # Number of bytes of host memory used
host_seconds 640.63 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory
system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory
system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory
system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 237510597 # DTB read hits
system.cpu.dtb.read_misses 194650 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
system.cpu.dtb.write_hits 98301200 # DTB write hits
system.cpu.dtb.write_misses 6871 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
system.cpu.dtb.data_hits 335811797 # DTB hits
system.cpu.dtb.data_misses 201521 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336013318 # DTB accesses
system.cpu.itb.fetch_hits 928789150 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 928789255 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.numCycles 928789255 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928587629 # Number of instructions committed
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
system.cpu.num_int_insts 822136244 # number of integer instructions
system.cpu.num_fp_insts 33439365 # number of float instructions
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
system.cpu.num_mem_refs 336013318 # number of memory refs
system.cpu.num_load_insts 237705247 # Number of load instructions
system.cpu.num_store_insts 98308071 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 928789255 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 123111018 # Number of branches fetched
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 928789150 # Class of executed instruction
system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
system.membus.trans_dist::WriteReq 98301200 # Transaction distribution
system.membus.trans_dist::WriteResp 98301200 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram
system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1264600947 # Request fanout histogram
---------- End Simulation Statistics ----------

548
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
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@ -0,0 +1,548 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.288319 # Number of seconds simulated
sim_ticks 1288319411500 # Number of ticks simulated
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 888638 # Simulator instruction rate (inst/s)
host_op_rate 888638 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1232892743 # Simulator tick rate (ticks/s)
host_mem_usage 256432 # Number of bytes of host memory used
host_seconds 1044.96 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory
system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory
system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 237510597 # DTB read hits
system.cpu.dtb.read_misses 194650 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
system.cpu.dtb.write_hits 98301200 # DTB write hits
system.cpu.dtb.write_misses 6871 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
system.cpu.dtb.data_hits 335811797 # DTB hits
system.cpu.dtb.data_misses 201521 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336013318 # DTB accesses
system.cpu.itb.fetch_hits 928789151 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 928789256 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.numCycles 2576638823 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928587629 # Number of instructions committed
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
system.cpu.num_int_insts 822136244 # number of integer instructions
system.cpu.num_fp_insts 33439365 # number of float instructions
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
system.cpu.num_mem_refs 336013318 # number of memory refs
system.cpu.num_load_insts 237705247 # Number of load instructions
system.cpu.num_store_insts 98308071 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2576638823 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 123111018 # Number of branches fetched
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 928789150 # Class of executed instruction
system.cpu.dcache.tags.replacements 776432 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks
system.cpu.dcache.writebacks::total 88866 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
system.cpu.icache.tags.replacements 4618 # number of replacements
system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits
system.cpu.icache.overall_hits::total 928782983 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
system.cpu.icache.overall_misses::total 6168 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 4618 # number of writebacks
system.cpu.icache.writebacks::total 4618 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 258847 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits
system.cpu.l2cache.overall_hits::total 495307 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses
system.cpu.l2cache.overall_misses::total 291389 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 258847 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 224741 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
system.membus.trans_dist::CleanEvict 190447 # Transaction distribution
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 548519 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 548519 # Request fanout histogram
system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

906
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
View file

@ -0,0 +1,906 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.489946 # Number of seconds simulated
sim_ticks 489945697500 # Number of ticks simulated
final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 152136 # Simulator instruction rate (inst/s)
host_op_rate 187299 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 116346895 # Simulator tick rate (ticks/s)
host_mem_usage 275904 # Number of bytes of host memory used
host_seconds 4211.08 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory
system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 291212 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted
system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue
system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 18282 # Per bank write bursts
system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
system.physmem.perBankRdBursts::2 18217 # Per bank write bursts
system.physmem.perBankRdBursts::3 18178 # Per bank write bursts
system.physmem.perBankRdBursts::4 18288 # Per bank write bursts
system.physmem.perBankRdBursts::5 18411 # Per bank write bursts
system.physmem.perBankRdBursts::6 18177 # Per bank write bursts
system.physmem.perBankRdBursts::7 17990 # Per bank write bursts
system.physmem.perBankRdBursts::8 18028 # Per bank write bursts
system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
system.physmem.perBankRdBursts::10 18107 # Per bank write bursts
system.physmem.perBankRdBursts::11 18202 # Per bank write bursts
system.physmem.perBankRdBursts::12 18216 # Per bank write bursts
system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 489945603000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 291212 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads
system.physmem.totQLat 3297540750 # Total ticks spent queuing
system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.36 # Data bus utilization in percentage
system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing
system.physmem.readRowHits 195161 # Number of row buffer hits during reads
system.physmem.writeRowHits 51618 # Number of row buffer hits during writes
system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes
system.physmem.avgGap 1371205.96 # Average gap between requests
system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ)
system.physmem_0.averagePower 695.568361 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states
system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ)
system.physmem_1.averagePower 695.442012 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states
system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 144591747 # Number of BP lookups
system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups
system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 979891395 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640655085 # Number of instructions committed
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.529515 # CPI: cycles per instruction
system.cpu.ipc 0.653802 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction
system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 788730744 # Class of committed instruction
system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 778302 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits
system.cpu.dcache.overall_hits::total 378436756 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses
system.cpu.dcache.overall_misses::total 851693 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 379288449 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 379288449 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41451.468025 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks
system.cpu.dcache.writebacks::total 88712 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 69293 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 69293 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712937 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712937 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 782259 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 782259 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782398 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782398 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24459771500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24459771500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5070040000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5070040000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29529811500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29529811500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29531599500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29531599500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency
system.cpu.icache.tags.replacements 24859 # number of replacements
system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses
system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits
system.cpu.icache.overall_hits::total 252585994 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 26613 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 26613 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 26613 # number of overall misses
system.cpu.icache.overall_misses::total 26613 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 516729500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 516729500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 516729500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 516729500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 516729500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 516729500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 252612607 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 252612607 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 252612607 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 252612607 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 252612607 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 252612607 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19416.431819 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 24859 # number of writebacks
system.cpu.icache.writebacks::total 24859 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 490117500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 490117500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 490117500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 490117500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 490117500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 490117500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000105 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000105 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 258808 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.080339 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002698 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.910638 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.993675 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490486 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 490486 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 24049 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 493717 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 517766 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 24049 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 493717 # number of overall hits
system.cpu.l2cache.overall_hits::total 517766 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2564 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2564 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222590 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222590 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2564 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 288681 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 291245 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2564 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 288681 # number of overall misses
system.cpu.l2cache.overall_misses::total 291245 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4932129000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4932129000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 196405000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 196405000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18239788500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18239788500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 196405000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 23171917500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23368322500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 196405000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 23171917500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23368322500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88712 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88712 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 23528 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 23528 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26613 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 26613 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713076 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 713076 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 26613 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 782398 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 809011 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 26613 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 782398 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 809011 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096344 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096344 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312155 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312155 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096344 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368970 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.360001 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096344 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368970 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.360001 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 258808 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 225121 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190682 # Transaction distribution
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 547992 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 547992 # Request fanout histogram
system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
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@ -0,0 +1,243 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.395727 # Number of seconds simulated
sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 878754 # Simulator instruction rate (inst/s)
host_op_rate 1081862 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 542799023 # Simulator tick rate (ticks/s)
host_mem_usage 264636 # Number of bytes of host memory used
host_seconds 729.05 # Real time elapsed on the host
sim_insts 640654411 # Number of instructions simulated
sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 791453558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640654411 # Number of instructions committed
system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
system.cpu.num_int_insts 682251400 # number of integer instructions
system.cpu.num_fp_insts 24239771 # number of float instructions
system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364860 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram
system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
---------- End Simulation Statistics ----------

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@ -0,0 +1,659 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.045756 # Number of seconds simulated
sim_ticks 1045756396500 # Number of ticks simulated
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 554447 # Simulator instruction rate (inst/s)
host_op_rate 681172 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 906860836 # Simulator tick rate (ticks/s)
host_mem_usage 273604 # Number of bytes of host memory used
host_seconds 1153.16 # Real time elapsed on the host
sim_insts 639366787 # Number of instructions simulated
sim_ops 785501035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 2091512793 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 639366787 # Number of instructions committed
system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
system.cpu.num_int_insts 682251400 # number of integer instructions
system.cpu.num_fp_insts 24239771 # number of float instructions
system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364860 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
system.cpu.dcache.tags.replacements 778046 # number of replacements
system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits
system.cpu.dcache.overall_hits::total 378498833 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
system.cpu.dcache.writebacks::total 88995 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
system.cpu.icache.tags.replacements 8769 # number of replacements
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits
system.cpu.icache.overall_hits::total 643367692 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
system.cpu.icache.overall_misses::total 10208 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 8769 # number of writebacks
system.cpu.icache.writebacks::total 8769 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 257772 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
system.cpu.l2cache.overall_hits::total 501982 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 224275 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 546561 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 546561 # Request fanout histogram
system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

799
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -0,0 +1,799 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.059447 # Number of seconds simulated
sim_ticks 59447065000 # Number of ticks simulated
final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 249746 # Simulator instruction rate (inst/s)
host_op_rate 249746 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 167876675 # Simulator tick rate (ticks/s)
host_mem_usage 256840 # Number of bytes of host memory used
host_seconds 354.11 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory
system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 432832 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 432832 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7326016 # Number of bytes written to this memory
system.physmem.bytes_written::total 7326016 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6763 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158587 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165350 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114469 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114469 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7280965 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 170732870 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 178013835 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7280965 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7280965 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 123235958 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 123235958 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 123235958 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7280965 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 170732870 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 301249793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165350 # Number of read requests accepted
system.physmem.writeReqs 114469 # Number of write requests accepted
system.physmem.readBursts 165350 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 114469 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10581952 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
system.physmem.bytesWritten 7323968 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10582400 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7326016 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10315 # Per bank write bursts
system.physmem.perBankRdBursts::1 10360 # Per bank write bursts
system.physmem.perBankRdBursts::2 10206 # Per bank write bursts
system.physmem.perBankRdBursts::3 10057 # Per bank write bursts
system.physmem.perBankRdBursts::4 10348 # Per bank write bursts
system.physmem.perBankRdBursts::5 10343 # Per bank write bursts
system.physmem.perBankRdBursts::6 9775 # Per bank write bursts
system.physmem.perBankRdBursts::7 10207 # Per bank write bursts
system.physmem.perBankRdBursts::8 10536 # Per bank write bursts
system.physmem.perBankRdBursts::9 10606 # Per bank write bursts
system.physmem.perBankRdBursts::10 10500 # Per bank write bursts
system.physmem.perBankRdBursts::11 10228 # Per bank write bursts
system.physmem.perBankRdBursts::12 10273 # Per bank write bursts
system.physmem.perBankRdBursts::13 10559 # Per bank write bursts
system.physmem.perBankRdBursts::14 10465 # Per bank write bursts
system.physmem.perBankRdBursts::15 10565 # Per bank write bursts
system.physmem.perBankWrBursts::0 7163 # Per bank write bursts
system.physmem.perBankWrBursts::1 7274 # Per bank write bursts
system.physmem.perBankWrBursts::2 7296 # Per bank write bursts
system.physmem.perBankWrBursts::3 7002 # Per bank write bursts
system.physmem.perBankWrBursts::4 7127 # Per bank write bursts
system.physmem.perBankWrBursts::5 7186 # Per bank write bursts
system.physmem.perBankWrBursts::6 6833 # Per bank write bursts
system.physmem.perBankWrBursts::7 7099 # Per bank write bursts
system.physmem.perBankWrBursts::8 7226 # Per bank write bursts
system.physmem.perBankWrBursts::9 6999 # Per bank write bursts
system.physmem.perBankWrBursts::10 7117 # Per bank write bursts
system.physmem.perBankWrBursts::11 7034 # Per bank write bursts
system.physmem.perBankWrBursts::12 6992 # Per bank write bursts
system.physmem.perBankWrBursts::13 7299 # Per bank write bursts
system.physmem.perBankWrBursts::14 7307 # Per bank write bursts
system.physmem.perBankWrBursts::15 7483 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 59447041000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 165350 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 114469 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 163735 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1580 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 750 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7002 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7073 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7064 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7070 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7073 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7076 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 54692 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 327.365172 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 194.328231 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.549756 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 19615 35.86% 35.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11787 21.55% 57.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5586 10.21% 67.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3666 6.70% 74.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2860 5.23% 79.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2087 3.82% 83.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1603 2.93% 86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1458 2.67% 88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6030 11.03% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 54692 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.476853 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 336.379045 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7039 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.250639 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.234557 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.758479 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 6275 89.11% 89.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 11 0.16% 89.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 574 8.15% 97.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 150 2.13% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 18 0.26% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 9 0.13% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads
system.physmem.totQLat 1988923000 # Total ticks spent queuing
system.physmem.totMemAccLat 5089104250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 826715000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12029.07 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30779.07 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 178.01 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 123.20 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 178.01 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 123.24 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.35 # Data bus utilization in percentage
system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing
system.physmem.readRowHits 143858 # Number of row buffer hits during reads
system.physmem.writeRowHits 81218 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.01 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 70.95 # Row buffer hit rate for writes
system.physmem.avgGap 212448.19 # Average gap between requests
system.physmem.pageHitRate 80.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 199274040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 108730875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 636347400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 369068400 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 12411408285 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 24777095250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 42384271290 # Total energy per rank (pJ)
system.physmem_0.averagePower 713.053838 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 41070575000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1984840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 16385091250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 213940440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 116733375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 652860000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 372152880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 13085746785 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 24185582250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 42509362770 # Total energy per rank (pJ)
system.physmem_1.averagePower 715.158080 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 40083292000 # Time in different power states
system.physmem_1.memoryStateTime::REF 1984840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 14660042 # Number of BP lookups
system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9866507 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6346497 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 64.323646 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1708762 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 84355 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 37443 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 31778 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5665 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 7605 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20565775 # DTB read hits
system.cpu.dtb.read_misses 97355 # DTB read misses
system.cpu.dtb.read_acv 8 # DTB read access violations
system.cpu.dtb.read_accesses 20663130 # DTB read accesses
system.cpu.dtb.write_hits 14665271 # DTB write hits
system.cpu.dtb.write_misses 9409 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14674680 # DTB write accesses
system.cpu.dtb.data_hits 35231046 # DTB hits
system.cpu.dtb.data_misses 106764 # DTB misses
system.cpu.dtb.data_acv 8 # DTB access violations
system.cpu.dtb.data_accesses 35337810 # DTB accesses
system.cpu.itb.fetch_hits 25585531 # ITB hits
system.cpu.itb.fetch_misses 5208 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25590739 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 118894130 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1097381 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.344377 # CPI: cycles per instruction
system.cpu.ipc 0.743839 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction
system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction
system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 88438073 # Class of committed instruction
system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked
system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 200766 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 168.952954 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 687650500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.673886 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993817 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993817 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14333259 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34612040 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34612040 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34612040 # number of overall hits
system.cpu.dcache.overall_hits::total 34612040 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 89411 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 89411 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 280118 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 280118 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 369529 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 369529 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 369529 # number of overall misses
system.cpu.dcache.overall_misses::total 369529 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4770299000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4770299000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21700228000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21700228000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 26470527000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 26470527000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 26470527000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 26470527000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20368192 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20368192 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34981569 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34981569 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34981569 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34981569 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010564 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010564 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010564 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010564 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71633.151931 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 71633.151931 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 168424 # number of writebacks
system.cpu.dcache.writebacks::total 168424 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136555 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 136555 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143563 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143563 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204862 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2681247500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2681247500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10975422500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10975422500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13656670000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13656670000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13656670000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13656670000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43740.477006 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43740.477006 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76450.216978 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76450.216978 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
system.cpu.icache.tags.replacements 152872 # number of replacements
system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 154920 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 164.153176 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 42235793500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1932.382407 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.943546 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.943546 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1039 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses
system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25430610 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25430610 # number of overall hits
system.cpu.icache.overall_hits::total 25430610 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 154921 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 154921 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 154921 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 154921 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 154921 # number of overall misses
system.cpu.icache.overall_misses::total 154921 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2483739000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2483739000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2483739000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2483739000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2483739000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2483739000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25585531 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25585531 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25585531 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25585531 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25585531 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25585531 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006055 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.006055 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.006055 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.006055 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.006055 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.006055 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16032.293879 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16032.293879 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16032.293879 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16032.293879 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16032.293879 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16032.293879 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 152872 # number of writebacks
system.cpu.icache.writebacks::total 152872 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154921 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 154921 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 154921 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 154921 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 154921 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 154921 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2328819000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2328819000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2328819000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2328819000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2328819000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2328819000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006055 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006055 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006055 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15032.300334 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15032.300334 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 133382 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 165492 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.441175 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26350.763451 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2094.967777 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1983.317219 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.804161 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.063933 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.060526 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.928621 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32110 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11874 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18854 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 6016424 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 6016424 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 168424 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168424 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 152872 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 152872 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12681 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12681 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 148157 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 148157 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33594 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 33594 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 148157 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 46275 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 194432 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 148157 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 46275 # number of overall hits
system.cpu.l2cache.overall_hits::total 194432 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6764 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 6764 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27704 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 27704 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 6764 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158587 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 165351 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158587 # number of overall misses
system.cpu.l2cache.overall_misses::total 165351 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10626878000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10626878000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 540586000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 540586000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2236085500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2236085500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 540586000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12862963500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13403549500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 540586000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12862963500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13403549500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168424 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 168424 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 152872 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 152872 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143564 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143564 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 154921 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 154921 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61298 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 61298 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 154921 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204862 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 359783 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 154921 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204862 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 359783 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911670 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911670 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043661 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043661 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.451956 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.451956 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043661 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.774116 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.459585 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043661 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.774116 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.459585 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81193.722638 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81193.722638 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79921.052632 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79921.052632 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80713.452931 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80713.452931 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79921.052632 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81109.822999 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81061.194066 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79921.052632 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81109.822999 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81061.194066 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 114469 # number of writebacks
system.cpu.l2cache.writebacks::total 114469 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6764 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6764 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27704 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27704 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158587 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165351 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158587 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165351 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9318048000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9318048000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 472956000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 472956000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1959045500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1959045500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472956000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11277093500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11750049500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472956000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11277093500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11750049500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911670 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911670 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043661 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451956 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451956 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.459585 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.459585 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 713421 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 353638 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 51255 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143564 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143564 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 154921 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61298 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462713 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1073203 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19698688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 43588992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 133382 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 493165 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008186 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.090105 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 489128 99.18% 99.18% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 4037 0.82% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 493165 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 678006500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 232381497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 34467 # Transaction distribution
system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution
system.membus.trans_dist::CleanEvict 14990 # Transaction distribution
system.membus.trans_dist::ReadExReq 130883 # Transaction distribution
system.membus.trans_dist::ReadExResp 130883 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 34467 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460159 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 460159 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17908416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17908416 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 294809 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 294809 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 294809 # Request fanout histogram
system.membus.reqLayer0.occupancy 822950500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 872961750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

1057
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
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@ -0,0 +1,916 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.056803 # Number of seconds simulated
sim_ticks 56802974500 # Number of ticks simulated
final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 132517 # Simulator instruction rate (inst/s)
host_op_rate 169470 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 106146312 # Simulator tick rate (ticks/s)
host_mem_usage 275700 # Number of bytes of host memory used
host_seconds 535.14 # Real time elapsed on the host
sim_insts 70915150 # Number of instructions simulated
sim_ops 90690106 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory
system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory
system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory
system.physmem.num_reads::total 128284 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 86215 # Number of write requests responded to by this memory
system.physmem.num_writes::total 86215 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 5026216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 139511567 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 144537783 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5026216 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5026216 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 97138575 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 97138575 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 97138575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 5026216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 139511567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 241676358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128284 # Number of read requests accepted
system.physmem.writeReqs 86215 # Number of write requests accepted
system.physmem.readBursts 128284 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 86215 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 8209792 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
system.physmem.bytesWritten 5515904 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 8210176 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5517760 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 8062 # Per bank write bursts
system.physmem.perBankRdBursts::1 8315 # Per bank write bursts
system.physmem.perBankRdBursts::2 8233 # Per bank write bursts
system.physmem.perBankRdBursts::3 8142 # Per bank write bursts
system.physmem.perBankRdBursts::4 8284 # Per bank write bursts
system.physmem.perBankRdBursts::5 8403 # Per bank write bursts
system.physmem.perBankRdBursts::6 8055 # Per bank write bursts
system.physmem.perBankRdBursts::7 7916 # Per bank write bursts
system.physmem.perBankRdBursts::8 8035 # Per bank write bursts
system.physmem.perBankRdBursts::9 7587 # Per bank write bursts
system.physmem.perBankRdBursts::10 7763 # Per bank write bursts
system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
system.physmem.perBankRdBursts::12 7871 # Per bank write bursts
system.physmem.perBankRdBursts::13 7867 # Per bank write bursts
system.physmem.perBankRdBursts::14 7968 # Per bank write bursts
system.physmem.perBankRdBursts::15 7962 # Per bank write bursts
system.physmem.perBankWrBursts::0 5395 # Per bank write bursts
system.physmem.perBankWrBursts::1 5541 # Per bank write bursts
system.physmem.perBankWrBursts::2 5468 # Per bank write bursts
system.physmem.perBankWrBursts::3 5336 # Per bank write bursts
system.physmem.perBankWrBursts::4 5366 # Per bank write bursts
system.physmem.perBankWrBursts::5 5560 # Per bank write bursts
system.physmem.perBankWrBursts::6 5257 # Per bank write bursts
system.physmem.perBankWrBursts::7 5179 # Per bank write bursts
system.physmem.perBankWrBursts::8 5154 # Per bank write bursts
system.physmem.perBankWrBursts::9 5105 # Per bank write bursts
system.physmem.perBankWrBursts::10 5292 # Per bank write bursts
system.physmem.perBankWrBursts::11 5270 # Per bank write bursts
system.physmem.perBankWrBursts::12 5531 # Per bank write bursts
system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
system.physmem.perBankWrBursts::14 5703 # Per bank write bursts
system.physmem.perBankWrBursts::15 5432 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 56802942500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 128284 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 86215 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 116125 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 12132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 631 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 643 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5318 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5314 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5436 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5305 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 38880 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 352.990947 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 214.489872 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 335.589979 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12269 31.56% 31.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 8336 21.44% 53.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4191 10.78% 63.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2845 7.32% 71.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2490 6.40% 77.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1681 4.32% 81.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1302 3.35% 85.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1149 2.96% 88.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4617 11.88% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38880 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.227616 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 352.423208 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5291 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.279940 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.260845 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.856304 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 4659 88.01% 88.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 4 0.08% 88.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 483 9.12% 97.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 119 2.25% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 16 0.30% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 8 0.15% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
system.physmem.totQLat 1681541750 # Total ticks spent queuing
system.physmem.totMemAccLat 4086754250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 641390000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13108.57 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31858.57 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 144.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 97.11 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 144.54 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 97.14 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.89 # Data bus utilization in percentage
system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.24 # Average write queue length when enqueuing
system.physmem.readRowHits 111837 # Number of row buffer hits during reads
system.physmem.writeRowHits 63741 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.93 # Row buffer hit rate for writes
system.physmem.avgGap 264816.82 # Average gap between requests
system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 153127800 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 83551875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 510073200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 11545672905 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 23952789000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 40234383180 # Total energy per rank (pJ)
system.physmem_0.averagePower 708.339923 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 39720213500 # Time in different power states
system.physmem_0.memoryStateTime::REF 1896700000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15184054000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 140767200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 76807500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 279158400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 11005773750 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ)
system.physmem_1.averagePower 706.487303 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states
system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 14774616 # Number of BP lookups
system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 113605949 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915150 # Number of instructions committed
system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.601998 # CPI: cycles per instruction
system.cpu.ipc 0.624220 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 90690106 # Class of committed instruction
system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 156448 # number of replacements
system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits
system.cpu.dcache.overall_hits::total 42588476 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses
system.cpu.dcache.overall_misses::total 303974 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks
system.cpu.dcache.writebacks::total 128389 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
system.cpu.icache.tags.replacements 43497 # number of replacements
system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits
system.cpu.icache.overall_hits::total 24844377 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 45540 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 45540 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 45540 # number of overall misses
system.cpu.icache.overall_misses::total 45540 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 905103000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 905103000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 905103000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 905103000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 905103000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 905103000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24889917 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24889917 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24889917 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24889917 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24889917 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24889917 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001830 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001830 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001830 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001830 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001830 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001830 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19874.901186 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 43497 # number of writebacks
system.cpu.icache.writebacks::total 43497 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 859564000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 859564000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 859564000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 859564000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 859564000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 859564000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001830 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001830 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 96391 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1656.072920 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.817316 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043735 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.911590 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31907 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 31907 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 41065 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 77724 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 41065 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits
system.cpu.l2cache.overall_hits::total 77724 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4475 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 4475 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 4475 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 128360 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 4475 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses
system.cpu.l2cache.overall_misses::total 128360 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8279623500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8279623500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks
system.cpu.l2cache.writebacks::total 86215 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 96391 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 302475 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.037210 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.189781 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 291249 96.29% 96.29% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 11197 3.70% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
system.membus.trans_dist::ReadResp 26002 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution
system.membus.trans_dist::CleanEvict 6912 # Transaction distribution
system.membus.trans_dist::ReadExReq 102282 # Transaction distribution
system.membus.trans_dist::ReadExResp 102282 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13727936 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 221411 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 221411 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 221411 # Request fanout histogram
system.membus.reqLayer0.occupancy 590704500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 676958000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
---------- End Simulation Statistics ----------

1218
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
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@ -0,0 +1,807 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.208778 # Number of seconds simulated
sim_ticks 1208777694500 # Number of ticks simulated
final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 239767 # Simulator instruction rate (inst/s)
host_op_rate 239767 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 158688267 # Simulator tick rate (ticks/s)
host_mem_usage 248760 # Number of bytes of host memory used
host_seconds 7617.31 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory
system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65416896 # Number of bytes written to this memory
system.physmem.bytes_written::total 65416896 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1952658 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1953616 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1022139 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1022139 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 50722 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 103385521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 103436244 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 50722 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 50722 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54118219 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54118219 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54118219 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 50722 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 103385521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 157554463 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1953616 # Number of read requests accepted
system.physmem.writeReqs 1022139 # Number of write requests accepted
system.physmem.readBursts 1953616 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1022139 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 124948416 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 83008 # Total number of bytes read from write queue
system.physmem.bytesWritten 65415616 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 125031424 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 65416896 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1297 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 118316 # Per bank write bursts
system.physmem.perBankRdBursts::1 113525 # Per bank write bursts
system.physmem.perBankRdBursts::2 115740 # Per bank write bursts
system.physmem.perBankRdBursts::3 117258 # Per bank write bursts
system.physmem.perBankRdBursts::4 117310 # Per bank write bursts
system.physmem.perBankRdBursts::5 117126 # Per bank write bursts
system.physmem.perBankRdBursts::6 119402 # Per bank write bursts
system.physmem.perBankRdBursts::7 124113 # Per bank write bursts
system.physmem.perBankRdBursts::8 126650 # Per bank write bursts
system.physmem.perBankRdBursts::9 129582 # Per bank write bursts
system.physmem.perBankRdBursts::10 128169 # Per bank write bursts
system.physmem.perBankRdBursts::11 129917 # Per bank write bursts
system.physmem.perBankRdBursts::12 125580 # Per bank write bursts
system.physmem.perBankRdBursts::13 124837 # Per bank write bursts
system.physmem.perBankRdBursts::14 122150 # Per bank write bursts
system.physmem.perBankRdBursts::15 122644 # Per bank write bursts
system.physmem.perBankWrBursts::0 61421 # Per bank write bursts
system.physmem.perBankWrBursts::1 61661 # Per bank write bursts
system.physmem.perBankWrBursts::2 60724 # Per bank write bursts
system.physmem.perBankWrBursts::3 61398 # Per bank write bursts
system.physmem.perBankWrBursts::4 61819 # Per bank write bursts
system.physmem.perBankWrBursts::5 63309 # Per bank write bursts
system.physmem.perBankWrBursts::6 64356 # Per bank write bursts
system.physmem.perBankWrBursts::7 65855 # Per bank write bursts
system.physmem.perBankWrBursts::8 65577 # Per bank write bursts
system.physmem.perBankWrBursts::9 66031 # Per bank write bursts
system.physmem.perBankWrBursts::10 65643 # Per bank write bursts
system.physmem.perBankWrBursts::11 65945 # Per bank write bursts
system.physmem.perBankWrBursts::12 64508 # Per bank write bursts
system.physmem.perBankWrBursts::13 64526 # Per bank write bursts
system.physmem.perBankWrBursts::14 64900 # Per bank write bursts
system.physmem.perBankWrBursts::15 64446 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1208777578000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1953616 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1022139 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1830097 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 122205 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 32045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 55307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 59695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 60116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 60223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 60190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 60196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 60182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 60140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 60199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 60169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 60684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 61042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 60657 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 61101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 59617 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1831457 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 103.940817 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.136003 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 130.529919 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1452947 79.33% 79.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 261995 14.31% 93.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 48664 2.66% 96.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20593 1.12% 97.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13175 0.72% 98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7238 0.40% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5438 0.30% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 4580 0.25% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16827 0.92% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1831457 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 59614 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 32.747643 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 146.947369 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 59453 99.73% 99.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 9 0.02% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047 9 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 59614 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 59614 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.145620 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.109391 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.119268 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 27453 46.05% 46.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1268 2.13% 48.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 26337 44.18% 92.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 4007 6.72% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 455 0.76% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 71 0.12% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 59614 # Writes before turning the bus around for reads
system.physmem.totQLat 36537628750 # Total ticks spent queuing
system.physmem.totMemAccLat 73143610000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9761595000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18714.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 37464.99 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.23 # Data bus utilization in percentage
system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing
system.physmem.readRowHits 723773 # Number of row buffer hits during reads
system.physmem.writeRowHits 419204 # Number of row buffer hits during writes
system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes
system.physmem.avgGap 406208.70 # Average gap between requests
system.physmem.pageHitRate 38.43 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6714376200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3663598125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 7353738600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3243518640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 415074736440 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 361165338750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 876166703955 # Total energy per rank (pJ)
system.physmem_0.averagePower 724.837554 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 598070170000 # Time in different power states
system.physmem_0.memoryStateTime::REF 40363700000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 570342873000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 7131423600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3891153750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 7874224800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3379812480 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 426560774805 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 351089866500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 878878653135 # Total energy per rank (pJ)
system.physmem_1.averagePower 727.081103 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 581228871000 # Time in different power states
system.physmem_1.memoryStateTime::REF 40363700000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 246097965 # Number of BP lookups
system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 167640085 # Number of BTB lookups
system.cpu.branchPred.BTBHits 165196337 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.542265 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 18413332 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 104391 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 297 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 67 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 98 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 452860657 # DTB read hits
system.cpu.dtb.read_misses 4979867 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 457840524 # DTB read accesses
system.cpu.dtb.write_hits 161378231 # DTB write hits
system.cpu.dtb.write_misses 1709431 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 163087662 # DTB write accesses
system.cpu.dtb.data_hits 614238888 # DTB hits
system.cpu.dtb.data_misses 6689298 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 620928186 # DTB accesses
system.cpu.itb.fetch_hits 597989612 # ITB hits
system.cpu.itb.fetch_misses 19 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 597989631 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2417555389 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
system.cpu.discardedOps 51811935 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.323688 # CPI: cycles per instruction
system.cpu.ipc 0.755465 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction
system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1826378509 # Class of committed instruction
system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked
system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9121974 # number of replacements
system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9126070 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.914337 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726355 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 158481991 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 601538856 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 601538856 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 601538856 # number of overall hits
system.cpu.dcache.overall_hits::total 601538856 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7289538 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7289538 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2246511 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2246511 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9536049 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9536049 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9536049 # number of overall misses
system.cpu.dcache.overall_misses::total 9536049 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 185480529000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 108417025500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 293897554500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 293897554500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 293897554500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 293897554500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 450346403 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 450346403 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 611074905 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 611074905 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 611074905 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 611074905 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30819.635522 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30819.635522 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks
system.cpu.dcache.writebacks::total 3686603 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 50808 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359171 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 359171 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 409979 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 409979 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 409979 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 409979 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238730 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887340 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1887340 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9126070 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9126070 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9126070 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9126070 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83258719000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83258719000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260269787000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 260269787000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 624205.275574 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 750.173547 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.366296 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.366296 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 597988654 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 597988654 # number of overall hits
system.cpu.icache.overall_hits::total 597988654 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses
system.cpu.icache.overall_misses::total 958 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 76338000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 76338000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 76338000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 76338000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 76338000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 76338000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 597989612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 597989612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 597989612 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 597989612 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 597989612 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 597989612 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 79684.759916 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 79684.759916 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
system.cpu.icache.writebacks::total 3 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75380000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 75380000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75380000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 75380000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75380000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 75380000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 1920891 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1950696 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.386949 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 89219766000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.817395 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.451611 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001307 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.485965 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.938883 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1217 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12865 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106830 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1106830 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066582 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6066582 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7173412 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7173412 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7173412 # number of overall hits
system.cpu.l2cache.overall_hits::total 7173412 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 780510 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 780510 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 958 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 958 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1172148 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1172148 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1952658 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1953616 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1952658 # number of overall misses
system.cpu.l2cache.overall_misses::total 1953616 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68734828000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 68734828000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73941000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 73941000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 73941000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 171234996000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 73941000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 171234996000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3686603 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3686603 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887340 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1887340 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 958 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 958 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238730 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7238730 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 958 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9126070 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9127028 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 958 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9126070 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9127028 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413550 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413550 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161927 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161927 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.213965 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214047 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.213965 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214047 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks
system.cpu.l2cache.writebacks::total 1022139 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780510 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 780510 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 958 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 958 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172148 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172148 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1952658 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1953616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1952658 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1953616 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60929728000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60929728000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64361000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64361000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90704747000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90704747000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64361000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64361000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413550 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413550 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161927 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161927 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6334123 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1887340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1887340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238730 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374114 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27376033 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61504 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 820072576 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1920891 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 11047919 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11046651 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11047919 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12811108500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1173106 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution
system.membus.trans_dist::CleanEvict 897726 # Transaction distribution
system.membus.trans_dist::ReadExReq 780510 # Transaction distribution
system.membus.trans_dist::ReadExResp 780510 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1173106 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827097 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5827097 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190448320 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3873481 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3873481 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3873481 # Request fanout histogram
system.membus.reqLayer0.occupancy 8428417500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 10685410500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------

1095
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
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@ -0,0 +1,152 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.913189 # Number of seconds simulated
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1469307 # Simulator instruction rate (inst/s)
host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 737317476 # Simulator tick rate (ticks/s)
host_mem_usage 238516 # Number of bytes of host memory used
host_seconds 1238.53 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory
system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory
system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory
system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378509 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 214632552 # Number of branches fetched
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
system.membus.trans_dist::WriteReq 160728502 # Transaction distribution
system.membus.trans_dist::WriteResp 160728502 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram
system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2431702674 # Request fanout histogram
---------- End Simulation Statistics ----------

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View file

@ -0,0 +1,543 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.636720 # Number of seconds simulated
sim_ticks 2636719559500 # Number of ticks simulated
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 874013 # Simulator instruction rate (inst/s)
host_op_rate 874013 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1266376533 # Simulator tick rate (ticks/s)
host_mem_usage 247480 # Number of bytes of host memory used
host_seconds 2082.10 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory
system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory
system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 5273439119 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5273439119 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 214632552 # Number of branches fetched
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
system.cpu.dcache.tags.replacements 9107638 # number of replacements
system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
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system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1919525 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution
system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
system.membus.trans_dist::ReadExReq 782385 # Transaction distribution
system.membus.trans_dist::ReadExResp 782385 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3870887 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3870887 # Request fanout histogram
system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------

917
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
View file

@ -0,0 +1,917 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.116866 # Number of seconds simulated
sim_ticks 1116865668500 # Number of ticks simulated
final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 243832 # Simulator instruction rate (inst/s)
host_op_rate 262692 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 176313668 # Simulator tick rate (ticks/s)
host_mem_usage 266900 # Number of bytes of host memory used
host_seconds 6334.54 # Real time elapsed on the host
sim_insts 1544563088 # Number of instructions simulated
sim_ops 1664032481 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory
system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory
system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2046591 # Number of read requests accepted
system.physmem.writeReqs 1050123 # Number of write requests accepted
system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue
system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 127279 # Per bank write bursts
system.physmem.perBankRdBursts::1 124661 # Per bank write bursts
system.physmem.perBankRdBursts::2 121601 # Per bank write bursts
system.physmem.perBankRdBursts::3 123656 # Per bank write bursts
system.physmem.perBankRdBursts::4 122620 # Per bank write bursts
system.physmem.perBankRdBursts::5 122679 # Per bank write bursts
system.physmem.perBankRdBursts::6 123247 # Per bank write bursts
system.physmem.perBankRdBursts::7 123770 # Per bank write bursts
system.physmem.perBankRdBursts::8 131396 # Per bank write bursts
system.physmem.perBankRdBursts::9 133511 # Per bank write bursts
system.physmem.perBankRdBursts::10 132081 # Per bank write bursts
system.physmem.perBankRdBursts::11 133308 # Per bank write bursts
system.physmem.perBankRdBursts::12 133249 # Per bank write bursts
system.physmem.perBankRdBursts::13 133362 # Per bank write bursts
system.physmem.perBankRdBursts::14 129309 # Per bank write bursts
system.physmem.perBankRdBursts::15 129555 # Per bank write bursts
system.physmem.perBankWrBursts::0 66136 # Per bank write bursts
system.physmem.perBankWrBursts::1 64410 # Per bank write bursts
system.physmem.perBankWrBursts::2 62576 # Per bank write bursts
system.physmem.perBankWrBursts::3 63006 # Per bank write bursts
system.physmem.perBankWrBursts::4 63000 # Per bank write bursts
system.physmem.perBankWrBursts::5 63100 # Per bank write bursts
system.physmem.perBankWrBursts::6 64443 # Per bank write bursts
system.physmem.perBankWrBursts::7 65436 # Per bank write bursts
system.physmem.perBankWrBursts::8 67310 # Per bank write bursts
system.physmem.perBankWrBursts::9 67797 # Per bank write bursts
system.physmem.perBankWrBursts::10 67549 # Per bank write bursts
system.physmem.perBankWrBursts::11 67882 # Per bank write bursts
system.physmem.perBankWrBursts::12 67326 # Per bank write bursts
system.physmem.perBankWrBursts::13 67793 # Per bank write bursts
system.physmem.perBankWrBursts::14 66482 # Per bank write bursts
system.physmem.perBankWrBursts::15 65854 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1116865574000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 2046591 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1050123 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads
system.physmem.totQLat 38124700750 # Total ticks spent queuing
system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.39 # Data bus utilization in percentage
system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing
system.physmem.readRowHits 773341 # Number of row buffer hits during reads
system.physmem.writeRowHits 411895 # Number of row buffer hits during writes
system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes
system.physmem.avgGap 360661.52 # Average gap between requests
system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ)
system.physmem_0.averagePower 731.196952 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states
system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ)
system.physmem_1.averagePower 733.256935 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states
system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 239639355 # Number of BP lookups
system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups
system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 230 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 307 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 2233731337 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563088 # Number of instructions committed
system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.446190 # CPI: cycles per instruction
system.cpu.ipc 0.691472 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction
system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1664032481 # Class of committed instruction
system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked
system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9221041 # number of replacements
system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits
system.cpu.dcache.overall_hits::total 624218806 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses
system.cpu.dcache.overall_misses::total 9589474 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses
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system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency
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system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses
system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses
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system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits
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system.cpu.icache.overall_hits::total 465281510 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 819 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 2013919 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits
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system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits
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system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits
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system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits
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system.cpu.l2cache.overall_hits::cpu.data 7179324 # number of overall hits
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system.cpu.l2cache.ReadExReq_misses::total 801159 # number of ReadExReq misses
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system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadSharedReq_misses::total 1244654 # number of ReadSharedReq misses
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system.cpu.l2cache.overall_misses::cpu.data 2045813 # number of overall misses
system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 70441435500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadCleanReq_miss_latency::total 59945000 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500 # number of ReadSharedReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 179138607000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684567 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3684567 # number of WritebackDirty accesses(hits+misses)
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system.cpu.l2cache.WritebackClean_accesses::total 29 # number of WritebackClean accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.423702 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169704 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169704 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks
system.cpu.l2cache.writebacks::total 1050123 # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801159 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 801159 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62429845500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62429845500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52115000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52115000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96190393500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96190393500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52115000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52115000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 2013919 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1245432 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution
system.membus.trans_dist::CleanEvict 962724 # Transaction distribution
system.membus.trans_dist::ReadExReq 801159 # Transaction distribution
system.membus.trans_dist::ReadExResp 801159 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4059438 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4059438 # Request fanout histogram
system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.832017 # Number of seconds simulated
sim_ticks 832017490500 # Number of ticks simulated
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1043463 # Simulator instruction rate (inst/s)
host_op_rate 1124173 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 562087533 # Simulator tick rate (ticks/s)
host_mem_usage 256656 # Number of bytes of host memory used
host_seconds 1480.23 # Real time elapsed on the host
sim_insts 1544563042 # Number of instructions simulated
sim_ops 1664032434 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1664034982 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563042 # Number of instructions committed
system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462427 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032481 # Class of executed instruction
system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram
system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
---------- End Simulation Statistics ----------

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@ -0,0 +1,655 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.377030 # Number of seconds simulated
sim_ticks 2377029670500 # Number of ticks simulated
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 651336 # Simulator instruction rate (inst/s)
host_op_rate 701905 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1006163929 # Simulator tick rate (ticks/s)
host_mem_usage 265624 # Number of bytes of host memory used
host_seconds 2362.47 # Real time elapsed on the host
sim_insts 1538759602 # Number of instructions simulated
sim_ops 1658228915 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4754059341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759602 # Number of instructions committed
system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462427 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032481 # Class of executed instruction
system.cpu.dcache.tags.replacements 9111140 # number of replacements
system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
system.cpu.dcache.writebacks::total 3681379 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
system.cpu.icache.tags.replacements 7 # number of replacements
system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits
system.cpu.icache.overall_hits::total 1544564953 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
system.cpu.icache.overall_misses::total 638 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
system.cpu.icache.writebacks::total 7 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 1919027 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3869897 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3869897 # Request fanout histogram
system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------

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@ -0,0 +1,127 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 786137 # Simulator instruction rate (inst/s)
host_op_rate 1224873 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 743780816 # Simulator tick rate (ticks/s)
host_mem_usage 258352 # Number of bytes of host memory used
host_seconds 3826.41 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4684368009 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 248500691 # Number of branches fetched
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 4686862596 # Class of executed instruction
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram
system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
---------- End Simulation Statistics ----------

515
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -0,0 +1,515 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.895948 # Number of seconds simulated
sim_ticks 5895947852500 # Number of ticks simulated
final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 545612 # Simulator instruction rate (inst/s)
host_op_rate 850113 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1069419451 # Simulator tick rate (ticks/s)
host_mem_usage 268340 # Number of bytes of host memory used
host_seconds 5513.22 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11791895705 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4684368009 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 248500691 # Number of branches fetched
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 4686862596 # Class of executed instruction
system.cpu.dcache.tags.replacements 9108581 # number of replacements
system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
system.cpu.dcache.writebacks::total 3682716 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
system.cpu.icache.tags.replacements 10 # number of replacements
system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
system.cpu.icache.overall_misses::total 675 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 10 # number of writebacks
system.cpu.icache.writebacks::total 10 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 1919169 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3870249 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3870249 # Request fanout histogram
system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -0,0 +1,764 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.051906 # Number of seconds simulated
sim_ticks 51905634500 # Number of ticks simulated
final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 261291 # Simulator instruction rate (inst/s)
host_op_rate 261291 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 147573427 # Simulator tick rate (ticks/s)
host_mem_usage 252408 # Number of bytes of host memory used
host_seconds 351.73 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory
system.physmem.bytes_read::total 340480 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 3907399 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2652198 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6559596 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3907399 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3907399 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3907399 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2652198 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6559596 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5320 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 469 # Per bank write bursts
system.physmem.perBankRdBursts::1 295 # Per bank write bursts
system.physmem.perBankRdBursts::2 308 # Per bank write bursts
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
system.physmem.perBankRdBursts::4 224 # Per bank write bursts
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
system.physmem.perBankRdBursts::7 289 # Per bank write bursts
system.physmem.perBankRdBursts::8 252 # Per bank write bursts
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
system.physmem.perBankRdBursts::10 254 # Per bank write bursts
system.physmem.perBankRdBursts::11 261 # Per bank write bursts
system.physmem.perBankRdBursts::12 410 # Per bank write bursts
system.physmem.perBankRdBursts::13 344 # Per bank write bursts
system.physmem.perBankRdBursts::14 500 # Per bank write bursts
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 51905547000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 5320 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 346.395112 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 212.989816 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 328.326928 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 308 31.36% 31.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 213 21.69% 53.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 101 10.29% 63.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 90 9.16% 72.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 71 7.23% 79.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 37 3.77% 83.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 21 2.14% 85.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 29 2.95% 88.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 112 11.41% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation
system.physmem.totQLat 32661000 # Total ticks spent queuing
system.physmem.totMemAccLat 132411000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6139.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24889.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4334 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 9756681.77 # Average gap between requests
system.physmem.pageHitRate 81.47 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 19983600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1736098875 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29619147750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34770724710 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.912241 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49270880000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 899376250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3885840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2120250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 21309600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1812535875 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29552097750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34782010275 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.129676 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49159142250 # Time in different power states
system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 11440185 # Number of BP lookups
system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6076858 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5316207 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 87.482824 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1173724 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 26312 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 24255 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2057 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20416195 # DTB read hits
system.cpu.dtb.read_misses 43360 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20459555 # DTB read accesses
system.cpu.dtb.write_hits 6579893 # DTB write hits
system.cpu.dtb.write_misses 278 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6580171 # DTB write accesses
system.cpu.dtb.data_hits 26996088 # DTB hits
system.cpu.dtb.data_misses 43638 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 27039726 # DTB accesses
system.cpu.itb.fetch_hits 22951506 # ITB hits
system.cpu.itb.fetch_misses 90 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 22951596 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 103811269 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903089 # Number of instructions committed
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.129573 # CPI: cycles per instruction
system.cpu.ipc 0.885290 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction
system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91903089 # Class of committed instruction
system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked
system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits
system.cpu.dcache.overall_hits::total 26572424 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses
system.cpu.dcache.overall_misses::total 3429 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
system.cpu.icache.tags.replacements 13853 # number of replacements
system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits
system.cpu.icache.overall_hits::total 22935687 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses
system.cpu.icache.overall_misses::total 15819 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 13853 # number of writebacks
system.cpu.icache.writebacks::total 13853 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15819 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15819 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15819 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15819 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15819 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 391009000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 391009000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 391009000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 391009000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 391009000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 391009000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3667 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.259067 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780381 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.965355 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.965124 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064147 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.075675 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3667 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13853 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12649 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12649 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12649 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 12728 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12649 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 12728 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3169 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3169 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5320 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
system.cpu.l2cache.overall_misses::total 5320 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128506000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 128506000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234465500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 234465500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35663000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35663000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200341 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200341 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200341 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 18048 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 18048 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 18048 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 29989000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23727000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3601 # Transaction distribution
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 5320 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5320 # Request fanout histogram
system.membus.reqLayer0.occupancy 6419000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 28167750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.130383 # Number of seconds simulated
sim_ticks 130382890500 # Number of ticks simulated
final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 181123 # Simulator instruction rate (inst/s)
host_op_rate 190933 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 137045131 # Simulator tick rate (ticks/s)
host_mem_usage 270196 # Number of bytes of host memory used
host_seconds 951.39 # Real time elapsed on the host
sim_insts 172317810 # Number of instructions simulated
sim_ops 181650743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
system.physmem.bytes_read::total 247424 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3866 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 305 # Per bank write bursts
system.physmem.perBankRdBursts::1 217 # Per bank write bursts
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
system.physmem.perBankRdBursts::4 306 # Per bank write bursts
system.physmem.perBankRdBursts::5 305 # Per bank write bursts
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
system.physmem.perBankRdBursts::8 248 # Per bank write bursts
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
system.physmem.perBankRdBursts::11 200 # Per bank write bursts
system.physmem.perBankRdBursts::12 183 # Per bank write bursts
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
system.physmem.perBankRdBursts::15 204 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 130382796000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 3866 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation
system.physmem.totQLat 27071500 # Total ticks spent queuing
system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 2948 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33725503.36 # Average gap between requests
system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.831686 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states
system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.803682 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states
system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 49622074 # Number of BP lookups
system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups
system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 260765781 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317810 # Number of instructions committed
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.513284 # CPI: cycles per instruction
system.cpu.ipc 0.660815 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 181650743 # Class of committed instruction
system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements
system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits
system.cpu.dcache.overall_hits::total 40709659 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses
system.cpu.dcache.overall_misses::total 2441 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
system.cpu.icache.tags.replacements 2881 # number of replacements
system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits
system.cpu.icache.overall_hits::total 70779397 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses
system.cpu.icache.overall_misses::total 4678 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 2881 # number of writebacks
system.cpu.icache.writebacks::total 2881 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits
system.cpu.l2cache.overall_hits::total 2606 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
system.cpu.l2cache.overall_misses::total 3883 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 2775 # Transaction distribution
system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3866 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3866 # Request fanout histogram
system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
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tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
sim_ticks 2783854535000 # Number of ticks simulated
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1008697 # Simulator instruction rate (inst/s)
host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19668230366 # Simulator tick rate (ticks/s)
host_mem_usage 576064 # Number of bytes of host memory used
host_seconds 141.54 # Real time elapsed on the host
host_inst_rate 787133 # Simulator instruction rate (inst/s)
host_op_rate 958208 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15348024787 # Simulator tick rate (ticks/s)
host_mem_usage 576068 # Number of bytes of host memory used
host_seconds 181.38 # Real time elapsed on the host
sim_insts 142771651 # Number of instructions simulated
sim_ops 173801592 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 31525949 # DTB read hits
system.cpu.dtb.read_hits 31525950 # DTB read hits
system.cpu.dtb.read_misses 8580 # DTB read misses
system.cpu.dtb.write_hits 23124104 # DTB write hits
system.cpu.dtb.write_hits 23124105 # DTB write hits
system.cpu.dtb.write_misses 1448 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 31534529 # DTB read accesses
system.cpu.dtb.write_accesses 23125552 # DTB write accesses
system.cpu.dtb.read_accesses 31534530 # DTB read accesses
system.cpu.dtb.write_accesses 23125553 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 54650053 # DTB hits
system.cpu.dtb.hits 54650055 # DTB hits
system.cpu.dtb.misses 10028 # DTB misses
system.cpu.dtb.accesses 54660081 # DTB accesses
system.cpu.dtb.accesses 54660083 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu
system.cpu.num_int_insts 153161279 # number of integer instructions
system.cpu.num_fp_insts 11484 # number of float instructions
system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read
system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written
system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read
@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 177218432 # Class of executed instruction
system.cpu.dcache.tags.replacements 819392 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits
system.cpu.dcache.overall_hits::total 52863656 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits
system.cpu.dcache.overall_hits::total 52863658 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n
system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
system.cpu.dcache.overall_misses::total 814065 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses

64
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu
sim_ticks 2802882797500 # Number of ticks simulated
final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 797664 # Simulator instruction rate (inst/s)
host_op_rate 971941 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15227033289 # Simulator tick rate (ticks/s)
host_mem_usage 590380 # Number of bytes of host memory used
host_seconds 184.07 # Real time elapsed on the host
host_inst_rate 748827 # Simulator instruction rate (inst/s)
host_op_rate 912434 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14294755935 # Simulator tick rate (ticks/s)
host_mem_usage 590384 # Number of bytes of host memory used
host_seconds 196.08 # Real time elapsed on the host
sim_insts 146828219 # Number of instructions simulated
sim_ops 178907974 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -138,9 +138,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570
system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 20339693 # DTB read hits
system.cpu0.dtb.read_hits 20339694 # DTB read hits
system.cpu0.dtb.read_misses 6871 # DTB read misses
system.cpu0.dtb.write_hits 16391003 # DTB write hits
system.cpu0.dtb.write_hits 16391004 # DTB write hits
system.cpu0.dtb.write_misses 1093 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 20346564 # DTB read accesses
system.cpu0.dtb.write_accesses 16392096 # DTB write accesses
system.cpu0.dtb.read_accesses 20346565 # DTB read accesses
system.cpu0.dtb.write_accesses 16392097 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 36730696 # DTB hits
system.cpu0.dtb.hits 36730698 # DTB hits
system.cpu0.dtb.misses 7964 # DTB misses
system.cpu0.dtb.accesses 36738660 # DTB accesses
system.cpu0.dtb.accesses 36738662 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -239,7 +239,7 @@ system.cpu0.num_conditional_control_insts 13204192 # n
system.cpu0.num_int_insts 100762477 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read
system.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written
system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read
@ -289,9 +289,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu0.op_class::total 116881836 # Class of executed instruction
system.cpu0.dcache.tags.replacements 693478 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
@ -301,22 +301,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits
system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits
system.cpu0.dcache.overall_hits::total 35144934 # number of overall hits
system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits
system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses
@ -331,20 +331,20 @@ system.cpu0.dcache.demand_misses::cpu0.data 668899 #
system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses
system.cpu0.dcache.overall_misses::total 769220 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses

64
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
sim_ticks 2783854535000 # Number of ticks simulated
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 888036 # Simulator instruction rate (inst/s)
host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17315504636 # Simulator tick rate (ticks/s)
host_mem_usage 573724 # Number of bytes of host memory used
host_seconds 160.77 # Real time elapsed on the host
host_inst_rate 766060 # Simulator instruction rate (inst/s)
host_op_rate 932555 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14937129777 # Simulator tick rate (ticks/s)
host_mem_usage 573732 # Number of bytes of host memory used
host_seconds 186.37 # Real time elapsed on the host
sim_insts 142771651 # Number of instructions simulated
sim_ops 173801592 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 31525949 # DTB read hits
system.cpu.dtb.read_hits 31525950 # DTB read hits
system.cpu.dtb.read_misses 8580 # DTB read misses
system.cpu.dtb.write_hits 23124104 # DTB write hits
system.cpu.dtb.write_hits 23124105 # DTB write hits
system.cpu.dtb.write_misses 1448 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 31534529 # DTB read accesses
system.cpu.dtb.write_accesses 23125552 # DTB write accesses
system.cpu.dtb.read_accesses 31534530 # DTB read accesses
system.cpu.dtb.write_accesses 23125553 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 54650053 # DTB hits
system.cpu.dtb.hits 54650055 # DTB hits
system.cpu.dtb.misses 10028 # DTB misses
system.cpu.dtb.accesses 54660081 # DTB accesses
system.cpu.dtb.accesses 54660083 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu
system.cpu.num_int_insts 153161279 # number of integer instructions
system.cpu.num_fp_insts 11484 # number of float instructions
system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read
system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written
system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read
@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 177218432 # Class of executed instruction
system.cpu.dcache.tags.replacements 819392 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits
system.cpu.dcache.overall_hits::total 52863656 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits
system.cpu.dcache.overall_hits::total 52863658 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n
system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
system.cpu.dcache.overall_misses::total 814065 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses

284
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 2.869789 # Nu
sim_ticks 2869788970000 # Number of ticks simulated
final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 543935 # Simulator instruction rate (inst/s)
host_op_rate 657921 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11865725522 # Simulator tick rate (ticks/s)
host_mem_usage 611884 # Number of bytes of host memory used
host_seconds 241.86 # Real time elapsed on the host
sim_insts 131553572 # Number of instructions simulated
sim_ops 159121620 # Number of ops (including micro ops) simulated
host_inst_rate 480288 # Simulator instruction rate (inst/s)
host_op_rate 580935 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10477281069 # Simulator tick rate (ticks/s)
host_mem_usage 611892 # Number of bytes of host memory used
host_seconds 273.91 # Real time elapsed on the host
sim_insts 131553574 # Number of instructions simulated
sim_ops 159121622 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
@ -286,12 +286,12 @@ system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Wr
system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads
system.physmem.totQLat 4572923146 # Total ticks spent queuing
system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 4572903146 # Total ticks spent queuing
system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers
system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst
system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s
@ -313,28 +313,28 @@ system.physmem_0.preEnergy 190001625 # En
system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ)
system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.573415 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states
system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states
system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states
system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ)
system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.487743 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states
system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states
system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states
system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
@ -425,9 +425,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549
system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 25156507 # DTB read hits
system.cpu0.dtb.read_hits 25156508 # DTB read hits
system.cpu0.dtb.read_misses 6829 # DTB read misses
system.cpu0.dtb.write_hits 18749940 # DTB write hits
system.cpu0.dtb.write_hits 18749941 # DTB write hits
system.cpu0.dtb.write_misses 1114 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -438,12 +438,12 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 25163336 # DTB read accesses
system.cpu0.dtb.write_accesses 18751054 # DTB write accesses
system.cpu0.dtb.read_accesses 25163337 # DTB read accesses
system.cpu0.dtb.write_accesses 18751055 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 43906447 # DTB hits
system.cpu0.dtb.hits 43906449 # DTB hits
system.cpu0.dtb.misses 7943 # DTB misses
system.cpu0.dtb.accesses 43914390 # DTB accesses
system.cpu0.dtb.accesses 43914392 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -533,19 +533,19 @@ system.cpu0.numWorkItemsStarted 0 # nu
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed
system.cpu0.committedInsts 115352403 # Number of instructions committed
system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed
system.cpu0.committedInsts 115352405 # Number of instructions committed
system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses
system.cpu0.num_func_calls 12675179 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls
system.cpu0.num_int_insts 123360698 # number of integer instructions
system.cpu0.num_fp_insts 9756 # number of float instructions
system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read
system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written
system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read
system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read
system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written
system.cpu0.num_mem_refs 45042977 # number of memory refs
system.cpu0.num_load_insts 25408336 # Number of load instructions
@ -592,9 +592,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu0.op_class::total 143145074 # Class of executed instruction
system.cpu0.dcache.tags.replacements 692159 # number of replacements
system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy
@ -604,22 +604,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits
system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits
system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits
system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits
system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses
@ -634,8 +634,8 @@ system.cpu0.dcache.demand_misses::cpu0.data 721136 #
system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses
system.cpu0.dcache.overall_misses::total 848828 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles
@ -644,24 +644,24 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500
system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses
@ -676,8 +676,8 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914
system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency
@ -686,10 +686,10 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -726,8 +726,8 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles
@ -738,10 +738,10 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles
@ -760,8 +760,8 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency
@ -772,10 +772,10 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency
@ -977,18 +977,18 @@ system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000
system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses)
@ -1056,18 +1056,18 @@ system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1124,8 +1124,8 @@ system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles
@ -1136,19 +1136,19 @@ system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles
@ -1186,8 +1186,8 @@ system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency
@ -1198,19 +1198,19 @@ system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency
@ -2512,30 +2512,30 @@ system.l2c.ReadExReq_miss_latency::total 1749515500 # nu
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles
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system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles
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system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles
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system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles
system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses)
@ -2628,30 +2628,30 @@ system.l2c.ReadExReq_avg_miss_latency::total 90185.860096
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -2732,30 +2732,30 @@ system.l2c.ReadExReq_mshr_miss_latency::total 1555525500
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles
@ -2816,30 +2816,30 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency

190
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 2.909587 # Nu
sim_ticks 2909586837500 # Number of ticks simulated
final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 581636 # Simulator instruction rate (inst/s)
host_op_rate 701272 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15048595995 # Simulator tick rate (ticks/s)
host_mem_usage 573724 # Number of bytes of host memory used
host_seconds 193.35 # Real time elapsed on the host
sim_insts 112457033 # Number of instructions simulated
sim_ops 135588117 # Number of ops (including micro ops) simulated
host_inst_rate 495886 # Simulator instruction rate (inst/s)
host_op_rate 597884 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12830006266 # Simulator tick rate (ticks/s)
host_mem_usage 573732 # Number of bytes of host memory used
host_seconds 226.78 # Real time elapsed on the host
sim_insts 112457035 # Number of instructions simulated
sim_ops 135588119 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
@ -261,12 +261,12 @@ system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Wr
system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads
system.physmem.totQLat 1624802000 # Total ticks spent queuing
system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 1624800000 # Total ticks spent queuing
system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst
system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
@ -302,14 +302,14 @@ system.physmem_1.preEnergy 116362125 # En
system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ)
system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.477277 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states
system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states
system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states
system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
@ -389,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382
system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 24520655 # DTB read hits
system.cpu.dtb.read_hits 24520656 # DTB read hits
system.cpu.dtb.read_misses 8124 # DTB read misses
system.cpu.dtb.write_hits 19606816 # DTB write hits
system.cpu.dtb.write_hits 19606817 # DTB write hits
system.cpu.dtb.write_misses 1422 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@ -402,12 +402,12 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 24528779 # DTB read accesses
system.cpu.dtb.write_accesses 19608238 # DTB write accesses
system.cpu.dtb.read_accesses 24528780 # DTB read accesses
system.cpu.dtb.write_accesses 19608239 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 44127471 # DTB hits
system.cpu.dtb.hits 44127473 # DTB hits
system.cpu.dtb.misses 9546 # DTB misses
system.cpu.dtb.accesses 44137017 # DTB accesses
system.cpu.dtb.accesses 44137019 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -491,19 +491,19 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
system.cpu.committedInsts 112457033 # Number of instructions committed
system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed
system.cpu.committedInsts 112457035 # Number of instructions committed
system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
system.cpu.num_func_calls 9892146 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls
system.cpu.num_int_insts 119893391 # number of integer instructions
system.cpu.num_fp_insts 11161 # number of float instructions
system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read
system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written
system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read
system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read
system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read
system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written
system.cpu.num_mem_refs 45407924 # number of memory refs
system.cpu.num_load_insts 24843119 # Number of load instructions
@ -550,9 +550,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 138708215 # Class of executed instruction
system.cpu.dcache.tags.replacements 819223 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy
@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344
system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits
system.cpu.dcache.overall_hits::total 42329995 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits
system.cpu.dcache.overall_hits::total 42329997 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses
@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 25589348500
system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses
@ -760,12 +760,12 @@ system.cpu.icache.demand_misses::cpu.inst 1696239 # n
system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses
system.cpu.icache.overall_misses::total 1696239 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses
@ -778,12 +778,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.014679
system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -802,12 +802,12 @@ system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
@ -818,12 +818,12 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679
system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
@ -914,20 +914,20 @@ system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses)
@ -987,20 +987,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1049,20 +1049,20 @@ system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles
@ -1101,20 +1101,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency

64
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.783854 # Nu
sim_ticks 2783853866500 # Number of ticks simulated
final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 806647 # Simulator instruction rate (inst/s)
host_op_rate 981963 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15728650419 # Simulator tick rate (ticks/s)
host_mem_usage 576800 # Number of bytes of host memory used
host_seconds 176.99 # Real time elapsed on the host
host_inst_rate 760140 # Simulator instruction rate (inst/s)
host_op_rate 925348 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14821821018 # Simulator tick rate (ticks/s)
host_mem_usage 577060 # Number of bytes of host memory used
host_seconds 187.82 # Real time elapsed on the host
sim_insts 142770436 # Number of instructions simulated
sim_ops 173800089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -136,9 +136,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680
system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 15997245 # DTB read hits
system.cpu0.dtb.read_hits 15997246 # DTB read hits
system.cpu0.dtb.read_misses 4805 # DTB read misses
system.cpu0.dtb.write_hits 11281011 # DTB write hits
system.cpu0.dtb.write_hits 11281012 # DTB write hits
system.cpu0.dtb.write_misses 896 # DTB write misses
system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
@ -149,12 +149,12 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 16002050 # DTB read accesses
system.cpu0.dtb.write_accesses 11281907 # DTB write accesses
system.cpu0.dtb.read_accesses 16002051 # DTB read accesses
system.cpu0.dtb.write_accesses 11281908 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 27278256 # DTB hits
system.cpu0.dtb.hits 27278258 # DTB hits
system.cpu0.dtb.misses 5701 # DTB misses
system.cpu0.dtb.accesses 27283957 # DTB accesses
system.cpu0.dtb.accesses 27283959 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -237,7 +237,7 @@ system.cpu0.num_conditional_control_insts 9459738 # n
system.cpu0.num_int_insts 77491639 # number of integer instructions
system.cpu0.num_fp_insts 5273 # number of float instructions
system.cpu0.num_int_register_reads 144069521 # number of times the integer registers were read
system.cpu0.num_int_register_writes 54447635 # number of times the integer registers were written
system.cpu0.num_int_register_writes 54447639 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 268878195 # number of times the CC registers were read
@ -287,9 +287,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu0.op_class::total 89752341 # Class of executed instruction
system.cpu0.dcache.tags.replacements 819388 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 53783376 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 53783378 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 819900 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 65.597483 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 65.597485 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830508 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166666 # Average occupied blocks per requestor
@ -301,14 +301,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 219233084 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 219233084 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15305417 # number of ReadReq hits
system.cpu0.dcache.tags.tag_accesses 219233092 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 219233092 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15305418 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 30128492 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 10893994 # number of WriteReq hits
system.cpu0.dcache.ReadReq_hits::total 30128493 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 10893995 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 11445651 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 22339645 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 22339646 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185752 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209291 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 395043 # number of SoftPFReq hits
@ -318,12 +318,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 457316
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236694 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223428 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 26199411 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu0.data 26199413 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 26268726 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 52468137 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 26385163 # number of overall hits
system.cpu0.dcache.demand_hits::total 52468139 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 26385165 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 26478017 # number of overall hits
system.cpu0.dcache.overall_hits::total 52863180 # number of overall hits
system.cpu0.dcache.overall_hits::total 52863182 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 197452 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 198861 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 396313 # number of ReadReq misses
@ -344,12 +344,12 @@ system.cpu0.dcache.demand_misses::total 697978 # nu
system.cpu0.dcache.overall_misses::cpu0.data 389311 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 424732 # number of overall misses
system.cpu0.dcache.overall_misses::total 814043 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502869 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502870 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021936 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 30524805 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031501 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 30524806 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031502 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609809 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 22641310 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 22641311 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 511108 # number of SoftPFReq accesses(hits+misses)
@ -359,12 +359,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 465945
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236694 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223430 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 26534370 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu0.data 26534372 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 26631745 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 53166115 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 26774474 # number of overall (read+write) accesses
system.cpu0.dcache.demand_accesses::total 53166117 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 26774476 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 26902749 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 53677223 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 53677225 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses

180
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 2.903880 # Nu
sim_ticks 2903879904500 # Number of ticks simulated
final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 558564 # Simulator instruction rate (inst/s)
host_op_rate 673462 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14421337908 # Simulator tick rate (ticks/s)
host_mem_usage 577056 # Number of bytes of host memory used
host_seconds 201.36 # Real time elapsed on the host
sim_insts 112472356 # Number of instructions simulated
sim_ops 135608165 # Number of ops (including micro ops) simulated
host_inst_rate 505304 # Simulator instruction rate (inst/s)
host_op_rate 609246 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 13046252349 # Simulator tick rate (ticks/s)
host_mem_usage 577060 # Number of bytes of host memory used
host_seconds 222.58 # Real time elapsed on the host
sim_insts 112472358 # Number of instructions simulated
sim_ops 135608167 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
@ -291,12 +291,12 @@ system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Wr
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5814 # Writes before turning the bus around for reads
system.physmem.totQLat 1475229250 # Total ticks spent queuing
system.physmem.totMemAccLat 4623710500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 1475227250 # Total ticks spent queuing
system.physmem.totMemAccLat 4623708500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 839595000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8785.36 # Average queueing delay per DRAM burst
system.physmem.avgQLat 8785.35 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27535.36 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 27535.35 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
@ -584,9 +584,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu0.op_class::total 68839780 # Class of executed instruction
system.cpu0.dcache.tags.replacements 819212 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.827217 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 43241766 # Total number of references to valid blocks.
system.cpu0.dcache.tags.total_refs 43241768 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 819724 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 52.751616 # Average number of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 52.751619 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.161528 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.665688 # Average occupied blocks per requestor
@ -599,14 +599,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 177132709 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 177132709 # Number of data accesses
system.cpu0.dcache.tags.tag_accesses 177132717 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 177132717 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11490299 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 11626239 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23116538 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 11626240 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23116539 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 9270780 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 9555063 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18825843 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 9555064 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18825844 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200211 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192673 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 392884 # number of SoftPFReq hits
@ -617,11 +617,11 @@ system.cpu0.dcache.StoreCondReq_hits::cpu0.data 232922
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227346 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20761079 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 21181302 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41942381 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 21181304 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41942383 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20961290 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21373975 # number of overall hits
system.cpu0.dcache.overall_hits::total 42335265 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21373977 # number of overall hits
system.cpu0.dcache.overall_hits::total 42335267 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 199689 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 200118 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 399807 # number of ReadReq misses
@ -660,11 +660,11 @@ system.cpu0.dcache.overall_miss_latency::cpu0.data 8732466000
system.cpu0.dcache.overall_miss_latency::cpu1.data 9861594500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 18594060500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11689988 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826357 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 23516345 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826358 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 23516346 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9413501 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710991 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19124492 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710992 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19124493 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257183 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253897 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 511080 # number of SoftPFReq accesses(hits+misses)
@ -675,11 +675,11 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 232924
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227346 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 21103489 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 21537348 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42640837 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 21537350 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42640839 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 21360672 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 21791245 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43151917 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 21791247 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43151919 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017082 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016921 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.017001 # miss rate for ReadReq accesses
@ -878,14 +878,14 @@ system.cpu0.icache.overall_misses::cpu0.inst 854412
system.cpu0.icache.overall_misses::cpu1.inst 844092 # number of overall misses
system.cpu0.icache.overall_misses::total 1698504 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11714597500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693316500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 23407914000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693314500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 23407912000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11714597500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 11693316500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 23407914000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 11693314500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 23407912000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11714597500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 11693316500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 23407914000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 11693314500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 23407912000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57466570 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 58103866 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 115570436 # number of ReadReq accesses(hits+misses)
@ -905,14 +905,14 @@ system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014868
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014527 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13710.712747 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.130346 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.488887 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.127977 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.487709 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13781.488887 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.127977 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13781.487709 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13781.488887 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.127977 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13781.487709 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -935,14 +935,14 @@ system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10860185500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849224500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709410000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849222500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709408000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10860185500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849224500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 21709410000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849222500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 21709408000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10860185500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849224500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 21709410000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849222500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 21709408000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles
@ -957,14 +957,14 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014868
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.488887 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.487709 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.487709 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.487709 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency
@ -1034,9 +1034,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5422
system.cpu1.dtb.walker.walkRequestOrigin::total 11977 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 12327133 # DTB read hits
system.cpu1.dtb.read_hits 12327134 # DTB read hits
system.cpu1.dtb.read_misses 5631 # DTB read misses
system.cpu1.dtb.write_hits 9951025 # DTB write hits
system.cpu1.dtb.write_hits 9951026 # DTB write hits
system.cpu1.dtb.write_misses 924 # DTB write misses
system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA
@ -1047,12 +1047,12 @@ system.cpu1.dtb.align_faults 0 # Nu
system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 12332764 # DTB read accesses
system.cpu1.dtb.write_accesses 9951949 # DTB write accesses
system.cpu1.dtb.read_accesses 12332765 # DTB read accesses
system.cpu1.dtb.write_accesses 9951950 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 22278158 # DTB hits
system.cpu1.dtb.hits 22278160 # DTB hits
system.cpu1.dtb.misses 6555 # DTB misses
system.cpu1.dtb.accesses 22284713 # DTB accesses
system.cpu1.dtb.accesses 22284715 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@ -1138,19 +1138,19 @@ system.cpu1.numWorkItemsStarted 0 # nu
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.committedInsts 56542374 # Number of instructions committed
system.cpu1.committedOps 68331078 # Number of ops (including micro ops) committed
system.cpu1.committedInsts 56542376 # Number of instructions committed
system.cpu1.committedOps 68331080 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 60434186 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5384 # Number of float alu accesses
system.cpu1.num_func_calls 4958421 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 7671718 # number of instructions that are conditional controls
system.cpu1.num_int_insts 60434186 # number of integer instructions
system.cpu1.num_fp_insts 5384 # number of float instructions
system.cpu1.num_int_register_reads 109968089 # number of times the integer registers were read
system.cpu1.num_int_register_writes 41558580 # number of times the integer registers were written
system.cpu1.num_int_register_reads 109968090 # number of times the integer registers were read
system.cpu1.num_int_register_writes 41558584 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3965 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1422 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 246670954 # number of times the CC registers were read
system.cpu1.num_cc_register_reads 246670957 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26165253 # number of times the CC registers were written
system.cpu1.num_mem_refs 22910809 # number of memory refs
system.cpu1.num_load_insts 12487681 # Number of load instructions
@ -1510,8 +1510,8 @@ system.l2c.ReadExReq_miss_latency::cpu0.data 4487898000
system.l2c.ReadExReq_miss_latency::cpu1.data 5568339500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10056237500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 663327500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794140000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 1457467500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794138000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 1457465500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 478260000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 540016500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 1018276500 # number of ReadSharedReq miss cycles
@ -1521,18 +1521,18 @@ system.l2c.demand_miss_latency::cpu0.inst 663327500 # n
system.l2c.demand_miss_latency::cpu0.data 4966158000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 447000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 794140000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 794138000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 6108356000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 12532847000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 12532845000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 663327500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 4966158000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 447000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 794140000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 794138000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 6108356000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 12532847000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 12532845000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 6059 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3328 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5254 # number of ReadReq accesses(hits+misses)
@ -1625,8 +1625,8 @@ system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77402.907849
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76857.688061 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77100.056735 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81479.855055 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.884373 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81046.961019 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.681162 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81046.849803 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84933.404369 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83671.599008 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 84259.536616 # average ReadSharedReq miss latency
@ -1636,18 +1636,18 @@ system.l2c.demand_avg_miss_latency::cpu0.inst 81479.855055
system.l2c.demand_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80688.681162 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 78081.895719 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 78081.883259 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 81479.855055 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80688.681162 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 78081.895719 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 78081.883259 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1718,8 +1718,8 @@ system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3908088000
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4843839500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8751927500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 581917500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695720000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 1277637500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695718000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 1277635500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421950000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 475476500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 897426500 # number of ReadSharedReq MSHR miss cycles
@ -1729,18 +1729,18 @@ system.l2c.demand_mshr_miss_latency::cpu0.inst 581917500
system.l2c.demand_mshr_miss_latency::cpu0.data 4330038000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 397000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 695720000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 695718000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 5319316000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 10927757000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 10927755000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 581917500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4330038000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 397000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 695720000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 695718000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 5319316000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 10927757000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 10927755000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2654142000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3237757500 # number of ReadReq MSHR uncacheable cycles
@ -1800,8 +1800,8 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67402.907849
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66857.688061 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67100.056735 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.961019 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.849803 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74933.404369 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73671.599008 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74259.536616 # average ReadSharedReq mshr miss latency
@ -1811,18 +1811,18 @@ system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71479.855055
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 68081.883259 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 68081.883259 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184008.735441 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193715.298552 # average ReadReq mshr uncacheable latency

12
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
sim_ticks 17232500 # Number of ticks simulated
final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66942 # Simulator instruction rate (inst/s)
host_op_rate 78386 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 251130115 # Simulator tick rate (ticks/s)
host_mem_usage 265932 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_inst_rate 37479 # Simulator instruction rate (inst/s)
host_op_rate 43886 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 140595410 # Simulator tick rate (ticks/s)
host_mem_usage 265936 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -791,7 +791,7 @@ system.cpu.int_regfile_writes 4270 # nu
system.cpu.fp_regfile_reads 32 # number of floating regfile reads
system.cpu.cc_regfile_reads 27801 # number of cc regfile reads
system.cpu.cc_regfile_writes 3276 # number of cc regfile writes
system.cpu.misc_regfile_reads 3018 # number of misc regfile reads
system.cpu.misc_regfile_reads 3010 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use

12
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
sim_ticks 18821000 # Number of ticks simulated
final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 45352 # Simulator instruction rate (inst/s)
host_op_rate 53108 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 185838458 # Simulator tick rate (ticks/s)
host_mem_usage 261708 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 22479 # Simulator instruction rate (inst/s)
host_op_rate 26323 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 92110547 # Simulator tick rate (ticks/s)
host_mem_usage 261716 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -672,7 +672,7 @@ system.cpu.int_regfile_writes 3787 # nu
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.cc_regfile_reads 24229 # number of cc regfile reads
system.cpu.cc_regfile_writes 2921 # number of cc regfile writes
system.cpu.misc_regfile_reads 2586 # number of misc regfile reads
system.cpu.misc_regfile_reads 2578 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.dcache.tags.replacements 1 # number of replacements
system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use

947
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View file

@ -0,0 +1,947 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000029 # Number of seconds simulated
sim_ticks 28845500 # Number of ticks simulated
final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50478 # Simulator instruction rate (inst/s)
host_op_rate 50473 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 100846842 # Simulator tick rate (ticks/s)
host_mem_usage 247864 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 510 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 511 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 105 # Per bank write bursts
system.physmem.perBankRdBursts::1 28 # Per bank write bursts
system.physmem.perBankRdBursts::2 53 # Per bank write bursts
system.physmem.perBankRdBursts::3 27 # Per bank write bursts
system.physmem.perBankRdBursts::4 23 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 38 # Per bank write bursts
system.physmem.perBankRdBursts::8 7 # Per bank write bursts
system.physmem.perBankRdBursts::9 4 # Per bank write bursts
system.physmem.perBankRdBursts::10 2 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 57 # Per bank write bursts
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankRdBursts::14 63 # Per bank write bursts
system.physmem.perBankRdBursts::15 41 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 28814000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 511 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation
system.physmem.totQLat 3584250 # Total ticks spent queuing
system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 8.86 # Data bus utilization in percentage
system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 428 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 56387.48 # Average gap between requests
system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 12618 # Number of BP lookups
system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups
system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 57692 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 796 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 25362 # Type of FU issued
system.cpu.iq.rate 0.439610 # Inst issue rate
system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1579 # number of nop insts executed
system.cpu.iew.exec_refs 6244 # number of memory reference insts executed
system.cpu.iew.exec_branches 5021 # Number of branches executed
system.cpu.iew.exec_stores 2299 # Number of stores executed
system.cpu.iew.exec_rate 0.411045 # Inst execution rate
system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10530 # num instructions producing a value
system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3673 # Number of memory references committed
system.cpu.commit.loads 2225 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3358 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 62581 # The number of ROB reads
system.cpu.rob.rob_writes 65380 # The number of ROB writes
system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 36850 # number of integer regfile reads
system.cpu.int_regfile_writes 20548 # number of integer regfile writes
system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits
system.cpu.dcache.overall_hits::total 4642 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses
system.cpu.dcache.overall_misses::total 549 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles
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system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
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system.cpu.icache.tags.data_accesses 15425 # Number of data accesses
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system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 581 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
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system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles
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system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
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system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
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system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses
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system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
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system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency
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system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadResp 426 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 511 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 511 # Request fanout histogram
system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 9.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

124
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.000008 # Number of seconds simulated
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 353219 # Simulator instruction rate (inst/s)
host_op_rate 353015 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 177141347 # Simulator tick rate (ticks/s)
host_mem_usage 236080 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory
system.physmem.bytes_read::total 72170 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory
system.physmem.bytes_written::total 9042 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory
system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory
system.physmem.num_other::total 6 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15225 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 15162 # Number of instructions committed
system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
system.cpu.num_int_insts 12219 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
system.cpu.num_int_register_writes 13819 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 3683 # number of memory refs
system.cpu.num_load_insts 2231 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 3363 # Number of branches fetched
system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
system.membus.trans_dist::ReadReq 17432 # Transaction distribution
system.membus.trans_dist::ReadResp 17432 # Transaction distribution
system.membus.trans_dist::WriteReq 1442 # Transaction distribution
system.membus.trans_dist::WriteResp 1442 # Transaction distribution
system.membus.trans_dist::SwapReq 6 # Transaction distribution
system.membus.trans_dist::SwapResp 6 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 18880 # Request fanout histogram
system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram
system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 18880 # Request fanout histogram
---------- End Simulation Statistics ----------

474
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
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@ -0,0 +1,474 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000044 # Number of seconds simulated
sim_ticks 44282500 # Number of ticks simulated
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 282453 # Simulator instruction rate (inst/s)
host_op_rate 282325 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 824249311 # Simulator tick rate (ticks/s)
host_mem_usage 245052 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 88565 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 15162 # Number of instructions committed
system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
system.cpu.num_int_insts 12219 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 3683 # number of memory refs
system.cpu.num_load_insts 2231 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 3363 # Number of branches fetched
system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
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system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
system.cpu.dcache.overall_hits::total 3529 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 138 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.icache.tags.replacements 0 # number of replacements
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system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
system.cpu.icache.overall_hits::total 14928 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
system.cpu.icache.overall_misses::total 280 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
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system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 416 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles
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system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 331 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 416 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 416 # Request fanout histogram
system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 4.7 # Layer utilization (%)
---------- End Simulation Statistics ----------

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---------- Begin Simulation Statistics ----------
sim_seconds 0.054141 # Number of seconds simulated
sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 991860 # Simulator instruction rate (inst/s)
host_op_rate 996799 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 592702245 # Simulator tick rate (ticks/s)
host_mem_usage 389728 # Number of bytes of host memory used
host_seconds 91.35 # Real time elapsed on the host
sim_insts 90602408 # Number of instructions simulated
sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 108282002 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602408 # Number of instructions committed
system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
system.cpu.num_int_insts 72326352 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732305 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054081 # Class of executed instruction
system.membus.trans_dist::ReadReq 130287906 # Transaction distribution
system.membus.trans_dist::ReadResp 130291793 # Transaction distribution
system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram
system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 135031171 # Request fanout histogram
---------- End Simulation Statistics ----------

648
tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -0,0 +1,648 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.147149 # Number of seconds simulated
sim_ticks 147148719500 # Number of ticks simulated
final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 596574 # Simulator instruction rate (inst/s)
host_op_rate 599539 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 969178238 # Simulator tick rate (ticks/s)
host_mem_usage 398700 # Number of bytes of host memory used
host_seconds 151.83 # Real time elapsed on the host
sim_insts 90576862 # Number of instructions simulated
sim_ops 91026991 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 294297439 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576862 # Number of instructions committed
system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
system.cpu.num_int_insts 72326352 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732305 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054081 # Class of executed instruction
system.cpu.dcache.tags.replacements 942702 # number of replacements
system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits
system.cpu.dcache.overall_hits::total 26245827 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
system.cpu.dcache.overall_misses::total 946799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
system.cpu.dcache.writebacks::total 942334 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
system.cpu.icache.tags.replacements 2 # number of replacements
system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
system.cpu.icache.overall_hits::total 107830173 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 2 # number of writebacks
system.cpu.icache.writebacks::total 2 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits
system.cpu.l2cache.overall_hits::total 932057 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 792 # Transaction distribution
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15340 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15340 # Request fanout histogram
system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

124
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@ -0,0 +1,124 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.122216 # Number of seconds simulated
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1393980 # Simulator instruction rate (inst/s)
host_op_rate 1394037 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 698723411 # Simulator tick rate (ticks/s)
host_mem_usage 370524 # Number of bytes of host memory used
host_seconds 174.91 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory
system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431648 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29302884 # Number of branches fetched
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
system.membus.trans_dist::SwapReq 3886 # Transaction distribution
system.membus.trans_dist::SwapResp 3886 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 349547768 # Request fanout histogram
---------- End Simulation Statistics ----------

127
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@ -0,0 +1,127 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 769614 # Simulator instruction rate (inst/s)
host_op_rate 1355167 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 823011137 # Simulator tick rate (ticks/s)
host_mem_usage 396564 # Number of bytes of host memory used
host_seconds 205.28 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900081 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278169482 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29309705 # Number of branches fetched
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram
system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 339915363 # Request fanout histogram
---------- End Simulation Statistics ----------

152
tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
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@ -0,0 +1,152 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1428598 # Simulator instruction rate (inst/s)
host_op_rate 1428597 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 714299076 # Simulator tick rate (ticks/s)
host_mem_usage 244476 # Number of bytes of host memory used
host_seconds 279.06 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory
system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory
system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory
system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory
system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520764 # DTB write accesses
system.cpu.dtb.data_hits 168275218 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664595 # Number of instructions committed
system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365907 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275274 # number of memory refs
system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_store_insts 73520764 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 398664824 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 44587532 # Number of branches fetched
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction
system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664651 # Class of executed instruction
system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 566939869 # Request fanout histogram
---------- End Simulation Statistics ----------

2902
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
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997
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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@ -0,0 +1,997 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 856943 # Simulator instruction rate (inst/s)
host_op_rate 856930 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 110961270 # Simulator tick rate (ticks/s)
host_mem_usage 258436 # Number of bytes of host memory used
host_seconds 0.79 # Real time elapsed on the host
sim_insts 677333 # Number of instructions simulated
sim_ops 677333 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 175326 # Number of instructions committed
system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
system.cpu0.num_int_insts 120376 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 82397 # number of memory refs
system.cpu0.num_load_insts 54591 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles
system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu0.Branches 29689 # Number of branches fetched
system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction
system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction
system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 175388 # Class of executed instruction
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
system.cpu0.dcache.overall_misses::total 328 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.icache.tags.replacements 215 # number of replacements
system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
system.cpu0.icache.overall_hits::total 174921 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
system.cpu0.icache.writebacks::total 215 # number of writebacks
system.cpu1.numCycles 173297 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 167400 # Number of instructions committed
system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls
system.cpu1.num_int_insts 107326 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read
system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 49494 # number of memory refs
system.cpu1.num_load_insts 39345 # Number of load instructions
system.cpu1.num_store_insts 10149 # Number of store instructions
system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles
system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles
system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles
system.cpu1.Branches 35694 # Number of branches fetched
system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction
system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction
system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction
system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 167432 # Class of executed instruction
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits
system.cpu1.dcache.overall_hits::total 49120 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses
system.cpu1.dcache.overall_misses::total 287 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.tags.replacements 278 # number of replacements
system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits
system.cpu1.icache.overall_hits::total 167074 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
system.cpu1.icache.overall_misses::total 358 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 278 # number of writebacks
system.cpu1.icache.writebacks::total 278 # number of writebacks
system.cpu2.numCycles 173296 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 167335 # Number of instructions committed
system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 633 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls
system.cpu2.num_int_insts 114196 # number of integer instructions
system.cpu2.num_fp_insts 0 # number of float instructions
system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read
system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu2.num_mem_refs 59830 # number of memory refs
system.cpu2.num_load_insts 42793 # Number of load instructions
system.cpu2.num_store_insts 17037 # Number of store instructions
system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles
system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles
system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
system.cpu2.Branches 32221 # Number of branches fetched
system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction
system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction
system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction
system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 167367 # Class of executed instruction
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits
system.cpu2.dcache.overall_hits::total 59499 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses
system.cpu2.dcache.overall_misses::total 255 # number of overall misses
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.tags.replacements 278 # number of replacements
system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits
system.cpu2.icache.overall_hits::total 167009 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
system.cpu2.icache.overall_misses::total 358 # number of overall misses
system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks 278 # number of writebacks
system.cpu2.icache.writebacks::total 278 # number of writebacks
system.cpu3.numCycles 173297 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 167272 # Number of instructions committed
system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 633 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls
system.cpu3.num_int_insts 113295 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read
system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu3.num_mem_refs 58510 # number of memory refs
system.cpu3.num_load_insts 42344 # Number of load instructions
system.cpu3.num_store_insts 16166 # Number of store instructions
system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles
system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
system.cpu3.Branches 32639 # Number of branches fetched
system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 167304 # Class of executed instruction
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
system.cpu3.dcache.overall_misses::total 260 # number of overall misses
system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.tags.replacements 279 # number of replacements
system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
system.cpu3.icache.overall_hits::total 166945 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
system.cpu3.icache.overall_misses::total 359 # number of overall misses
system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks 279 # number of writebacks
system.cpu3.icache.writebacks::total 279 # number of writebacks
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use
system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 19424 # Number of tag accesses
system.l2c.tags.data_accesses 19424 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 1220 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 559 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.membus.snoop_filter.tot_requests 879 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 320 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadResp 423 # Transaction distribution
system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
system.membus.trans_dist::ReadExReq 183 # Transaction distribution
system.membus.trans_dist::ReadExResp 136 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 879 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 879 # Request fanout histogram
system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 0 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram
---------- End Simulation Statistics ----------

1644
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
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152
tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1535738 # Simulator instruction rate (inst/s)
host_op_rate 1535737 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 768748978 # Simulator tick rate (ticks/s)
host_mem_usage 246592 # Number of bytes of host memory used
host_seconds 57.52 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory
system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory
system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory
system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory
system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.itb.fetch_hits 88438073 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 88442007 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
system.cpu.num_int_insts 78039444 # number of integer instructions
system.cpu.num_fp_insts 267757 # number of float instructions
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
system.cpu.num_mem_refs 34987415 # number of memory refs
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 88442007 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 123328088 # Request fanout histogram
---------- End Simulation Statistics ----------

546
tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -0,0 +1,546 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.134742 # Number of seconds simulated
sim_ticks 134741611500 # Number of ticks simulated
final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 882134 # Simulator instruction rate (inst/s)
host_op_rate 882134 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1345475029 # Simulator tick rate (ticks/s)
host_mem_usage 255564 # Number of bytes of host memory used
host_seconds 100.14 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory
system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory
system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory
system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.itb.fetch_hits 88438074 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 269483223 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
system.cpu.num_int_insts 78039444 # number of integer instructions
system.cpu.num_fp_insts 267757 # number of float instructions
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
system.cpu.num_mem_refs 34987415 # number of memory refs
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 269483223 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
system.cpu.dcache.tags.replacements 200248 # number of replacements
system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks
system.cpu.dcache.writebacks::total 168278 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
system.cpu.icache.tags.replacements 74391 # number of replacements
system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses
system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits
system.cpu.icache.overall_hits::total 88361638 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
system.cpu.icache.overall_misses::total 76436 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 74391 # number of writebacks
system.cpu.icache.writebacks::total 74391 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1199082500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 131998 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 731 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9441 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21639 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 70696 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33240 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 33240 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 70696 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 116632 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 70696 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits
system.cpu.l2cache.overall_hits::total 116632 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5740 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 5740 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27526 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 27526 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 5740 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158408 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 164148 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 5740 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158408 # number of overall misses
system.cpu.l2cache.overall_misses::total 164148 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7787542500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7787542500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 341866000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 341866000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1637990000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1637990000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 341866000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9425532500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9767398500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 341866000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9425532500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9767398500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168278 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 168278 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 76436 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 60766 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 60766 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911574 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911574 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075096 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075096 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452984 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452984 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075096 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775203 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks
system.cpu.l2cache.writebacks::total 114382 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 131998 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 33266 # Transaction distribution
system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution
system.membus.trans_dist::CleanEvict 13845 # Transaction distribution
system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 292375 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 292375 # Request fanout histogram
system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------

243
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View file

@ -0,0 +1,243 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.048960 # Number of seconds simulated
sim_ticks 48960022500 # Number of ticks simulated
final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 866033 # Simulator instruction rate (inst/s)
host_op_rate 1107536 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 597928109 # Simulator tick rate (ticks/s)
host_mem_usage 264428 # Number of bytes of host memory used
host_seconds 81.88 # Real time elapsed on the host
sim_insts 70913204 # Number of instructions simulated
sim_ops 90688159 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 97920046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70913204 # Number of instructions committed
system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528528 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741468 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
system.membus.trans_dist::ReadReq 100925158 # Transaction distribution
system.membus.trans_dist::ReadResp 100941077 # Transaction distribution
system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930641 # Request fanout histogram
system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram
system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 120930641 # Request fanout histogram
---------- End Simulation Statistics ----------

662
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
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@ -0,0 +1,662 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.128077 # Number of seconds simulated
sim_ticks 128076834500 # Number of ticks simulated
final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 531513 # Simulator instruction rate (inst/s)
host_op_rate 678593 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 967329196 # Simulator tick rate (ticks/s)
host_mem_usage 273400 # Number of bytes of host memory used
host_seconds 132.40 # Real time elapsed on the host
sim_insts 70373651 # Number of instructions simulated
sim_ops 89847385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory
system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory
system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory
system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory
system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 256153669 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373651 # Number of instructions committed
system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528528 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741468 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
system.cpu.dcache.tags.replacements 155902 # number of replacements
system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits
system.cpu.dcache.overall_hits::total 42569839 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses
system.cpu.dcache.overall_misses::total 183873 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks
system.cpu.dcache.writebacks::total 128175 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency
system.cpu.icache.tags.replacements 16890 # number of replacements
system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses
system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits
system.cpu.icache.overall_hits::total 78126184 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
system.cpu.icache.overall_misses::total 18908 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 16890 # number of writebacks
system.cpu.icache.writebacks::total 16890 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 95333 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits
system.cpu.l2cache.overall_hits::total 51431 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses
system.cpu.l2cache.overall_misses::total 127475 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks
system.cpu.l2cache.writebacks::total 86150 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 95333 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 25194 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution
system.membus.trans_dist::CleanEvict 6168 # Transaction distribution
system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 219817 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 219817 # Request fanout histogram
system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

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@ -0,0 +1,124 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148677000 # Number of ticks simulated
final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1339454 # Simulator instruction rate (inst/s)
host_op_rate 1356797 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 679186650 # Simulator tick rate (ticks/s)
host_mem_usage 246572 # Number of bytes of host memory used
host_seconds 100.34 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297355 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398959 # Number of instructions committed
system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187757 # number of integer instructions
system.cpu.num_fp_insts 2326976 # number of float instructions
system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160261 # number of memory refs
system.cpu.num_load_insts 37275864 # Number of load instructions
system.cpu.num_store_insts 20884397 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719094 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293808 # Class of executed instruction
system.membus.trans_dist::ReadReq 171784880 # Transaction distribution
system.membus.trans_dist::ReadResp 171784880 # Transaction distribution
system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
system.membus.trans_dist::SwapReq 15916 # Transaction distribution
system.membus.trans_dist::SwapResp 15916 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 192665100 # Request fanout histogram
system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 192665100 # Request fanout histogram
---------- End Simulation Statistics ----------

535
tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -0,0 +1,535 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.203116 # Number of seconds simulated
sim_ticks 203115946500 # Number of ticks simulated
final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 790551 # Simulator instruction rate (inst/s)
host_op_rate 800787 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1194752753 # Simulator tick rate (ticks/s)
host_mem_usage 255284 # Number of bytes of host memory used
host_seconds 170.01 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory
system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory
system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory
system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 406231893 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398959 # Number of instructions committed
system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187757 # number of integer instructions
system.cpu.num_fp_insts 2326976 # number of float instructions
system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160261 # number of memory refs
system.cpu.num_load_insts 37275864 # Number of load instructions
system.cpu.num_store_insts 20884397 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719094 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293808 # Class of executed instruction
system.cpu.dcache.tags.replacements 146583 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits
system.cpu.dcache.overall_hits::total 57944940 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses
system.cpu.dcache.overall_misses::total 150664 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks
system.cpu.dcache.writebacks::total 123865 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
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system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use
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system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id
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system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
system.cpu.icache.overall_misses::total 187024 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
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system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id
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system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 99022 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 29258 # Transaction distribution
system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution
system.membus.trans_dist::CleanEvict 10301 # Transaction distribution
system.membus.trans_dist::ReadExReq 101264 # Transaction distribution
system.membus.trans_dist::ReadExResp 101264 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 226093 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 226093 # Request fanout histogram
system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

152
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@ -0,0 +1,152 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.045952 # Number of seconds simulated
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1593313 # Simulator instruction rate (inst/s)
host_op_rate 1593310 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 796655733 # Simulator tick rate (ticks/s)
host_mem_usage 242160 # Number of bytes of host memory used
host_seconds 57.68 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory
system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory
system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory
system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory
system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.itb.fetch_hits 91903089 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 91903136 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 91903136 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903056 # Number of instructions committed
system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
system.cpu.num_int_insts 79581109 # number of integer instructions
system.cpu.num_fp_insts 6862064 # number of float instructions
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
system.cpu.num_mem_refs 26497334 # number of memory refs
system.cpu.num_load_insts 19996208 # Number of load instructions
system.cpu.num_store_insts 6501126 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 91903136 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 10240685 # Number of branches fetched
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91903089 # Class of executed instruction
system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 118400390 # Request fanout histogram
---------- End Simulation Statistics ----------

534
tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -0,0 +1,534 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.118763 # Number of seconds simulated
sim_ticks 118762761500 # Number of ticks simulated
final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 940295 # Simulator instruction rate (inst/s)
host_op_rate 940295 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1215106876 # Simulator tick rate (ticks/s)
host_mem_usage 251128 # Number of bytes of host memory used
host_seconds 97.74 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.itb.fetch_hits 91903090 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 91903137 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 237525523 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903056 # Number of instructions committed
system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
system.cpu.num_int_insts 79581109 # number of integer instructions
system.cpu.num_fp_insts 6862064 # number of float instructions
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
system.cpu.num_mem_refs 26497334 # number of memory refs
system.cpu.num_load_insts 19996208 # Number of load instructions
system.cpu.num_store_insts 6501126 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 237525523 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 10240685 # Number of branches fetched
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91903089 # Class of executed instruction
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
system.cpu.dcache.overall_misses::total 2223 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
system.cpu.icache.tags.replacements 6681 # number of replacements
system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses
system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
system.cpu.icache.overall_hits::total 91894580 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
system.cpu.icache.overall_misses::total 8510 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 6681 # number of writebacks
system.cpu.icache.writebacks::total 6681 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 8510 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 475 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 475 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.307991 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888421 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888421 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2621 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 422 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 422 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4765 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4765 # Request fanout histogram
system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
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@ -0,0 +1,243 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.099596 # Number of seconds simulated
sim_ticks 99596491500 # Number of ticks simulated
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1040518 # Simulator instruction rate (inst/s)
host_op_rate 1096874 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 601401466 # Simulator tick rate (ticks/s)
host_mem_usage 259948 # Number of bytes of host memory used
host_seconds 165.61 # Real time elapsed on the host
sim_insts 172317410 # Number of instructions simulated
sim_ops 181650342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory
system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 199192984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317410 # Number of instructions committed
system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
system.cpu.num_int_insts 143085668 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read
system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read
system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
system.cpu.num_mem_refs 40540779 # number of memory refs
system.cpu.num_load_insts 27896144 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 40300312 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 181650743 # Class of executed instruction
system.membus.trans_dist::ReadReq 217614903 # Transaction distribution
system.membus.trans_dist::ReadResp 217637310 # Transaction distribution
system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
system.membus.trans_dist::SoftPFResp 463 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram
system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 230024467 # Request fanout histogram
---------- End Simulation Statistics ----------

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tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
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@ -0,0 +1,644 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.230198 # Number of seconds simulated
sim_ticks 230197694500 # Number of ticks simulated
final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 718293 # Simulator instruction rate (inst/s)
host_op_rate 757262 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 962214385 # Simulator tick rate (ticks/s)
host_mem_usage 268920 # Number of bytes of host memory used
host_seconds 239.24 # Real time elapsed on the host
sim_insts 171842484 # Number of instructions simulated
sim_ops 181165371 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 460395389 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 171842484 # Number of instructions committed
system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
system.cpu.num_int_insts 143085668 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read
system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read
system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
system.cpu.num_mem_refs 40540779 # number of memory refs
system.cpu.num_load_insts 27896144 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 40300312 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 181650743 # Class of executed instruction
system.cpu.dcache.tags.replacements 40 # number of replacements
system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits
system.cpu.dcache.overall_hits::total 40117812 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency
system.cpu.icache.tags.replacements 1506 # number of replacements
system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses
system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits
system.cpu.icache.overall_hits::total 189857002 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
system.cpu.icache.overall_misses::total 3051 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1506 # number of writebacks
system.cpu.icache.writebacks::total 1506 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 57 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 57 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1729 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1729 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 689 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.566699 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3453 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3453 # Request fanout histogram
system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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@ -0,0 +1,124 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.096723 # Number of seconds simulated
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1393535 # Simulator instruction rate (inst/s)
host_op_rate 1393537 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 696772335 # Simulator tick rate (ticks/s)
host_mem_usage 242012 # Number of bytes of host memory used
host_seconds 138.82 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory
system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory
system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory
system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory
system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory
system.physmem.num_other::total 22406 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445891 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 193444518 # Number of instructions committed
system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974806 # number of integer instructions
system.cpu.num_fp_insts 1970372 # number of float instructions
system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
system.cpu.num_mem_refs 76733958 # number of memory refs
system.cpu.num_load_insts 57735091 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 15132745 # Number of branches fetched
system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 193445773 # Class of executed instruction
system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
system.membus.trans_dist::SwapReq 22406 # Transaction distribution
system.membus.trans_dist::SwapResp 22406 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 270179448 # Request fanout histogram
---------- End Simulation Statistics ----------

515
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@ -0,0 +1,515 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.270600 # Number of seconds simulated
sim_ticks 270599529500 # Number of ticks simulated
final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 833752 # Simulator instruction rate (inst/s)
host_op_rate 833752 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1166291607 # Simulator tick rate (ticks/s)
host_mem_usage 251752 # Number of bytes of host memory used
host_seconds 232.02 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 541199059 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 193444518 # Number of instructions committed
system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974806 # number of integer instructions
system.cpu.num_fp_insts 1970372 # number of float instructions
system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
system.cpu.num_mem_refs 76733958 # number of memory refs
system.cpu.num_load_insts 57735091 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 15132745 # Number of branches fetched
system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 193445773 # Class of executed instruction
system.cpu.dcache.tags.replacements 2 # number of replacements
system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
system.cpu.dcache.overall_misses::total 1575 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
system.cpu.dcache.writebacks::total 2 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
system.cpu.icache.tags.replacements 10362 # number of replacements
system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses
system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits
system.cpu.icache.overall_hits::total 193433248 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
system.cpu.icache.overall_misses::total 12288 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 10362 # number of writebacks
system.cpu.icache.writebacks::total 10362 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits
system.cpu.l2cache.overall_hits::total 8691 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses
system.cpu.l2cache.overall_misses::total 5173 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 5173 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5173 # Request fanout histogram
system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

127
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---------- Begin Simulation Statistics ----------
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 719836 # Simulator instruction rate (inst/s)
host_op_rate 1206511 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 716141111 # Simulator tick rate (ticks/s)
host_mem_usage 284280 # Number of bytes of host memory used
host_seconds 183.47 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory
system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory
system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786559 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 219019986 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12326938 # Number of branches fetched
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram
system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 250692103 # Request fanout histogram
---------- End Simulation Statistics ----------

507
tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -0,0 +1,507 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.250987 # Number of seconds simulated
sim_ticks 250987138500 # Number of ticks simulated
final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 489633 # Simulator instruction rate (inst/s)
host_op_rate 820669 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 930494730 # Simulator tick rate (ticks/s)
host_mem_usage 293244 # Number of bytes of host memory used
host_seconds 269.74 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 501974277 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 219019986 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12326938 # Number of branches fetched
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
system.cpu.dcache.tags.replacements 41 # number of replacements
system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
system.cpu.dcache.overall_misses::total 1905 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
system.cpu.dcache.writebacks::total 7 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
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system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
system.cpu.icache.overall_misses::total 4694 # number of overall misses
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system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4735 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4735 # Request fanout histogram
system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------