X86: Make conditional moves zero extend their 32 bit destinations always.
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@ -639,7 +639,7 @@ let {{
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class Mov(CondRegOp):
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class Mov(CondRegOp):
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code = 'DestReg = merge(SrcReg1, op2, dataSize)'
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code = 'DestReg = merge(SrcReg1, op2, dataSize)'
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else_code = 'DestReg=DestReg;'
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else_code = 'DestReg = merge(DestReg, DestReg, dataSize);'
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# Shift instructions
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# Shift instructions
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