sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports.

Browse source
This commit is contained in:
Gabe Black 2008-06-12 00:58:13 -04:00
parent 1f5b992b58
commit da20c0ec54
1 changed files with 5 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/dev/x86/PC.py
View file

@ -50,6 +50,10 @@ class PC(Platform):
# "Non-existant" port used for timing purposes by the linux kernel # "Non-existant" port used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
# Serial port and console # Serial port and console
console = SimConsole() console = SimConsole()
com_1 = Uart8250() com_1 = Uart8250()
@ -59,6 +63,7 @@ class PC(Platform):
def attachIO(self, bus): def attachIO(self, bus):
self.south_bridge.pio = bus.port self.south_bridge.pio = bus.port
self.i_dont_exist.pio = bus.port self.i_dont_exist.pio = bus.port
self.behind_pci.pio = bus.port
self.com_1.pio = bus.port self.com_1.pio = bus.port
self.pciconfig.pio = bus.default self.pciconfig.pio = bus.default
bus.responder_set = True bus.responder_set = True