protocol: cleaned up MESI...got rid of unneccessary virtual networks
This commit is contained in:
parent
83a9dc2939
commit
d9a2450054
5 changed files with 59 additions and 148 deletions
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@ -27,12 +27,6 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/*
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* $Id: MSI_MOSI_CMP_directory-L1cache.sm 1.10 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
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*
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*/
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machine(L1Cache, "MSI Directory L1 Cache CMP")
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machine(L1Cache, "MSI Directory L1 Cache CMP")
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: int l1_request_latency,
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: int l1_request_latency,
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int l1_response_latency,
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int l1_response_latency,
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@ -47,15 +41,15 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
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// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
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// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
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MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
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MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
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// a local L1 -> this L2 bank
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// a local L1 -> this L2 bank
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MessageBuffer responseFromL1Cache, network="To", virtual_network="3", ordered="false";
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MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false";
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MessageBuffer unblockFromL1Cache, network="To", virtual_network="4", ordered="false";
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MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false";
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// To this node's L1 cache FROM the network
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// To this node's L1 cache FROM the network
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// a L2 bank -> this L1
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// a L2 bank -> this L1
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MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
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MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
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// a L2 bank -> this L1
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// a L2 bank -> this L1
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MessageBuffer responseToL1Cache, network="From", virtual_network="3", ordered="false";
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MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false";
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// STATES
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// STATES
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enumeration(State, desc="Cache states", default="L1Cache_State_I") {
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enumeration(State, desc="Cache states", default="L1Cache_State_I") {
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@ -40,14 +40,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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// L2 BANK QUEUES
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// L2 BANK QUEUES
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// From local bank of L2 cache TO the network
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// From local bank of L2 cache TO the network
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MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="2", ordered="false"; // this L2 bank -> Memory
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MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> Memory
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MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1
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MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> a local L1
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MessageBuffer responseFromL2Cache, network="To", virtual_network="3", ordered="false"; // this L2 bank -> a local L1 || Memory
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MessageBuffer responseFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1 || Memory
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// FROM the network to this local bank of L2 cache
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// FROM the network to this local bank of L2 cache
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MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank
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MessageBuffer unblockToL2Cache, network="From", virtual_network="2", ordered="false"; // a local L1 || Memory -> this L2 bank
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MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank
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MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank
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MessageBuffer responseToL2Cache, network="From", virtual_network="3", ordered="false"; // a local L1 || Memory -> this L2 bank
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MessageBuffer responseToL2Cache, network="From", virtual_network="1", ordered="false"; // a local L1 || Memory -> this L2 bank
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// MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank
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// MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank
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// STATES
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// STATES
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@ -3,8 +3,8 @@ machine(DMA, "DMA Controller")
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: int request_latency
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: int request_latency
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{
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{
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MessageBuffer responseFromDir, network="From", virtual_network="6", ordered="true", no_vector="true";
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MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
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MessageBuffer reqToDirectory, network="To", virtual_network="7", ordered="false", no_vector="true";
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MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
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enumeration(State, desc="DMA states", default="DMA_State_READY") {
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enumeration(State, desc="DMA states", default="DMA_State_READY") {
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READY, desc="Ready to accept a new request";
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READY, desc="Ready to accept a new request";
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@ -51,13 +51,13 @@ machine(DMA, "DMA Controller")
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}
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}
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}
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}
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in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
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in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
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if (dmaResponseQueue_in.isReady()) {
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if (dmaResponseQueue_in.isReady()) {
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peek( dmaResponseQueue_in, DMAResponseMsg) {
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peek( dmaResponseQueue_in, ResponseMsg) {
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if (in_msg.Type == DMAResponseType:ACK) {
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if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:Ack, in_msg.LineAddress);
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trigger(Event:Ack, makeLineAddress(in_msg.Address));
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} else if (in_msg.Type == DMAResponseType:DATA) {
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} else if (in_msg.Type == CoherenceResponseType:DATA) {
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trigger(Event:Data, in_msg.LineAddress);
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trigger(Event:Data, makeLineAddress(in_msg.Address));
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} else {
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} else {
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error("Invalid response type");
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error("Invalid response type");
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}
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}
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@ -67,10 +67,9 @@ machine(DMA, "DMA Controller")
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action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
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action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
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peek(dmaRequestQueue_in, SequencerMsg) {
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peek(dmaRequestQueue_in, SequencerMsg) {
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enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
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enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
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out_msg.PhysicalAddress := in_msg.PhysicalAddress;
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out_msg.Address := in_msg.PhysicalAddress;
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out_msg.LineAddress := in_msg.LineAddress;
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out_msg.Type := CoherenceRequestType:DMA_READ;
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out_msg.Type := DMARequestType:READ;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Destination.add(map_Address_to_Directory(address));
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@ -81,10 +80,9 @@ machine(DMA, "DMA Controller")
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action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
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action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
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peek(dmaRequestQueue_in, SequencerMsg) {
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peek(dmaRequestQueue_in, SequencerMsg) {
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enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
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enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
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out_msg.PhysicalAddress := in_msg.PhysicalAddress;
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out_msg.Address := in_msg.PhysicalAddress;
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out_msg.LineAddress := in_msg.LineAddress;
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out_msg.Type := CoherenceRequestType:DMA_WRITE;
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out_msg.Type := DMARequestType:WRITE;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Destination.add(map_Address_to_Directory(address));
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@ -94,13 +92,11 @@ machine(DMA, "DMA Controller")
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}
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}
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action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
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action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
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peek (dmaResponseQueue_in, DMAResponseMsg) {
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dma_sequencer.ackCallback();
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dma_sequencer.ackCallback();
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}
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}
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}
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action(d_dataCallback, "d", desc="Write data to dma sequencer") {
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action(d_dataCallback, "d", desc="Write data to dma sequencer") {
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peek (dmaResponseQueue_in, DMAResponseMsg) {
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peek (dmaResponseQueue_in, ResponseMsg) {
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dma_sequencer.dataCallback(in_msg.DataBlk);
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dma_sequencer.dataCallback(in_msg.DataBlk);
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}
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}
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}
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}
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@ -40,13 +40,11 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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int directory_latency
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int directory_latency
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{
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{
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MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
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MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false";
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MessageBuffer responseToDir, network="From", virtual_network="3", ordered="false";
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MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false";
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MessageBuffer responseFromDir, network="To", virtual_network="3", ordered="false";
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MessageBuffer dmaRequestFromDir, network="To", virtual_network="6", ordered="true";
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MessageBuffer dmaRequestToDir, network="From", virtual_network="7", ordered="true";
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MessageBuffer requestFromDir, network="To", virtual_network="0", ordered="false";
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MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
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// STATES
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// STATES
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enumeration(State, desc="Directory states", default="Directory_State_I") {
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enumeration(State, desc="Directory states", default="Directory_State_I") {
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@ -167,32 +165,19 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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// ** OUT_PORTS **
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// ** OUT_PORTS **
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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out_port(memQueue_out, MemoryMsg, memBuffer);
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out_port(memQueue_out, MemoryMsg, memBuffer);
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out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir);
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// ** IN_PORTS **
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// ** IN_PORTS **
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//added by SS for dma
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in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
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if (dmaRequestQueue_in.isReady()) {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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if (in_msg.Type == DMARequestType:READ) {
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trigger(Event:DMA_READ, in_msg.LineAddress);
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} else if (in_msg.Type == DMARequestType:WRITE) {
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trigger(Event:DMA_WRITE, in_msg.LineAddress);
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} else {
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error("Invalid message");
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}
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}
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}
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}
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in_port(requestNetwork_in, RequestMsg, requestToDir) {
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in_port(requestNetwork_in, RequestMsg, requestToDir) {
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if (requestNetwork_in.isReady()) {
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if (requestNetwork_in.isReady()) {
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peek(requestNetwork_in, RequestMsg) {
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peek(requestNetwork_in, RequestMsg) {
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assert(in_msg.Destination.isElement(machineID));
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assert(in_msg.Destination.isElement(machineID));
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if (isGETRequest(in_msg.Type)) {
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if (isGETRequest(in_msg.Type)) {
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trigger(Event:Fetch, in_msg.Address);
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trigger(Event:Fetch, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
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trigger(Event:DMA_READ, makeLineAddress(in_msg.Address));
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} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
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trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address));
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} else {
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} else {
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DEBUG_EXPR(in_msg);
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DEBUG_EXPR(in_msg);
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error("Invalid message");
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error("Invalid message");
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@ -328,7 +313,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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}
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}
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//added by SS for dma
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//added by SS for dma
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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@ -342,14 +327,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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}
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}
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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dmaRequestQueue_in.dequeue();
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requestNetwork_in.dequeue();
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}
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}
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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peek(memQueue_in, MemoryMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.PhysicalAddress := address;
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out_msg.Address := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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@ -358,15 +343,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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}
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}
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action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
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action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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peek(requestNetwork_in, RequestMsg) {
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//directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len);
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directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
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directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len);
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}
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}
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}
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}
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action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
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action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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}
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}
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.PhysicalAddress := address;
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out_msg.Address := address;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Type := CoherenceResponseType:ACK;
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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@ -397,7 +380,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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}
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}
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action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
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action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
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dmaRequestQueue_in.recycle();
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requestNetwork_in.recycle();
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}
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}
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@ -410,12 +393,12 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
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enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:INV;
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out_msg.Type := CoherenceResponseType:INV;
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out_msg.Sender := machineID;
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out_msg.Sender := machineID;
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out_msg.Destination := directory[in_msg.PhysicalAddress].Owner;
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out_msg.Destination := directory[address].Owner;
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out_msg.MessageSize := MessageSizeType:Response_Control;
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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}
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@ -424,9 +407,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
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action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
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peek(responseNetwork_in, ResponseMsg) {
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peek(responseNetwork_in, ResponseMsg) {
|
||||||
enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) {
|
enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
|
||||||
out_msg.PhysicalAddress := address;
|
out_msg.Address := address;
|
||||||
out_msg.Type := DMAResponseType:DATA;
|
out_msg.Type := CoherenceResponseType:DATA;
|
||||||
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
|
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
|
||||||
out_msg.Destination.add(map_Address_to_DMA(address));
|
out_msg.Destination.add(map_Address_to_DMA(address));
|
||||||
out_msg.MessageSize := MessageSizeType:Response_Data;
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
||||||
|
@ -439,10 +422,10 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||||
}
|
}
|
||||||
|
|
||||||
action(v_allocateTBE, "v", desc="Allocate TBE") {
|
action(v_allocateTBE, "v", desc="Allocate TBE") {
|
||||||
peek(dmaRequestQueue_in, DMARequestMsg) {
|
peek(requestNetwork_in, RequestMsg) {
|
||||||
TBEs.allocate(address);
|
TBEs.allocate(address);
|
||||||
TBEs[address].DataBlk := in_msg.DataBlk;
|
TBEs[address].DataBlk := in_msg.DataBlk;
|
||||||
TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
|
TBEs[address].PhysicalAddress := in_msg.Address;
|
||||||
TBEs[address].Len := in_msg.Len;
|
TBEs[address].Len := in_msg.Len;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -514,7 +497,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||||
//added by SS for dma support
|
//added by SS for dma support
|
||||||
transition(I, DMA_READ, ID) {
|
transition(I, DMA_READ, ID) {
|
||||||
qf_queueMemoryFetchRequestDMA;
|
qf_queueMemoryFetchRequestDMA;
|
||||||
p_popIncomingDMARequestQueue;
|
j_popIncomingRequestQueue;
|
||||||
}
|
}
|
||||||
|
|
||||||
transition(ID, Memory_Data, I) {
|
transition(ID, Memory_Data, I) {
|
||||||
|
@ -525,7 +508,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||||
transition(I, DMA_WRITE, ID_W) {
|
transition(I, DMA_WRITE, ID_W) {
|
||||||
dw_writeDMAData;
|
dw_writeDMAData;
|
||||||
qw_queueMemoryWBRequest_partial;
|
qw_queueMemoryWBRequest_partial;
|
||||||
p_popIncomingDMARequestQueue;
|
j_popIncomingRequestQueue;
|
||||||
}
|
}
|
||||||
|
|
||||||
transition(ID_W, Memory_Ack, I) {
|
transition(ID_W, Memory_Ack, I) {
|
||||||
|
@ -544,7 +527,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||||
|
|
||||||
transition(M, DMA_READ, M_DRD) {
|
transition(M, DMA_READ, M_DRD) {
|
||||||
inv_sendCacheInvalidate;
|
inv_sendCacheInvalidate;
|
||||||
p_popIncomingDMARequestQueue;
|
j_popIncomingRequestQueue;
|
||||||
}
|
}
|
||||||
|
|
||||||
transition(M_DRD, Data, M_DRDI) {
|
transition(M_DRD, Data, M_DRDI) {
|
||||||
|
@ -563,7 +546,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||||
transition(M, DMA_WRITE, M_DWR) {
|
transition(M, DMA_WRITE, M_DWR) {
|
||||||
v_allocateTBE;
|
v_allocateTBE;
|
||||||
inv_sendCacheInvalidate;
|
inv_sendCacheInvalidate;
|
||||||
p_popIncomingDMARequestQueue;
|
j_popIncomingRequestQueue;
|
||||||
}
|
}
|
||||||
|
|
||||||
transition(M_DWR, Data, M_DWRI) {
|
transition(M_DWR, Data, M_DWRI) {
|
||||||
|
|
|
@ -70,7 +70,8 @@ enumeration(CoherenceRequestType, desc="...") {
|
||||||
WB_NACK, desc="Writeback neg. ack";
|
WB_NACK, desc="Writeback neg. ack";
|
||||||
FWD, desc="Generic FWD";
|
FWD, desc="Generic FWD";
|
||||||
|
|
||||||
|
DMA_READ, desc="DMA Read";
|
||||||
|
DMA_WRITE, desc="DMA Write";
|
||||||
}
|
}
|
||||||
|
|
||||||
// CoherenceResponseType
|
// CoherenceResponseType
|
||||||
|
@ -95,6 +96,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
|
||||||
NetDest Destination, desc="What components receive the request, includes MachineType and num";
|
NetDest Destination, desc="What components receive the request, includes MachineType and num";
|
||||||
MessageSizeType MessageSize, desc="size category of the message";
|
MessageSizeType MessageSize, desc="size category of the message";
|
||||||
DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
|
DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
|
||||||
|
int Len;
|
||||||
bool Dirty, default="false", desc="Dirty bit";
|
bool Dirty, default="false", desc="Dirty bit";
|
||||||
PrefetchBit Prefetch, desc="Is this a prefetch request";
|
PrefetchBit Prefetch, desc="Is this a prefetch request";
|
||||||
}
|
}
|
||||||
|
@ -111,68 +113,4 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
|
||||||
MessageSizeType MessageSize, desc="size category of the message";
|
MessageSizeType MessageSize, desc="size category of the message";
|
||||||
}
|
}
|
||||||
|
|
||||||
enumeration(DMARequestType, desc="...", default="DMARequestType_NULL") {
|
|
||||||
READ, desc="Memory Read";
|
|
||||||
WRITE, desc="Memory Write";
|
|
||||||
NULL, desc="Invalid";
|
|
||||||
}
|
|
||||||
|
|
||||||
enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
|
|
||||||
DATA, desc="DATA read";
|
|
||||||
ACK, desc="ACK write";
|
|
||||||
NULL, desc="Invalid";
|
|
||||||
}
|
|
||||||
|
|
||||||
structure(DMARequestMsg, desc="...", interface="NetworkMessage") {
|
|
||||||
DMARequestType Type, desc="Request type (read/write)";
|
|
||||||
Address PhysicalAddress, desc="Physical address for this request";
|
|
||||||
Address LineAddress, desc="Line address for this request";
|
|
||||||
NetDest Destination, desc="Destination";
|
|
||||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
|
||||||
int Offset, desc="The offset into the datablock";
|
|
||||||
int Len, desc="The length of the request";
|
|
||||||
MessageSizeType MessageSize, desc="size category of the message";
|
|
||||||
}
|
|
||||||
|
|
||||||
structure(DMAResponseMsg, desc="...", interface="NetworkMessage") {
|
|
||||||
DMAResponseType Type, desc="Response type (DATA/ACK)";
|
|
||||||
Address PhysicalAddress, desc="Physical address for this request";
|
|
||||||
Address LineAddress, desc="Line address for this request";
|
|
||||||
NetDest Destination, desc="Destination";
|
|
||||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
|
||||||
MessageSizeType MessageSize, desc="size category of the message";
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
GenericRequestType convertToGenericType(CoherenceRequestType type) {
|
|
||||||
if(type == CoherenceRequestType:PUTX) {
|
|
||||||
return GenericRequestType:PUTX;
|
|
||||||
} else if(type == CoherenceRequestType:GETS) {
|
|
||||||
return GenericRequestType:GETS;
|
|
||||||
} else if(type == CoherenceRequestType:GET_INSTR) {
|
|
||||||
return GenericRequestType:GET_INSTR;
|
|
||||||
} else if(type == CoherenceRequestType:GETX) {
|
|
||||||
return GenericRequestType:GETX;
|
|
||||||
} else if(type == CoherenceRequestType:UPGRADE) {
|
|
||||||
return GenericRequestType:UPGRADE;
|
|
||||||
} else if(type == CoherenceRequestType:PUTS) {
|
|
||||||
return GenericRequestType:PUTS;
|
|
||||||
} else if(type == CoherenceRequestType:INV) {
|
|
||||||
return GenericRequestType:INV;
|
|
||||||
} else if(type == CoherenceRequestType:INV_S) {
|
|
||||||
return GenericRequestType:INV_S;
|
|
||||||
} else if(type == CoherenceRequestType:L1_DG) {
|
|
||||||
return GenericRequestType:DOWNGRADE;
|
|
||||||
} else if(type == CoherenceRequestType:WB_ACK) {
|
|
||||||
return GenericRequestType:WB_ACK;
|
|
||||||
} else if(type == CoherenceRequestType:EXE_ACK) {
|
|
||||||
return GenericRequestType:EXE_ACK;
|
|
||||||
} else {
|
|
||||||
DEBUG_EXPR(type);
|
|
||||||
error("invalid CoherenceRequestType");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue