ruby: moesi cmp directory: separate actions for external hits

This patch adds separate actions for requests that missed in the local cache
and messages were sent out to get the requested line. These separate actions
are required for differentiating between the hit and miss latencies in the
statistics collected.
This commit is contained in:
Nilay Vaish 2013-06-25 00:32:04 -05:00
parent 128ab50c47
commit d8ed1d1a2c

View file

@ -629,6 +629,12 @@ machine(L1Cache, "Directory protocol")
sequencer.readCallback(address, cache_entry.DataBlk); sequencer.readCallback(address, cache_entry.DataBlk);
} }
action(hx_load_hit, "hx", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") { action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry)); assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
@ -636,6 +642,13 @@ machine(L1Cache, "Directory protocol")
cache_entry.Dirty := true; cache_entry.Dirty := true;
} }
action(xx_store_hit, "\xx", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
action(i_allocateTBE, "i", desc="Allocate TBE") { action(i_allocateTBE, "i", desc="Allocate TBE") {
check_allocate(TBEs); check_allocate(TBEs);
TBEs.allocate(address); TBEs.allocate(address);
@ -1162,7 +1175,7 @@ machine(L1Cache, "Directory protocol")
} }
transition(OM, All_acks, MM_W) { transition(OM, All_acks, MM_W) {
hh_store_hit; xx_store_hit;
gg_sendUnblockExclusive; gg_sendUnblockExclusive;
s_deallocateTBE; s_deallocateTBE;
o_scheduleUseTimeout; o_scheduleUseTimeout;
@ -1183,7 +1196,7 @@ machine(L1Cache, "Directory protocol")
transition(IS, Data, S) { transition(IS, Data, S) {
u_writeDataToCache; u_writeDataToCache;
m_decrementNumberOfMessages; m_decrementNumberOfMessages;
h_load_hit; hx_load_hit;
g_sendUnblock; g_sendUnblock;
s_deallocateTBE; s_deallocateTBE;
n_popResponseQueue; n_popResponseQueue;
@ -1192,7 +1205,7 @@ machine(L1Cache, "Directory protocol")
transition(IS, Exclusive_Data, M_W) { transition(IS, Exclusive_Data, M_W) {
u_writeDataToCache; u_writeDataToCache;
m_decrementNumberOfMessages; m_decrementNumberOfMessages;
h_load_hit; hx_load_hit;
gg_sendUnblockExclusive; gg_sendUnblockExclusive;
o_scheduleUseTimeout; o_scheduleUseTimeout;
s_deallocateTBE; s_deallocateTBE;