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O3: Skipping mem-order violation check for uncachable loads.

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Uncachable load is not executed until it reaches the head of the ROB,
hence cannot cause one.
This commit is contained in:
Min Kyu Jeong 2010-08-23 11:18:42 -05:00
parent e6a0be648e
commit d8d6b869a2
3 changed files with 21 additions and 11 deletions
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6
src/cpu/o3/fetch_impl.hh
View file

@ -1150,9 +1150,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
instruction->setThreadState(cpu->thread[tid]); instruction->setThreadState(cpu->thread[tid]);
DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
"[sn:%lli]\n", "[sn:%lli]\n", tid, instruction->readPC(),
tid, instruction->readPC(), inst_seq); instruction->readMicroPC(), inst_seq);
//DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);

8
src/cpu/o3/iew_impl.hh
View file

@ -1318,10 +1318,10 @@ DefaultIEW<Impl>::executeInsts()
DynInstPtr violator; DynInstPtr violator;
violator = ldstQueue.getMemDepViolator(tid); violator = ldstQueue.getMemDepViolator(tid);
DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %#x "
"%#x, inst PC: %#x. Addr is: %#x.\n", "[sn:%lli], inst PC: %#x [sn:%lli]. Addr is: %#x.\n",
violator->readPC(), inst->readPC(), inst->physEffAddr); violator->readPC(), violator->seqNum,
inst->readPC(), inst->seqNum, inst->physEffAddr);
// Ensure the violating instruction is older than // Ensure the violating instruction is older than
// current squash // current squash
/* if (fetchRedirect[tid] && /* if (fetchRedirect[tid] &&

18
src/cpu/o3/lsq_unit_impl.hh
View file

@ -479,9 +479,14 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// are quad word accesses. // are quad word accesses.
// @todo: Fix this, magic number being used here // @todo: Fix this, magic number being used here
// @todo: Uncachable load is not executed until it reaches
// the head of the ROB. Once this if checks only the executed
// loads(as noted above), this check can be removed
if (loadQueue[load_idx]->effAddrValid && if (loadQueue[load_idx]->effAddrValid &&
(loadQueue[load_idx]->effAddr >> 8) == ((loadQueue[load_idx]->effAddr >> 8)
(inst->effAddr >> 8)) { == (inst->effAddr >> 8)) &&
!loadQueue[load_idx]->uncacheable()) {
// A load incorrectly passed this load. Squash and refetch. // A load incorrectly passed this load. Squash and refetch.
// For now return a fault to show that it was unsuccessful. // For now return a fault to show that it was unsuccessful.
DynInstPtr violator = loadQueue[load_idx]; DynInstPtr violator = loadQueue[load_idx];
@ -553,9 +558,14 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
// are quad word accesses. // are quad word accesses.
// @todo: Fix this, magic number being used here // @todo: Fix this, magic number being used here
// @todo: Uncachable load is not executed until it reaches
// the head of the ROB. Once this if checks only the executed
// loads(as noted above), this check can be removed
if (loadQueue[load_idx]->effAddrValid && if (loadQueue[load_idx]->effAddrValid &&
(loadQueue[load_idx]->effAddr >> 8) == ((loadQueue[load_idx]->effAddr >> 8)
(store_inst->effAddr >> 8)) { == (store_inst->effAddr >> 8)) &&
!loadQueue[load_idx]->uncacheable()) {
// A load incorrectly passed this store. Squash and refetch. // A load incorrectly passed this store. Squash and refetch.
// For now return a fault to show that it was unsuccessful. // For now return a fault to show that it was unsuccessful.
DynInstPtr violator = loadQueue[load_idx]; DynInstPtr violator = loadQueue[load_idx];