mem: change NULL to nullptr in the cache related classes

Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Nikos Nikoleris 2016-05-26 11:56:24 +01:00
parent 90bf50b4c7
commit d68f3577d6
12 changed files with 49 additions and 49 deletions

View file

@ -80,7 +80,7 @@ BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
isReadOnly(p->is_read_only), isReadOnly(p->is_read_only),
blocked(0), blocked(0),
order(0), order(0),
noTargetMSHR(NULL), noTargetMSHR(nullptr),
missCount(p->max_miss_count), missCount(p->max_miss_count),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
system(p->system) system(p->system)

View file

@ -322,7 +322,7 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
old_blk->invalidate(); old_blk->invalidate();
} }
blk = NULL; blk = nullptr;
// lookupLatency is the latency in case the request is uncacheable. // lookupLatency is the latency in case the request is uncacheable.
lat = lookupLatency; lat = lookupLatency;
return false; return false;
@ -394,10 +394,10 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
return true; return true;
} }
if (blk == NULL) { if (blk == nullptr) {
// need to do a replacement // need to do a replacement
blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
if (blk == NULL) { if (blk == nullptr) {
// no replaceable block available: give up, fwd to next level. // no replaceable block available: give up, fwd to next level.
incMissCount(pkt); incMissCount(pkt);
return false; return false;
@ -427,7 +427,7 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
incHitCount(pkt); incHitCount(pkt);
return true; return true;
} else if (pkt->cmd == MemCmd::CleanEvict) { } else if (pkt->cmd == MemCmd::CleanEvict) {
if (blk != NULL) { if (blk != nullptr) {
// Found the block in the tags, need to stop CleanEvict from // Found the block in the tags, need to stop CleanEvict from
// propagating further down the hierarchy. Returning true will // propagating further down the hierarchy. Returning true will
// treat the CleanEvict like a satisfied write request and delete // treat the CleanEvict like a satisfied write request and delete
@ -439,7 +439,7 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
// like a Writeback which could not find a replaceable block so has to // like a Writeback which could not find a replaceable block so has to
// go to next level. // go to next level.
return false; return false;
} else if ((blk != NULL) && } else if ((blk != nullptr) &&
(pkt->needsWritable() ? blk->isWritable() : (pkt->needsWritable() ? blk->isWritable() :
blk->isReadable())) { blk->isReadable())) {
// OK to satisfy access // OK to satisfy access
@ -448,12 +448,12 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
return true; return true;
} }
// Can't satisfy access normally... either no block (blk == NULL) // Can't satisfy access normally... either no block (blk == nullptr)
// or have block but need writable // or have block but need writable
incMissCount(pkt); incMissCount(pkt);
if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) {
// complete miss on store conditional... just give up now // complete miss on store conditional... just give up now
pkt->req->setExtraData(0); pkt->req->setExtraData(0);
return true; return true;
@ -674,7 +674,7 @@ Cache::recvTimingReq(PacketPtr pkt)
// We use lookupLatency here because it is used to specify the latency // We use lookupLatency here because it is used to specify the latency
// to access. // to access.
Cycles lat = lookupLatency; Cycles lat = lookupLatency;
CacheBlk *blk = NULL; CacheBlk *blk = nullptr;
bool satisfied = false; bool satisfied = false;
{ {
PacketList writebacks; PacketList writebacks;
@ -1013,7 +1013,7 @@ Cache::recvAtomic(PacketPtr pkt)
// writebacks... that would mean that someone used an atomic // writebacks... that would mean that someone used an atomic
// access in timing mode // access in timing mode
CacheBlk *blk = NULL; CacheBlk *blk = nullptr;
PacketList writebacks; PacketList writebacks;
bool satisfied = access(pkt, blk, lat, writebacks); bool satisfied = access(pkt, blk, lat, writebacks);
@ -1035,7 +1035,7 @@ Cache::recvAtomic(PacketPtr pkt)
PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
bool is_forward = (bus_pkt == NULL); bool is_forward = (bus_pkt == nullptr);
if (is_forward) { if (is_forward) {
// just forwarding the same request to the next level // just forwarding the same request to the next level
@ -1275,7 +1275,7 @@ Cache::recvTimingResp(PacketPtr pkt)
if (mshr == noTargetMSHR) { if (mshr == noTargetMSHR) {
// we always clear at least one target // we always clear at least one target
clearBlocked(Blocked_NoTargets); clearBlocked(Blocked_NoTargets);
noTargetMSHR = NULL; noTargetMSHR = nullptr;
} }
// Initial target is used just for stats // Initial target is used just for stats
@ -1315,7 +1315,7 @@ Cache::recvTimingResp(PacketPtr pkt)
pkt->getAddr()); pkt->getAddr());
blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill); blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill);
assert(blk != NULL); assert(blk != nullptr);
} }
// allow invalidation responses originating from write-line // allow invalidation responses originating from write-line
@ -1360,7 +1360,7 @@ Cache::recvTimingResp(PacketPtr pkt)
mshr->promoteWritable(); mshr->promoteWritable();
// NB: we use the original packet here and not the response! // NB: we use the original packet here and not the response!
blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill); blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill);
assert(blk != NULL); assert(blk != nullptr);
// treat as a fill, and discard the invalidation // treat as a fill, and discard the invalidation
// response // response
@ -1660,7 +1660,7 @@ Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
{ {
CacheBlk *blk = tags->findVictim(addr); CacheBlk *blk = tags->findVictim(addr);
// It is valid to return NULL if there is no victim // It is valid to return nullptr if there is no victim
if (!blk) if (!blk)
return nullptr; return nullptr;
@ -1674,7 +1674,7 @@ Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
assert(repl_mshr->needsWritable()); assert(repl_mshr->needsWritable());
// too hard to replace block with transient state // too hard to replace block with transient state
// allocation failed, block not inserted // allocation failed, block not inserted
return NULL; return nullptr;
} else { } else {
DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
"(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns",
@ -1726,7 +1726,7 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
assert(addr == blockAlign(addr)); assert(addr == blockAlign(addr));
assert(!writeBuffer.findMatch(addr, is_secure)); assert(!writeBuffer.findMatch(addr, is_secure));
if (blk == NULL) { if (blk == nullptr) {
// better have read new data... // better have read new data...
assert(pkt->hasData()); assert(pkt->hasData());
@ -1737,9 +1737,9 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
// need to do a replacement if allocating, otherwise we stick // need to do a replacement if allocating, otherwise we stick
// with the temporary storage // with the temporary storage
blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL; blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr;
if (blk == NULL) { if (blk == nullptr) {
// No replaceable block or a mostly exclusive // No replaceable block or a mostly exclusive
// cache... just use temporary storage to complete the // cache... just use temporary storage to complete the
// current request and then get rid of it // current request and then get rid of it
@ -2309,7 +2309,7 @@ Cache::isCachedAbove(PacketPtr pkt, bool is_timing) const
// prefetch request because prefetch requests need an MSHR and may // prefetch request because prefetch requests need an MSHR and may
// generate a snoop response. // generate a snoop response.
assert(pkt->isEviction()); assert(pkt->isEviction());
snoop_pkt.senderState = NULL; snoop_pkt.senderState = nullptr;
cpuSidePort->sendTimingSnoopReq(&snoop_pkt); cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
// Writeback/CleanEvict snoops do not generate a snoop response. // Writeback/CleanEvict snoops do not generate a snoop response.
assert(!(snoop_pkt.cacheResponding())); assert(!(snoop_pkt.cacheResponding()));
@ -2353,7 +2353,7 @@ Cache::sendMSHRQueuePacket(MSHR* mshr)
if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) {
// we should never have hardware prefetches to allocated // we should never have hardware prefetches to allocated
// blocks // blocks
assert(blk == NULL); assert(blk == nullptr);
// We need to check the caches above us to verify that // We need to check the caches above us to verify that
// they don't have a copy of this block in the dirty state // they don't have a copy of this block in the dirty state
@ -2415,7 +2415,7 @@ Cache::sendMSHRQueuePacket(MSHR* mshr)
// MSHR request, proceed to get the packet to send downstream // MSHR request, proceed to get the packet to send downstream
PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
mshr->isForward = (pkt == NULL); mshr->isForward = (pkt == nullptr);
if (mshr->isForward) { if (mshr->isForward) {
// not a cache block request, but a response is expected // not a cache block request, but a response is expected

View file

@ -290,7 +290,7 @@ class Cache : public BaseCache
* Find a block frame for new block at address addr targeting the * Find a block frame for new block at address addr targeting the
* given security space, assuming that the block is not currently * given security space, assuming that the block is not currently
* in the cache. Append writebacks if any to provided packet * in the cache. Append writebacks if any to provided packet
* list. Return free block frame. May return NULL if there are * list. Return free block frame. May return nullptr if there are
* no replaceable blocks at the moment. * no replaceable blocks at the moment.
*/ */
CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
@ -464,10 +464,10 @@ class Cache : public BaseCache
* given parameters. * given parameters.
* @param cpu_pkt The miss that needs to be satisfied. * @param cpu_pkt The miss that needs to be satisfied.
* @param blk The block currently in the cache corresponding to * @param blk The block currently in the cache corresponding to
* cpu_pkt (NULL if none). * cpu_pkt (nullptr if none).
* @param needsWritable Indicates that the block must be writable * @param needsWritable Indicates that the block must be writable
* even if the request in cpu_pkt doesn't indicate that. * even if the request in cpu_pkt doesn't indicate that.
* @return A new Packet containing the request, or NULL if the * @return A new Packet containing the request, or nullptr if the
* current request in cpu_pkt should just be forwarded on. * current request in cpu_pkt should just be forwarded on.
*/ */
PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,

View file

@ -95,7 +95,7 @@ MSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
// an MSHR entry. If we do, set the downstreamPending // an MSHR entry. If we do, set the downstreamPending
// flag. Otherwise, do nothing. // flag. Otherwise, do nothing.
MSHR *mshr = pkt->findNextSenderState<MSHR>(); MSHR *mshr = pkt->findNextSenderState<MSHR>();
if (mshr != NULL) { if (mshr != nullptr) {
assert(!mshr->downstreamPending); assert(!mshr->downstreamPending);
mshr->downstreamPending = true; mshr->downstreamPending = true;
} else { } else {
@ -166,7 +166,7 @@ MSHR::TargetList::clearDownstreamPending()
// downstreamPending flag in all caches this packet has // downstreamPending flag in all caches this packet has
// passed through. // passed through.
MSHR *mshr = t.pkt->findNextSenderState<MSHR>(); MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
if (mshr != NULL) { if (mshr != nullptr) {
mshr->clearDownstreamPending(); mshr->clearDownstreamPending();
} }
} }
@ -491,7 +491,7 @@ MSHR::checkFunctional(PacketPtr pkt)
// For other requests, we iterate over the individual targets // For other requests, we iterate over the individual targets
// since that's where the actual data lies. // since that's where the actual data lies.
if (pkt->isPrint()) { if (pkt->isPrint()) {
pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL); pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
return false; return false;
} else { } else {
return (targets.checkFunctional(pkt) || return (targets.checkFunctional(pkt) ||

View file

@ -117,14 +117,14 @@ QueuedPrefetcher::getPacket()
if (pfq.empty()) { if (pfq.empty()) {
DPRINTF(HWPrefetch, "No hardware prefetches available.\n"); DPRINTF(HWPrefetch, "No hardware prefetches available.\n");
return NULL; return nullptr;
} }
PacketPtr pkt = pfq.begin()->pkt; PacketPtr pkt = pfq.begin()->pkt;
pfq.pop_front(); pfq.pop_front();
pfIssued++; pfIssued++;
assert(pkt != NULL); assert(pkt != nullptr);
DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr()); DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
return pkt; return pkt;
} }

View file

@ -206,7 +206,7 @@ class Queue : public Drainable
Entry* getNext() const Entry* getNext() const
{ {
if (readyList.empty() || readyList.front()->readyTime > curTick()) { if (readyList.empty() || readyList.front()->readyTime > curTick()) {
return NULL; return nullptr;
} }
return readyList.front(); return readyList.front();
} }

View file

@ -193,7 +193,7 @@ public:
/** /**
* Access block and update replacement data. May not succeed, in which case * Access block and update replacement data. May not succeed, in which case
* NULL pointer is returned. This has all the implications of a cache * nullptr is returned. This has all the implications of a cache
* access and should only be used as such. Returns the access latency as a * access and should only be used as such. Returns the access latency as a
* side effect. * side effect.
* @param addr The address to find. * @param addr The address to find.
@ -215,14 +215,14 @@ public:
// a hit. Sequential access with a miss doesn't access data. // a hit. Sequential access with a miss doesn't access data.
tagAccesses += allocAssoc; tagAccesses += allocAssoc;
if (sequentialAccess) { if (sequentialAccess) {
if (blk != NULL) { if (blk != nullptr) {
dataAccesses += 1; dataAccesses += 1;
} }
} else { } else {
dataAccesses += allocAssoc; dataAccesses += allocAssoc;
} }
if (blk != NULL) { if (blk != nullptr) {
if (blk->whenReady > curTick() if (blk->whenReady > curTick()
&& cache->ticksToCycles(blk->whenReady - curTick()) && cache->ticksToCycles(blk->whenReady - curTick())
> accessLatency) { > accessLatency) {
@ -253,7 +253,7 @@ public:
*/ */
CacheBlk* findVictim(Addr addr) override CacheBlk* findVictim(Addr addr) override
{ {
BlkType *blk = NULL; BlkType *blk = nullptr;
int set = extractSet(addr); int set = extractSet(addr);
// prefer to evict an invalid block // prefer to evict an invalid block

View file

@ -104,7 +104,7 @@ CacheSet<Blktype>::findBlk(Addr tag, bool is_secure, int& way_id) const
return blks[i]; return blks[i];
} }
} }
return NULL; return nullptr;
} }
template <class Blktype> template <class Blktype>

View file

@ -79,12 +79,12 @@ FALRU::FALRU(const Params *p)
head = &(blks[0]); head = &(blks[0]);
tail = &(blks[numBlocks-1]); tail = &(blks[numBlocks-1]);
head->prev = NULL; head->prev = nullptr;
head->next = &(blks[1]); head->next = &(blks[1]);
head->inCache = cacheMask; head->inCache = cacheMask;
tail->prev = &(blks[numBlocks-2]); tail->prev = &(blks[numBlocks-2]);
tail->next = NULL; tail->next = nullptr;
tail->inCache = 0; tail->inCache = 0;
unsigned index = (1 << 17) / blkSize; unsigned index = (1 << 17) / blkSize;
@ -159,7 +159,7 @@ FALRU::hashLookup(Addr addr) const
if (iter != tagHash.end()) { if (iter != tagHash.end()) {
return (*iter).second; return (*iter).second;
} }
return NULL; return nullptr;
} }
void void
@ -199,7 +199,7 @@ FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
moveToHead(blk); moveToHead(blk);
} }
} else { } else {
blk = NULL; blk = nullptr;
for (unsigned i = 0; i <= numCaches; ++i) { for (unsigned i = 0; i <= numCaches; ++i) {
misses[i]++; misses[i]++;
} }
@ -223,7 +223,7 @@ FALRU::findBlock(Addr addr, bool is_secure) const
if (blk && blk->isValid()) { if (blk && blk->isValid()) {
assert(blk->tag == blkAddr); assert(blk->tag == blkAddr);
} else { } else {
blk = NULL; blk = nullptr;
} }
return blk; return blk;
} }
@ -277,15 +277,15 @@ FALRU::moveToHead(FALRUBlk *blk)
blk->inCache = cacheMask; blk->inCache = cacheMask;
if (blk != head) { if (blk != head) {
if (blk == tail){ if (blk == tail){
assert(blk->next == NULL); assert(blk->next == nullptr);
tail = blk->prev; tail = blk->prev;
tail->next = NULL; tail->next = nullptr;
} else { } else {
blk->prev->next = blk->next; blk->prev->next = blk->next;
blk->next->prev = blk->prev; blk->next->prev = blk->prev;
} }
blk->next = head; blk->next = head;
blk->prev = NULL; blk->prev = nullptr;
head->prev = blk; head->prev = blk;
head = blk; head = blk;
} }

View file

@ -178,8 +178,8 @@ public:
/** /**
* Access block and update replacement data. May not succeed, in which * Access block and update replacement data. May not succeed, in which
* case NULL pointer is returned. This has all the implications of a cache * case nullptr pointer is returned. This has all the implications of a
* access and should only be used as such. * cache access and should only be used as such.
* Returns the access latency and inCache flags as a side effect. * Returns the access latency and inCache flags as a side effect.
* @param addr The address to look for. * @param addr The address to look for.
* @param is_secure True if the target memory space is secure. * @param is_secure True if the target memory space is secure.

View file

@ -59,7 +59,7 @@ LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int master_id)
{ {
CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat, master_id); CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat, master_id);
if (blk != NULL) { if (blk != nullptr) {
// move this block to head of the MRU list // move this block to head of the MRU list
sets[blk->set].moveToHead(blk); sets[blk->set].moveToHead(blk);
DPRINTF(CacheRepl, "set %x: moving blk %x (%s) to MRU\n", DPRINTF(CacheRepl, "set %x: moving blk %x (%s) to MRU\n",
@ -75,7 +75,7 @@ LRU::findVictim(Addr addr)
{ {
int set = extractSet(addr); int set = extractSet(addr);
// grab a replacement candidate // grab a replacement candidate
BlkType *blk = NULL; BlkType *blk = nullptr;
for (int i = assoc - 1; i >= 0; i--) { for (int i = assoc - 1; i >= 0; i--) {
BlkType *b = sets[set].blks[i]; BlkType *b = sets[set].blks[i];
if (b->way < allocAssoc) { if (b->way < allocAssoc) {

View file

@ -132,7 +132,7 @@ WriteQueueEntry::checkFunctional(PacketPtr pkt)
// entity. For other requests, we iterate over the individual // entity. For other requests, we iterate over the individual
// targets since that's where the actual data lies. // targets since that's where the actual data lies.
if (pkt->isPrint()) { if (pkt->isPrint()) {
pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL); pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
return false; return false;
} else { } else {
return targets.checkFunctional(pkt); return targets.checkFunctional(pkt);