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Merge zizzer:/z/m5/Bitkeeper/m5

Browse source 
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean

--HG--
extra : convert_revision : e3bce987a3c33d8c5da9a9ab0458f153a56ba73f
This commit is contained in:
Ron Dreslinski 2004-11-17 23:28:15 -05:00
parent 171ebf16be 60e88ba7ad
commit d68a22f40f
2 changed files with 43 additions and 14 deletions
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51
cpu/simple_cpu/simple_cpu.cc
View file

@ -103,7 +103,7 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
void SimpleCPU::CacheCompletionEvent::process()
{
cpu->processCacheCompletion();
cpu->processCacheCompletion(read);
}
const char *
@ -414,20 +414,24 @@ template <class T>
Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
Fault fault;
if (status() == DcacheMissStall) {
//Just do the functional access
fault = xc->read(memReq, data);
if (traceData) {
traceData->setAddr(addr);
if (fault == No_Fault)
traceData->setData(data);
}
return fault;
}
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault fault = xc->translateDataReadReq(memReq);
// do functional access
if (fault == No_Fault)
fault = xc->read(memReq, data);
if (traceData) {
traceData->setAddr(addr);
if (fault == No_Fault)
traceData->setData(data);
}
fault = xc->translateDataReadReq(memReq);
// if we have a cache, do cache access too
if (fault == No_Fault && dcacheInterface) {
@ -440,11 +444,25 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
cacheCompletionEvent.read = true;
memReq->completionEvent = &cacheCompletionEvent;
//May later want to pass the staticinst as well, so it can call
//it independantly
lastDcacheStall = curTick;
unscheduleTickEvent();
_status = DcacheMissStall;
}
else {
// do functional access
if (fault == No_Fault)
fault = xc->read(memReq, data);
if (traceData) {
traceData->setAddr(addr);
if (fault == No_Fault)
traceData->setData(data);
}
}
}
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
@ -525,6 +543,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
cacheCompletionEvent.read = false;
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
unscheduleTickEvent();
@ -596,7 +615,7 @@ Tick save_cycle = 0;
void
SimpleCPU::processCacheCompletion()
SimpleCPU::processCacheCompletion(bool read)
{
switch (status()) {
case IcacheMissStall:
@ -606,6 +625,9 @@ SimpleCPU::processCacheCompletion()
break;
case DcacheMissStall:
dcacheStallCycles += curTick - lastDcacheStall;
if (read) {
globalsi->execute(this,traceData);
}
_status = Running;
scheduleTickEvent(1);
break;
@ -729,6 +751,7 @@ SimpleCPU::tick()
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && icacheInterface->doEvents()) {
cacheCompletionEvent.read = false;
memReq->completionEvent = &cacheCompletionEvent;
lastIcacheStall = curTick;
unscheduleTickEvent();
@ -753,6 +776,8 @@ SimpleCPU::tick()
inst = htoa(inst);
StaticInstPtr<TheISA> si(inst);
globalsi = si;
traceData = Trace::getInstRecord(curTick, xc, this, si,
xc->regs.pc);

6
cpu/simple_cpu/simple_cpu.hh
View file

@ -184,6 +184,8 @@ class SimpleCPU : public BaseCPU
// Refcounted pointer to the one memory request.
MemReqPtr memReq;
StaticInstPtr<TheISA> globalsi;
class CacheCompletionEvent : public Event
{
private:
@ -192,6 +194,8 @@ class SimpleCPU : public BaseCPU
public:
CacheCompletionEvent(SimpleCPU *_cpu);
bool read;
virtual void process();
virtual const char *description();
};
@ -238,7 +242,7 @@ class SimpleCPU : public BaseCPU
Stats::Scalar<> dcacheStallCycles;
Counter lastDcacheStall;
void processCacheCompletion();
void processCacheCompletion(bool read);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);