* * *
mem: support for gpu-style RMWs in ruby This patch adds support for GPU-style read-modify-write (RMW) operations in ruby. Such atomic operations are traditionally executed at the memory controller (instead of through an L1 cache using cache-line locking). Currently, this patch works by propogating operation functors through the memory system.
This commit is contained in:
parent
34fb6b5e35
commit
d658b6e1cc
6 changed files with 122 additions and 39 deletions
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@ -200,6 +200,19 @@ typedef std::shared_ptr<FaultBase> Fault;
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constexpr decltype(nullptr) NoFault = nullptr;
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constexpr decltype(nullptr) NoFault = nullptr;
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#endif
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#endif
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struct AtomicOpFunctor
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{
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virtual void operator()(uint8_t *p) = 0;
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virtual ~AtomicOpFunctor() {}
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};
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template <class T>
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struct TypedAtomicOpFunctor : public AtomicOpFunctor
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{
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void operator()(uint8_t *p) { execute((T *)p); }
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virtual void execute(T * p) = 0;
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};
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enum ByteOrder {
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enum ByteOrder {
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BigEndianByteOrder,
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BigEndianByteOrder,
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LittleEndianByteOrder
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LittleEndianByteOrder
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@ -341,6 +341,12 @@ AbstractMemory::access(PacketPtr pkt)
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uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
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uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
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if (pkt->cmd == MemCmd::SwapReq) {
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if (pkt->cmd == MemCmd::SwapReq) {
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if (pkt->isAtomicOp()) {
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if (pmemAddr) {
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memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
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(*(pkt->getAtomicOp()))(hostAddr);
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}
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} else {
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std::vector<uint8_t> overwrite_val(pkt->getSize());
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std::vector<uint8_t> overwrite_val(pkt->getSize());
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uint64_t condition_val64;
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uint64_t condition_val64;
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uint32_t condition_val32;
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uint32_t condition_val32;
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@ -374,6 +380,7 @@ AbstractMemory::access(PacketPtr pkt)
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assert(!pkt->req->isInstFetch());
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Read/Write");
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TRACE_PACKET("Read/Write");
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numOther[pkt->req->masterId()]++;
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numOther[pkt->req->masterId()]++;
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}
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} else if (pkt->isRead()) {
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} else if (pkt->isRead()) {
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assert(!pkt->isWrite());
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assert(!pkt->isWrite());
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if (pkt->isLLSC()) {
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if (pkt->isLLSC()) {
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@ -660,6 +660,12 @@ class Packet : public Printable
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return _isSecure;
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return _isSecure;
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}
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}
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/**
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* Accessor function to atomic op.
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*/
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AtomicOpFunctor *getAtomicOp() const { return req->getAtomicOpFunctor(); }
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bool isAtomicOp() const { return req->isAtomic(); }
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/**
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/**
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* It has been determined that the SC packet should successfully update
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* It has been determined that the SC packet should successfully update
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* memory. Therefore, convert this SC packet to a normal write.
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* memory. Therefore, convert this SC packet to a normal write.
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@ -56,6 +56,7 @@ bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt);
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enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
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enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
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// Valid data
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// Valid data
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Read_Only, desc="block is Read Only (modulo functional writes)";
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Read_Only, desc="block is Read Only (modulo functional writes)";
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Write_Only, desc="block is Write Only";
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Read_Write, desc="block is Read/Write";
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Read_Write, desc="block is Read/Write";
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// Possibly Invalid data
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// Possibly Invalid data
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@ -144,7 +145,9 @@ enumeration(TransitionResult, desc="...") {
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enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
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enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
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LD, desc="Load";
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LD, desc="Load";
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ST, desc="Store";
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ST, desc="Store";
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ATOMIC, desc="Atomic Load/Store";
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ATOMIC, desc="Atomic Load/Store -- depricated. use ATOMIC_RETURN or ATOMIC_NO_RETURN";
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ATOMIC_RETURN, desc="Atomic Load/Store, return data";
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ATOMIC_NO_RETURN, desc="Atomic Load/Store, do not return data";
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IFETCH, desc="Instruction fetch";
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IFETCH, desc="Instruction fetch";
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IO, desc="I/O";
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IO, desc="I/O";
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REPLACEMENT, desc="Replacement";
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REPLACEMENT, desc="Replacement";
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@ -166,6 +169,8 @@ enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL
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Default, desc="Replace this with access_types passed to the DMA Ruby object";
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Default, desc="Replace this with access_types passed to the DMA Ruby object";
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LD, desc="Load";
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LD, desc="Load";
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ST, desc="Store";
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ST, desc="Store";
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ATOMIC, desc="Atomic Load/Store";
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REPLACEMENT, desc="Replacement";
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FLUSH, desc="Flush request type";
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FLUSH, desc="Flush request type";
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NULL, desc="Invalid request type";
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NULL, desc="Invalid request type";
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}
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}
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@ -126,6 +126,7 @@ structure(RubyRequest, desc="...", interface="Message", external="yes") {
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int Size, desc="size in bytes of access";
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int Size, desc="size in bytes of access";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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int contextId, desc="this goes away but must be replace with Nilay";
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int contextId, desc="this goes away but must be replace with Nilay";
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int wfid, desc="Writethrough wavefront";
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HSAScope scope, desc="HSA scope";
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HSAScope scope, desc="HSA scope";
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HSASegment segment, desc="HSA segment";
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HSASegment segment, desc="HSA segment";
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}
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}
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@ -160,6 +160,11 @@ class Request
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/** The request should be marked with RELEASE. */
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/** The request should be marked with RELEASE. */
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RELEASE = 0x00040000,
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RELEASE = 0x00040000,
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/** The request is an atomic that returns data. */
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ATOMIC_RETURN_OP = 0x40000000,
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/** The request is an atomic that does not return data. */
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ATOMIC_NO_RETURN_OP = 0x80000000,
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/** The request should be marked with KERNEL.
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/** The request should be marked with KERNEL.
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* Used to indicate the synchronization associated with a GPU kernel
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* Used to indicate the synchronization associated with a GPU kernel
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* launch or completion.
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* launch or completion.
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@ -345,6 +350,9 @@ class Request
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/** Sequence number of the instruction that creates the request */
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/** Sequence number of the instruction that creates the request */
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InstSeqNum _reqInstSeqNum;
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InstSeqNum _reqInstSeqNum;
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/** A pointer to an atomic operation */
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AtomicOpFunctor *atomicOpFunctor;
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public:
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public:
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/**
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/**
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@ -356,7 +364,8 @@ class Request
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{}
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{}
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
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@ -364,7 +373,8 @@ class Request
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_reqInstSeqNum(seq_num), translateDelta(0), accessDelta(0), depth(0)
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_reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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{
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setPhys(paddr, size, flags, mid, curTick());
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setPhys(paddr, size, flags, mid, curTick());
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setThreadContext(cid, tid);
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setThreadContext(cid, tid);
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@ -380,7 +390,8 @@ class Request
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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{
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setPhys(paddr, size, flags, mid, curTick());
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setPhys(paddr, size, flags, mid, curTick());
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}
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}
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@ -389,7 +400,8 @@ class Request
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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{
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setPhys(paddr, size, flags, mid, time);
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setPhys(paddr, size, flags, mid, time);
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}
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}
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@ -398,12 +410,12 @@ class Request
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Addr pc)
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Addr pc)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(pc),
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_reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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{
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setPhys(paddr, size, flags, mid, time);
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setPhys(paddr, size, flags, mid, time);
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privateFlags.set(VALID_PC);
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privateFlags.set(VALID_PC);
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_pc = pc;
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}
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}
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Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
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Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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_reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
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_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
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accessDelta(0), depth(0)
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{
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{
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setVirt(asid, vaddr, size, flags, mid, pc);
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setVirt(asid, vaddr, size, flags, mid, pc);
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setThreadContext(cid, tid);
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setThreadContext(cid, tid);
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}
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}
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~Request() {}
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Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
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int cid, ThreadID tid, AtomicOpFunctor *atomic_op)
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: atomicOpFunctor(atomic_op)
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{
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setVirt(asid, vaddr, size, flags, mid, pc);
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setThreadContext(cid, tid);
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}
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~Request()
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{
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if (hasAtomicOpFunctor()) {
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delete atomicOpFunctor;
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}
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}
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/**
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/**
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* Set up CPU and thread numbers.
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* Set up CPU and thread numbers.
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return _time;
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return _time;
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}
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}
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/**
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* Accessor for atomic-op functor.
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*/
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bool
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hasAtomicOpFunctor()
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{
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return atomicOpFunctor != NULL;
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}
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AtomicOpFunctor *
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getAtomicOpFunctor()
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{
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assert(atomicOpFunctor != NULL);
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return atomicOpFunctor;
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}
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/** Accessor for flags. */
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/** Accessor for flags. */
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Flags
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Flags
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getFlags()
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getFlags()
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@ -749,6 +791,15 @@ class Request
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bool isAcquire() const { return _flags.isSet(ACQUIRE); }
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bool isAcquire() const { return _flags.isSet(ACQUIRE); }
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bool isRelease() const { return _flags.isSet(RELEASE); }
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bool isRelease() const { return _flags.isSet(RELEASE); }
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bool isKernel() const { return _flags.isSet(KERNEL); }
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bool isKernel() const { return _flags.isSet(KERNEL); }
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bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
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bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
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bool
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isAtomic() const
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{
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return _flags.isSet(ATOMIC_RETURN_OP) ||
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_flags.isSet(ATOMIC_NO_RETURN_OP);
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}
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/**
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/**
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* Accessor functions for the memory space configuration flags and used by
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* Accessor functions for the memory space configuration flags and used by
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