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configs: use SimpleMemory when using ruby in se mode

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A recent changeset altered the default memory class to DRAMCtrl.  In se mode,
ruby uses the physical memory to check if a given address is within the bounds
of the physical memory.  SimpleMemory is enough for this.  Moreover,
SimpleMemory does not check whether it is connected or not, something which
DRAMCtrl does.
This commit is contained in:
Nilay Vaish 2014-04-01 11:17:46 -05:00
parent b884fcf412
commit d6542d7758
1 changed files with 5 additions and 4 deletions
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9
configs/example/se.py
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@ -157,8 +157,6 @@ else:
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.numThreads = numThreads CPUClass.numThreads = numThreads
MemClass = Simulation.setMemClass(options)
# Check -- do not allow SMT with multiple CPUs # Check -- do not allow SMT with multiple CPUs
if options.smt and options.num_cpus > 1: if options.smt and options.num_cpus > 1:
fatal("You cannot use SMT with multiple CPUs!") fatal("You cannot use SMT with multiple CPUs!")
@ -228,8 +226,10 @@ if options.ruby:
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1) sys.exit(1)
# Set the option for physmem so that it is not allocated any space # Use SimpleMemory with the null option since this memory is only used
system.physmem = MemClass(range=AddrRange(options.mem_size), # for determining which addresses are within the range of the memory.
# No space allocation is required.
system.physmem = SimpleMemory(range=AddrRange(options.mem_size),
null = True) null = True)
options.use_map = True options.use_map = True
Ruby.create_system(options, system) Ruby.create_system(options, system)
@ -253,6 +253,7 @@ if options.ruby:
system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave
else: else:
MemClass = Simulation.setMemClass(options)
system.membus = CoherentBus() system.membus = CoherentBus()
system.system_port = system.membus.slave system.system_port = system.membus.slave
CacheConfig.config_cache(options, system) CacheConfig.config_cache(options, system)