Remove sampler and serializer. Now they are handled through C++ interacting with Python.
src/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/sim/pseudo_inst.cc: Remove sampler. src/sim/sim_object.cc: Remove serializer. --HG-- extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008
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@ -89,7 +89,6 @@ base_sources = Split('''
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cpu/pc_event.cc
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cpu/pc_event.cc
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cpu/quiesce_event.cc
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cpu/quiesce_event.cc
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cpu/static_inst.cc
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cpu/static_inst.cc
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cpu/sampler/sampler.cc
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cpu/simple_thread.cc
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cpu/simple_thread.cc
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cpu/thread_state.cc
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cpu/thread_state.cc
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@ -41,7 +41,6 @@
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#include "cpu/cpuevent.hh"
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#include "cpu/cpuevent.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/profile.hh"
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#include "cpu/profile.hh"
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#include "cpu/sampler/sampler.hh"
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#include "sim/param.hh"
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#include "sim/param.hh"
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#include "sim/process.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_events.hh"
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@ -36,7 +36,6 @@
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#include "base/statistics.hh"
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "config/full_system.hh"
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#include "cpu/sampler/sampler.hh"
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#include "sim/eventq.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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#include "sim/sim_object.hh"
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#include "arch/isa_traits.hh"
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#include "arch/isa_traits.hh"
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@ -66,7 +66,6 @@ class ThreadContext;
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class MemInterface;
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class MemInterface;
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class Checkpoint;
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class Checkpoint;
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class Request;
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class Request;
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class Sampler;
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/**
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/**
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* CheckerCPU class. Dynamically verifies instructions as they are
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* CheckerCPU class. Dynamically verifies instructions as they are
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@ -374,7 +373,7 @@ class Checker : public CheckerCPU
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: CheckerCPU(p)
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: CheckerCPU(p)
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{ }
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{ }
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void switchOut(Sampler *s);
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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void takeOverFrom(BaseCPU *oldCPU);
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void verify(DynInstPtr &inst);
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void verify(DynInstPtr &inst);
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@ -293,7 +293,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
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template <class DynInstPtr>
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template <class DynInstPtr>
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void
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void
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Checker<DynInstPtr>::switchOut(Sampler *s)
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Checker<DynInstPtr>::switchOut()
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{
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{
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instList.clear();
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instList.clear();
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}
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}
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@ -714,9 +714,8 @@ FullO3CPU<Impl>::haltContext(int tid)
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template <class Impl>
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template <class Impl>
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void
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void
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FullO3CPU<Impl>::switchOut(Sampler *_sampler)
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FullO3CPU<Impl>::switchOut()
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{
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{
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sampler = _sampler;
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switchCount = 0;
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switchCount = 0;
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fetch.switchOut();
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fetch.switchOut();
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decode.switchOut();
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decode.switchOut();
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@ -745,12 +744,11 @@ FullO3CPU<Impl>::signalSwitched()
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#if USE_CHECKER
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#if USE_CHECKER
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if (checker)
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if (checker)
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checker->switchOut(sampler);
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checker->switchOut();
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#endif
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#endif
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if (tickEvent.scheduled())
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if (tickEvent.scheduled())
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tickEvent.squash();
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tickEvent.squash();
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sampler->signalSwitched();
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_status = SwitchedOut;
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_status = SwitchedOut;
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}
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}
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assert(switchCount <= 5);
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assert(switchCount <= 5);
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@ -271,7 +271,7 @@ class FullO3CPU : public BaseO3CPU
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virtual void syscall(int tid) { panic("Unimplemented!"); }
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virtual void syscall(int tid) { panic("Unimplemented!"); }
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/** Switches out this CPU. */
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/** Switches out this CPU. */
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void switchOut(Sampler *sampler);
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void switchOut();
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/** Signals to this CPU that a stage has completed switching out. */
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/** Signals to this CPU that a stage has completed switching out. */
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void signalSwitched();
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void signalSwitched();
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@ -550,9 +550,6 @@ class FullO3CPU : public BaseO3CPU
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/** Pointer to memory. */
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/** Pointer to memory. */
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MemObject *mem;
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MemObject *mem;
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/** Pointer to the sampler */
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Sampler *sampler;
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/** Counter of how many stages have completed switching out. */
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/** Counter of how many stages have completed switching out. */
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int switchCount;
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int switchCount;
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@ -40,8 +40,6 @@
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#include "mem/port.hh"
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#include "mem/port.hh"
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#include "sim/eventq.hh"
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#include "sim/eventq.hh"
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class Sampler;
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/**
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/**
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* DefaultFetch class handles both single threaded and SMT fetch. Its
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* DefaultFetch class handles both single threaded and SMT fetch. Its
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* width is specified by the parameters; each cycle it tries to fetch
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* width is specified by the parameters; each cycle it tries to fetch
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@ -55,7 +55,6 @@ class AlphaDTB;
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class PhysicalMemory;
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class PhysicalMemory;
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class MemoryController;
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class MemoryController;
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class Sampler;
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class RemoteGDB;
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class RemoteGDB;
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class GDBListener;
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class GDBListener;
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@ -356,12 +355,10 @@ class OzoneCPU : public BaseCPU
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int cpuId;
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int cpuId;
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void switchOut(Sampler *sampler);
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void switchOut();
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void signalSwitched();
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void signalSwitched();
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void takeOverFrom(BaseCPU *oldCPU);
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void takeOverFrom(BaseCPU *oldCPU);
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Sampler *sampler;
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int switchCount;
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int switchCount;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -244,9 +244,8 @@ OzoneCPU<Impl>::~OzoneCPU()
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template <class Impl>
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template <class Impl>
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void
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void
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OzoneCPU<Impl>::switchOut(Sampler *_sampler)
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OzoneCPU<Impl>::switchOut()
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{
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{
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sampler = _sampler;
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switchCount = 0;
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switchCount = 0;
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// Front end needs state from back end, so switch out the back end first.
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// Front end needs state from back end, so switch out the back end first.
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backEnd->switchOut();
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backEnd->switchOut();
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@ -262,13 +261,12 @@ OzoneCPU<Impl>::signalSwitched()
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frontEnd->doSwitchOut();
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frontEnd->doSwitchOut();
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#if USE_CHECKER
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#if USE_CHECKER
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if (checker)
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if (checker)
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checker->switchOut(sampler);
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checker->switchOut();
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#endif
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#endif
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_status = SwitchedOut;
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_status = SwitchedOut;
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if (tickEvent.scheduled())
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if (tickEvent.scheduled())
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tickEvent.squash();
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tickEvent.squash();
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sampler->signalSwitched();
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}
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}
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assert(switchCount <= 2);
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assert(switchCount <= 2);
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}
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}
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@ -41,7 +41,6 @@
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/profile.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/smt.hh"
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#include "cpu/smt.hh"
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@ -38,7 +38,6 @@
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/port.hh"
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// Static data storage
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// Static data storage
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TheISA::IntReg dataReg;
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TheISA::IntReg dataReg;
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// Pointer to the sampler that is telling us to switchover.
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// Used to signal the completion of the pipe drain and schedule
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// the next switchover
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Sampler *sampler;
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StaticInstPtr curStaticInst;
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StaticInstPtr curStaticInst;
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void checkForInterrupts();
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void checkForInterrupts();
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@ -52,8 +52,6 @@
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using namespace std;
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using namespace std;
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extern Sampler *SampCPU;
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using namespace Stats;
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using namespace Stats;
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using namespace TheISA;
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using namespace TheISA;
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void switchcpu(ThreadContext *tc)
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void switchcpu(ThreadContext *tc)
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{
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{
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if (SampCPU)
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SampCPU->switchCPUs();
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}
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}
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}
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}
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#include "base/misc.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "base/stats/events.hh"
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#include "base/stats/events.hh"
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#include "base/serializer.hh"
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#include "sim/host.hh"
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#include "sim/host.hh"
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#include "sim/sim_object.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "sim/stats.hh"
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