Remove sampler and serializer. Now they are handled through C++ interacting with Python.

src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
    Remove sampler.
src/sim/sim_object.cc:
    Remove serializer.

--HG--
extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008
This commit is contained in:
Kevin Lim 2006-07-05 21:14:36 -04:00
parent d8fd09cc15
commit d598061dd6
14 changed files with 8 additions and 36 deletions

View file

@ -89,7 +89,6 @@ base_sources = Split('''
cpu/pc_event.cc cpu/pc_event.cc
cpu/quiesce_event.cc cpu/quiesce_event.cc
cpu/static_inst.cc cpu/static_inst.cc
cpu/sampler/sampler.cc
cpu/simple_thread.cc cpu/simple_thread.cc
cpu/thread_state.cc cpu/thread_state.cc

View file

@ -41,7 +41,6 @@
#include "cpu/cpuevent.hh" #include "cpu/cpuevent.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "cpu/profile.hh" #include "cpu/profile.hh"
#include "cpu/sampler/sampler.hh"
#include "sim/param.hh" #include "sim/param.hh"
#include "sim/process.hh" #include "sim/process.hh"
#include "sim/sim_events.hh" #include "sim/sim_events.hh"

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@ -36,7 +36,6 @@
#include "base/statistics.hh" #include "base/statistics.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
#include "cpu/sampler/sampler.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "arch/isa_traits.hh" #include "arch/isa_traits.hh"

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@ -66,7 +66,6 @@ class ThreadContext;
class MemInterface; class MemInterface;
class Checkpoint; class Checkpoint;
class Request; class Request;
class Sampler;
/** /**
* CheckerCPU class. Dynamically verifies instructions as they are * CheckerCPU class. Dynamically verifies instructions as they are
@ -374,7 +373,7 @@ class Checker : public CheckerCPU
: CheckerCPU(p) : CheckerCPU(p)
{ } { }
void switchOut(Sampler *s); void switchOut();
void takeOverFrom(BaseCPU *oldCPU); void takeOverFrom(BaseCPU *oldCPU);
void verify(DynInstPtr &inst); void verify(DynInstPtr &inst);

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@ -293,7 +293,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
template <class DynInstPtr> template <class DynInstPtr>
void void
Checker<DynInstPtr>::switchOut(Sampler *s) Checker<DynInstPtr>::switchOut()
{ {
instList.clear(); instList.clear();
} }

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@ -714,9 +714,8 @@ FullO3CPU<Impl>::haltContext(int tid)
template <class Impl> template <class Impl>
void void
FullO3CPU<Impl>::switchOut(Sampler *_sampler) FullO3CPU<Impl>::switchOut()
{ {
sampler = _sampler;
switchCount = 0; switchCount = 0;
fetch.switchOut(); fetch.switchOut();
decode.switchOut(); decode.switchOut();
@ -745,12 +744,11 @@ FullO3CPU<Impl>::signalSwitched()
#if USE_CHECKER #if USE_CHECKER
if (checker) if (checker)
checker->switchOut(sampler); checker->switchOut();
#endif #endif
if (tickEvent.scheduled()) if (tickEvent.scheduled())
tickEvent.squash(); tickEvent.squash();
sampler->signalSwitched();
_status = SwitchedOut; _status = SwitchedOut;
} }
assert(switchCount <= 5); assert(switchCount <= 5);

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@ -271,7 +271,7 @@ class FullO3CPU : public BaseO3CPU
virtual void syscall(int tid) { panic("Unimplemented!"); } virtual void syscall(int tid) { panic("Unimplemented!"); }
/** Switches out this CPU. */ /** Switches out this CPU. */
void switchOut(Sampler *sampler); void switchOut();
/** Signals to this CPU that a stage has completed switching out. */ /** Signals to this CPU that a stage has completed switching out. */
void signalSwitched(); void signalSwitched();
@ -550,9 +550,6 @@ class FullO3CPU : public BaseO3CPU
/** Pointer to memory. */ /** Pointer to memory. */
MemObject *mem; MemObject *mem;
/** Pointer to the sampler */
Sampler *sampler;
/** Counter of how many stages have completed switching out. */ /** Counter of how many stages have completed switching out. */
int switchCount; int switchCount;

View file

@ -40,8 +40,6 @@
#include "mem/port.hh" #include "mem/port.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"
class Sampler;
/** /**
* DefaultFetch class handles both single threaded and SMT fetch. Its * DefaultFetch class handles both single threaded and SMT fetch. Its
* width is specified by the parameters; each cycle it tries to fetch * width is specified by the parameters; each cycle it tries to fetch

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@ -55,7 +55,6 @@ class AlphaDTB;
class PhysicalMemory; class PhysicalMemory;
class MemoryController; class MemoryController;
class Sampler;
class RemoteGDB; class RemoteGDB;
class GDBListener; class GDBListener;
@ -356,12 +355,10 @@ class OzoneCPU : public BaseCPU
int cpuId; int cpuId;
void switchOut(Sampler *sampler); void switchOut();
void signalSwitched(); void signalSwitched();
void takeOverFrom(BaseCPU *oldCPU); void takeOverFrom(BaseCPU *oldCPU);
Sampler *sampler;
int switchCount; int switchCount;
#if FULL_SYSTEM #if FULL_SYSTEM

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@ -244,9 +244,8 @@ OzoneCPU<Impl>::~OzoneCPU()
template <class Impl> template <class Impl>
void void
OzoneCPU<Impl>::switchOut(Sampler *_sampler) OzoneCPU<Impl>::switchOut()
{ {
sampler = _sampler;
switchCount = 0; switchCount = 0;
// Front end needs state from back end, so switch out the back end first. // Front end needs state from back end, so switch out the back end first.
backEnd->switchOut(); backEnd->switchOut();
@ -262,13 +261,12 @@ OzoneCPU<Impl>::signalSwitched()
frontEnd->doSwitchOut(); frontEnd->doSwitchOut();
#if USE_CHECKER #if USE_CHECKER
if (checker) if (checker)
checker->switchOut(sampler); checker->switchOut();
#endif #endif
_status = SwitchedOut; _status = SwitchedOut;
if (tickEvent.scheduled()) if (tickEvent.scheduled())
tickEvent.squash(); tickEvent.squash();
sampler->signalSwitched();
} }
assert(switchCount <= 2); assert(switchCount <= 2);
} }

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@ -41,7 +41,6 @@
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "cpu/profile.hh" #include "cpu/profile.hh"
#include "cpu/sampler/sampler.hh"
#include "cpu/simple/base.hh" #include "cpu/simple/base.hh"
#include "cpu/simple_thread.hh" #include "cpu/simple_thread.hh"
#include "cpu/smt.hh" #include "cpu/smt.hh"

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@ -38,7 +38,6 @@
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/simple_thread.hh" #include "cpu/simple_thread.hh"
#include "cpu/pc_event.hh" #include "cpu/pc_event.hh"
#include "cpu/sampler/sampler.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/port.hh" #include "mem/port.hh"
@ -128,11 +127,6 @@ class BaseSimpleCPU : public BaseCPU
// Static data storage // Static data storage
TheISA::IntReg dataReg; TheISA::IntReg dataReg;
// Pointer to the sampler that is telling us to switchover.
// Used to signal the completion of the pipe drain and schedule
// the next switchover
Sampler *sampler;
StaticInstPtr curStaticInst; StaticInstPtr curStaticInst;
void checkForInterrupts(); void checkForInterrupts();

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@ -52,8 +52,6 @@
using namespace std; using namespace std;
extern Sampler *SampCPU;
using namespace Stats; using namespace Stats;
using namespace TheISA; using namespace TheISA;
@ -280,7 +278,5 @@ namespace AlphaPseudo
void switchcpu(ThreadContext *tc) void switchcpu(ThreadContext *tc)
{ {
if (SampCPU)
SampCPU->switchCPUs();
} }
} }

View file

@ -37,7 +37,6 @@
#include "base/misc.hh" #include "base/misc.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "base/stats/events.hh" #include "base/stats/events.hh"
#include "base/serializer.hh"
#include "sim/host.hh" #include "sim/host.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "sim/stats.hh" #include "sim/stats.hh"