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X86: Take advantage of new PCState syntax.

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This commit is contained in:
Gabe Black 2010-12-08 00:27:23 -08:00
parent 4c9b023a7a
commit d3e021820e
4 changed files with 14 additions and 25 deletions
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2
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -199,7 +199,7 @@
#endif
0x54: m5panic({{
panic("M5 panic instruction called at pc = %#x.\n",
xc->pcState().pc());
RIP);
}}, IsNonSpeculative);
0x55: m5reserved1({{
warn("M5 reserved opcode 1 ignored.\n");

13
src/arch/x86/isa/microops/regop.isa
View file

@ -944,12 +944,8 @@ let {{
code = 'DoubleBits = psrc1 ^ op2;'
class Wrip(WrRegOp, CondRegOp):
code = '''
X86ISA::PCState pc = PCS;
pc.npc(psrc1 + sop2 + CSBase);
PCS = pc;
'''
else_code = "PCS = PCS;"
code = 'NRIP = psrc1 + sop2 + CSBase;'
else_code = "NRIP = NRIP;"
class Wruflags(WrRegOp):
code = 'ccFlagBits = psrc1 ^ op2'
@ -965,10 +961,7 @@ let {{
'''
class Rdip(RdRegOp):
code = '''
X86ISA::PCState pc = PCS;
DestReg = pc.npc() - CSBase;
'''
code = 'DestReg = NRIP - CSBase;'
class Ruflags(RdRegOp):
code = 'DestReg = ccFlagBits'

16
src/arch/x86/isa/microops/seqop.isa
View file

@ -169,23 +169,15 @@ let {{
return super(Eret, self).getAllocator(microFlags)
iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
{"code": '''
X86ISA::PCState pc = PCS;
pc.nupc(target);
PCS = pc;
''',
"else_code": "PCS = PCS",
{"code": "nuIP = target;",
"else_code": "nuIP = nuIP;",
"cond_test": "checkCondition(ccFlagBits, cc)"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
{"code": '''
X86ISA::PCState pc = PCS;
pc.nupc(target);
PCS = pc;
''',
"else_code": "PCS = PCS",
{"code": "nuIP = target;",
"else_code": "nuIP = nuIP;",
"cond_test": "true"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)

6
src/arch/x86/isa/operands.isa
View file

@ -97,7 +97,11 @@ def operands {{
'FpSrcReg2': floatReg('src2', 21),
'FpDestReg': floatReg('dest', 22),
'FpData': floatReg('data', 23),
'PCS': ('PCState', 'udw', None,
'RIP': ('PCState', 'uqw', 'pc',
(None, None, 'IsControl'), 50),
'NRIP': ('PCState', 'uqw', 'npc',
(None, None, 'IsControl'), 50),
'nuIP': ('PCState', 'uqw', 'nupc',
(None, None, 'IsControl'), 50),
# This holds the condition code portion of the flag register. The
# nccFlagBits version holds the rest.