X86: Take advantage of new PCState syntax.
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@ -198,8 +198,8 @@
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}}, IsNonSpeculative);
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}}, IsNonSpeculative);
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#endif
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#endif
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0x54: m5panic({{
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0x54: m5panic({{
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panic("M5 panic instruction called at pc=%#x.\n",
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panic("M5 panic instruction called at pc = %#x.\n",
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xc->pcState().pc());
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RIP);
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}}, IsNonSpeculative);
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}}, IsNonSpeculative);
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0x55: m5reserved1({{
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0x55: m5reserved1({{
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warn("M5 reserved opcode 1 ignored.\n");
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warn("M5 reserved opcode 1 ignored.\n");
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@ -944,12 +944,8 @@ let {{
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code = 'DoubleBits = psrc1 ^ op2;'
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code = 'DoubleBits = psrc1 ^ op2;'
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class Wrip(WrRegOp, CondRegOp):
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class Wrip(WrRegOp, CondRegOp):
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code = '''
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code = 'NRIP = psrc1 + sop2 + CSBase;'
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X86ISA::PCState pc = PCS;
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else_code = "NRIP = NRIP;"
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pc.npc(psrc1 + sop2 + CSBase);
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PCS = pc;
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'''
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else_code = "PCS = PCS;"
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class Wruflags(WrRegOp):
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class Wruflags(WrRegOp):
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code = 'ccFlagBits = psrc1 ^ op2'
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code = 'ccFlagBits = psrc1 ^ op2'
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@ -965,10 +961,7 @@ let {{
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'''
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'''
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class Rdip(RdRegOp):
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class Rdip(RdRegOp):
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code = '''
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code = 'DestReg = NRIP - CSBase;'
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X86ISA::PCState pc = PCS;
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DestReg = pc.npc() - CSBase;
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'''
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class Ruflags(RdRegOp):
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class Ruflags(RdRegOp):
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code = 'DestReg = ccFlagBits'
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code = 'DestReg = ccFlagBits'
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@ -169,23 +169,15 @@ let {{
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return super(Eret, self).getAllocator(microFlags)
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return super(Eret, self).getAllocator(microFlags)
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iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
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iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
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{"code": '''
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{"code": "nuIP = target;",
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X86ISA::PCState pc = PCS;
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"else_code": "nuIP = nuIP;",
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pc.nupc(target);
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PCS = pc;
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''',
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"else_code": "PCS = PCS",
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"cond_test": "checkCondition(ccFlagBits, cc)"})
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"cond_test": "checkCondition(ccFlagBits, cc)"})
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exec_output += SeqOpExecute.subst(iop)
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exec_output += SeqOpExecute.subst(iop)
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header_output += SeqOpDeclare.subst(iop)
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header_output += SeqOpDeclare.subst(iop)
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decoder_output += SeqOpConstructor.subst(iop)
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decoder_output += SeqOpConstructor.subst(iop)
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iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
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iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
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{"code": '''
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{"code": "nuIP = target;",
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X86ISA::PCState pc = PCS;
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"else_code": "nuIP = nuIP;",
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pc.nupc(target);
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PCS = pc;
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''',
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"else_code": "PCS = PCS",
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"cond_test": "true"})
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"cond_test": "true"})
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exec_output += SeqOpExecute.subst(iop)
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exec_output += SeqOpExecute.subst(iop)
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header_output += SeqOpDeclare.subst(iop)
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header_output += SeqOpDeclare.subst(iop)
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@ -97,7 +97,11 @@ def operands {{
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'FpSrcReg2': floatReg('src2', 21),
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'FpSrcReg2': floatReg('src2', 21),
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'FpDestReg': floatReg('dest', 22),
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'FpDestReg': floatReg('dest', 22),
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'FpData': floatReg('data', 23),
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'FpData': floatReg('data', 23),
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'PCS': ('PCState', 'udw', None,
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'RIP': ('PCState', 'uqw', 'pc',
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(None, None, 'IsControl'), 50),
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'NRIP': ('PCState', 'uqw', 'npc',
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(None, None, 'IsControl'), 50),
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'nuIP': ('PCState', 'uqw', 'nupc',
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(None, None, 'IsControl'), 50),
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(None, None, 'IsControl'), 50),
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# This holds the condition code portion of the flag register. The
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# This holds the condition code portion of the flag register. The
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# nccFlagBits version holds the rest.
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# nccFlagBits version holds the rest.
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