sim,kvm,arm: fix typos

Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/kvm/gic.hh

@@ -65,7 +65,7 @@ class KvmKernelGicV2
      * @param vm KVM VM representing this system
      * @param cpu_addr GIC CPU interface base address
      * @param dist_addr GIC distributor base address
-     * @param it_liens Number of interrupt lines to support
+     * @param it_lines Number of interrupt lines to support
      */
     KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr,
                    unsigned it_lines);

src/dev/arm/gic_pl390.cc

@@ -542,7 +542,7 @@ Pl390::writeCpu(PacketPtr pkt)
       case GICC_EOIR:
         iar = pkt->get<uint32_t>();
         if (iar.ack_id < SGI_MAX) {
-            // Clear out the bit that corrseponds to the cleared int
+            // Clear out the bit that corresponds to the cleared int
             uint64_t clr_int = ULL(1) << (ctx + 8 * iar.cpu_id);
             if (!(cpuSgiActive[iar.ack_id] & clr_int) &&
                 !(cpuSgiActiveExt[ctx] & (1 << iar.ack_id)))
@@ -709,7 +709,7 @@ Pl390::updateIntState(int hint)
                    DPRINTF(GIC, "Checking for interrupt# %d \n",int_nm);
                     /* Set current pending int as highest int for current cpu
                        if the interrupt's priority higher than current priority
-                       and if currrent cpu is the target (for mp configs only)
+                       and if current cpu is the target (for mp configs only)
                      */
                     if ((bits(getIntEnabled(cpu, x), y)
                         &bits(getPendingInt(cpu, x), y)) &&
@@ -775,7 +775,7 @@ Pl390::updateRunPri()
 void
 Pl390::sendInt(uint32_t num)
 {
-    DPRINTF(Interrupt, "Received Interupt number %d,  cpuTarget %#x: \n",
+    DPRINTF(Interrupt, "Received Interrupt number %d,  cpuTarget %#x: \n",
             num, cpuTarget[num]);
     if ((cpuTarget[num] & (cpuTarget[num] - 1)) && !gem5ExtensionsEnabled)
         panic("Multiple targets for peripheral interrupts is not supported\n");

src/dev/arm/gic_pl390.hh

@@ -88,7 +88,7 @@ class Pl390 : public BaseGic
         GICC_BPR   = 0x08, // binary point register
         GICC_IAR   = 0x0C, // interrupt ack register
         GICC_EOIR  = 0x10, // end of interrupt
-        GICC_RPR   = 0x14, // runing priority
+        GICC_RPR   = 0x14, // running priority
         GICC_HPPIR = 0x18, // highest pending interrupt
         GICC_ABPR  = 0x1c, // aliased binary point
         GICC_IIDR  = 0xfc, // cpu interface id register
@@ -391,22 +391,22 @@ class Pl390 : public BaseGic
     void unserialize(CheckpointIn &cp) override;
 
   protected:
-    /** Handle a read to the distributor poriton of the GIC
+    /** Handle a read to the distributor portion of the GIC
      * @param pkt packet to respond to
      */
     Tick readDistributor(PacketPtr pkt);
 
-    /** Handle a read to the cpu poriton of the GIC
+    /** Handle a read to the cpu portion of the GIC
      * @param pkt packet to respond to
      */
     Tick readCpu(PacketPtr pkt);
 
-    /** Handle a write to the distributor poriton of the GIC
+    /** Handle a write to the distributor portion of the GIC
      * @param pkt packet to respond to
      */
     Tick writeDistributor(PacketPtr pkt);
 
-    /** Handle a write to the cpu poriton of the GIC
+    /** Handle a write to the cpu portion of the GIC
      * @param pkt packet to respond to
      */
     Tick writeCpu(PacketPtr pkt);

src/sim/System.py

@@ -60,7 +60,7 @@ class System(MemObject):
 
     # When reserving memory on the host, we have the option of
     # reserving swap space or not (by passing MAP_NORESERVE to
-    # mmap). By enabling this flag, we accomodate cases where a large
+    # mmap). By enabling this flag, we accommodate cases where a large
     # (but sparse) memory is simulated.
     mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
                                           "without reserving swap")

src/sim/system.cc

@@ -159,7 +159,7 @@ System::System(Params *p)
         }
     }
 
-    // increment the number of running systms
+    // increment the number of running systems
     numSystemsRunning++;
 
     // Set back pointers to the system in all memories

src/sim/system.hh

@@ -224,7 +224,7 @@ class System : public MemObject
     /** Object pointer for the kernel code */
     ObjectFile *kernel;
 
-    /** Begining of kernel code */
+    /** Beginning of kernel code */
     Addr kernelStart;
 
     /** End of kernel code */
@@ -242,8 +242,8 @@ class System : public MemObject
     Addr loadAddrMask;
 
     /** Offset that should be used for binary/symbol loading.
-     * This further allows more flexibily than the loadAddrMask allows alone in
+     * This further allows more flexibility than the loadAddrMask allows alone
-     * loading kernels and similar. The loadAddrOffset is applied after the
+     * in loading kernels and similar. The loadAddrOffset is applied after the
      * loadAddrMask.
      */
     Addr loadAddrOffset;
@@ -278,7 +278,7 @@ class System : public MemObject
     Addr getPageBytes() const { return TheISA::PageBytes; }
 
     /**
-     * Get the number of bits worth of in-page adress for the ISA.
+     * Get the number of bits worth of in-page address for the ISA.
      */
     Addr getPageShift() const { return TheISA::PageShift; }
 
@@ -300,7 +300,7 @@ class System : public MemObject
     uint32_t numWorkIds;
     std::vector<bool> activeCpus;
 
-    /** This array is a per-sytem list of all devices capable of issuing a
+    /** This array is a per-system list of all devices capable of issuing a
      * memory system request and an associated string for each master id.
      * It's used to uniquely id any master in the system by name for things
      * like cache statistics.
@@ -314,8 +314,8 @@ class System : public MemObject
     /** Request an id used to create a request object in the system. All objects
      * that intend to issues requests into the memory system must request an id
      * in the init() phase of startup. All master ids must be fixed by the
-     * regStats() phase that immediately preceeds it. This allows objects in the
+     * regStats() phase that immediately precedes it. This allows objects in
-     * memory system to understand how many masters may exist and
+     * the memory system to understand how many masters may exist and
      * appropriately name the bins of their per-master stats before the stats
      * are finalized
      */
@@ -490,19 +490,19 @@ class System : public MemObject
   public:
 
     /**
-     * Returns the addess the kernel starts at.
+     * Returns the address the kernel starts at.
      * @return address the kernel starts at
      */
     Addr getKernelStart() const { return kernelStart; }
 
     /**
-     * Returns the addess the kernel ends at.
+     * Returns the address the kernel ends at.
      * @return address the kernel ends at
      */
     Addr getKernelEnd() const { return kernelEnd; }
 
     /**
-     * Returns the addess the entry point to the kernel code.
+     * Returns the address the entry point to the kernel code.
      * @return entry point of the kernel code
      */
     Addr getKernelEntry() const { return kernelEntry; }
@@ -544,7 +544,7 @@ class System : public MemObject
 
     /**
      * If needed, serialize additional symbol table entries for a
-     * specific subclass of this sytem. Currently this is used by
+     * specific subclass of this system. Currently this is used by
      * Alpha and MIPS.
      *
      * @param os stream to serialize to