Rename cycles() function to ticks()
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
This commit is contained in:
parent
887cd6a273
commit
d325f49b70
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@ -304,7 +304,7 @@ MiscRegFile::scheduleCP0Update(int delay)
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//schedule UPDATE
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//schedule UPDATE
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CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
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CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
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cp0_event->schedule(curTick + cpu->cycles(delay));
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cp0_event->schedule(curTick + cpu->ticks(delay));
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}
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}
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}
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}
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@ -364,9 +364,9 @@ void
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MiscRegFile::CP0Event::scheduleEvent(int delay)
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MiscRegFile::CP0Event::scheduleEvent(int delay)
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{
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{
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if (squashed())
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if (squashed())
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reschedule(curTick + cpu->cycles(delay));
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reschedule(curTick + cpu->ticks(delay));
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else if (!scheduled())
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else if (!scheduled())
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schedule(curTick + cpu->cycles(delay));
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schedule(curTick + cpu->ticks(delay));
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}
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}
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void
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void
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@ -1033,7 +1033,7 @@ doMmuReadError:
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(uint32_t)asi, va);
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(uint32_t)asi, va);
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}
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}
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pkt->makeAtomicResponse();
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pkt->makeAtomicResponse();
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return tc->getCpuPtr()->cycles(1);
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return tc->getCpuPtr()->ticks(1);
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}
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}
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Tick
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Tick
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@ -1280,7 +1280,7 @@ doMmuWriteError:
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(uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
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(uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
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}
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}
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pkt->makeAtomicResponse();
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pkt->makeAtomicResponse();
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return tc->getCpuPtr()->cycles(1);
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return tc->getCpuPtr()->ticks(1);
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}
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}
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#endif
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#endif
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@ -85,7 +85,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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if (!(tick_cmpr & ~mask(63)) && time > 0) {
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if (!(tick_cmpr & ~mask(63)) && time > 0) {
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if (tickCompare->scheduled())
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if (tickCompare->scheduled())
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tickCompare->deschedule();
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tickCompare->deschedule();
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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tickCompare->schedule(time * tc->getCpuPtr()->ticks(1));
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}
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}
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panic("writing to TICK compare register %#X\n", val);
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panic("writing to TICK compare register %#X\n", val);
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break;
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break;
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@ -101,7 +101,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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if (!(stick_cmpr & ~mask(63)) && time > 0) {
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if (!(stick_cmpr & ~mask(63)) && time > 0) {
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if (sTickCompare->scheduled())
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if (sTickCompare->scheduled())
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sTickCompare->deschedule();
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sTickCompare->deschedule();
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
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sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick);
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}
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}
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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break;
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break;
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@ -171,7 +171,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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if (!(hstick_cmpr & ~mask(63)) && time > 0) {
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if (!(hstick_cmpr & ~mask(63)) && time > 0) {
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if (hSTickCompare->scheduled())
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if (hSTickCompare->scheduled())
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hSTickCompare->deschedule();
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hSTickCompare->deschedule();
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hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
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hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1));
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}
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}
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DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
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DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
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break;
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break;
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@ -315,7 +315,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
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setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
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setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
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}
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}
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} else
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} else
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sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
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sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
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}
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}
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void
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void
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@ -341,6 +341,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
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}
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}
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// Need to do something to cause interrupt to happen here !!! @todo
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// Need to do something to cause interrupt to happen here !!! @todo
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} else
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} else
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hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
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hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
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}
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}
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@ -95,13 +95,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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Tick
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Tick
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DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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{
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{
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return tc->getCpuPtr()->cycles(1);
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return tc->getCpuPtr()->ticks(1);
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}
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}
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Tick
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Tick
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DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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{
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{
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return tc->getCpuPtr()->cycles(1);
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return tc->getCpuPtr()->ticks(1);
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}
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}
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#endif
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#endif
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@ -74,7 +74,7 @@ CPUProgressEvent::process()
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{
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{
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Counter temp = cpu->totalInstructions();
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Counter temp = cpu->totalInstructions();
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#ifndef NDEBUG
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#ifndef NDEBUG
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double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
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double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1));
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DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
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DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
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cpu->name(), temp - lastNumInst, ipc);
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cpu->name(), temp - lastNumInst, ipc);
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@ -223,7 +223,7 @@ BaseCPU::startup()
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if (params->progress_interval) {
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if (params->progress_interval) {
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new CPUProgressEvent(&mainEventQueue,
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new CPUProgressEvent(&mainEventQueue,
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cycles(params->progress_interval),
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ticks(params->progress_interval),
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this);
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this);
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}
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}
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}
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}
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@ -82,7 +82,7 @@ class BaseCPU : public MemObject
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public:
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public:
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// Tick currentTick;
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// Tick currentTick;
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick cycles(int numCycles) const { return clock * numCycles; }
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inline Tick ticks(int numCycles) const { return clock * numCycles; }
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inline Tick curCycle() const { return curTick / clock; }
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inline Tick curCycle() const { return curTick / clock; }
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inline Tick tickToCycles(Tick val) const { return val / clock; }
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inline Tick tickToCycles(Tick val) const { return val / clock; }
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// @todo remove me after debugging with legion done
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// @todo remove me after debugging with legion done
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@ -270,7 +270,7 @@ void
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MemTest::tick()
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MemTest::tick()
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{
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{
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if (!tickEvent.scheduled())
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if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + cycles(1));
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tickEvent.schedule(curTick + ticks(1));
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if (++noResponseCycles >= 500000) {
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if (++noResponseCycles >= 500000) {
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cerr << name() << ": deadlocked at cycle " << curTick << endl;
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cerr << name() << ": deadlocked at cycle " << curTick << endl;
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@ -55,7 +55,7 @@ class MemTest : public MemObject
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// register statistics
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// register statistics
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virtual void regStats();
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virtual void regStats();
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inline Tick cycles(int numCycles) const { return numCycles; }
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inline Tick ticks(int numCycles) const { return numCycles; }
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// main simulation loop (one cycle)
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// main simulation loop (one cycle)
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void tick();
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void tick();
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@ -325,7 +325,7 @@ DefaultCommit<Impl>::initStage()
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cpu->activateStage(O3CPU::CommitIdx);
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cpu->activateStage(O3CPU::CommitIdx);
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cpu->activityThisCycle();
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cpu->activityThisCycle();
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trapLatency = cpu->cycles(trapLatency);
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trapLatency = cpu->ticks(trapLatency);
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}
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}
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template <class Impl>
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template <class Impl>
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@ -464,7 +464,7 @@ FullO3CPU<Impl>::tick()
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lastRunningCycle = curTick;
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lastRunningCycle = curTick;
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timesIdled++;
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timesIdled++;
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} else {
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} else {
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tickEvent.schedule(nextCycle(curTick + cycles(1)));
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tickEvent.schedule(nextCycle(curTick + ticks(1)));
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DPRINTF(O3CPU, "Scheduling next tick!\n");
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DPRINTF(O3CPU, "Scheduling next tick!\n");
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}
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}
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}
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}
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@ -558,7 +558,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
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// Needs to set each stage to running as well.
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// Needs to set each stage to running as well.
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if (delay){
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if (delay){
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DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
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DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
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"on cycle %d\n", tid, curTick + cycles(delay));
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"on cycle %d\n", tid, curTick + ticks(delay));
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scheduleActivateThreadEvent(tid, delay);
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scheduleActivateThreadEvent(tid, delay);
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} else {
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} else {
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activateThread(tid);
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activateThread(tid);
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@ -585,7 +585,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
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// Schedule removal of thread data from CPU
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// Schedule removal of thread data from CPU
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if (delay){
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if (delay){
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DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
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DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
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"on cycle %d\n", tid, curTick + cycles(delay));
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"on cycle %d\n", tid, curTick + ticks(delay));
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scheduleDeallocateContextEvent(tid, remove, delay);
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scheduleDeallocateContextEvent(tid, remove, delay);
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return false;
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return false;
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} else {
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} else {
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@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU
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void scheduleTickEvent(int delay)
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void scheduleTickEvent(int delay)
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{
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{
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if (tickEvent.squashed())
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if (tickEvent.squashed())
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tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
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tickEvent.reschedule(nextCycle(curTick + ticks(delay)));
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else if (!tickEvent.scheduled())
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else if (!tickEvent.scheduled())
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tickEvent.schedule(nextCycle(curTick + cycles(delay)));
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tickEvent.schedule(nextCycle(curTick + ticks(delay)));
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}
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}
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/** Unschedule tick event, regardless of its current state. */
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/** Unschedule tick event, regardless of its current state. */
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@ -187,10 +187,10 @@ class FullO3CPU : public BaseO3CPU
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// Schedule thread to activate, regardless of its current state.
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// Schedule thread to activate, regardless of its current state.
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if (activateThreadEvent[tid].squashed())
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if (activateThreadEvent[tid].squashed())
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activateThreadEvent[tid].
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activateThreadEvent[tid].
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reschedule(nextCycle(curTick + cycles(delay)));
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reschedule(nextCycle(curTick + ticks(delay)));
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else if (!activateThreadEvent[tid].scheduled())
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else if (!activateThreadEvent[tid].scheduled())
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activateThreadEvent[tid].
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activateThreadEvent[tid].
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schedule(nextCycle(curTick + cycles(delay)));
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schedule(nextCycle(curTick + ticks(delay)));
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}
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}
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/** Unschedule actiavte thread event, regardless of its current state. */
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/** Unschedule actiavte thread event, regardless of its current state. */
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@ -238,10 +238,10 @@ class FullO3CPU : public BaseO3CPU
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// Schedule thread to activate, regardless of its current state.
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// Schedule thread to activate, regardless of its current state.
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if (deallocateContextEvent[tid].squashed())
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if (deallocateContextEvent[tid].squashed())
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deallocateContextEvent[tid].
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deallocateContextEvent[tid].
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reschedule(nextCycle(curTick + cycles(delay)));
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reschedule(nextCycle(curTick + ticks(delay)));
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else if (!deallocateContextEvent[tid].scheduled())
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else if (!deallocateContextEvent[tid].scheduled())
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deallocateContextEvent[tid].
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deallocateContextEvent[tid].
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schedule(nextCycle(curTick + cycles(delay)));
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schedule(nextCycle(curTick + ticks(delay)));
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}
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}
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/** Unschedule thread deallocation in CPU */
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/** Unschedule thread deallocation in CPU */
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@ -752,7 +752,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
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FUCompletion *execution = new FUCompletion(issuing_inst,
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FUCompletion *execution = new FUCompletion(issuing_inst,
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idx, this);
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idx, this);
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execution->schedule(curTick + cpu->cycles(issue_latency - 1));
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execution->schedule(curTick + cpu->ticks(issue_latency - 1));
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// @todo: Enforce that issue_latency == 1 or op_latency
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// @todo: Enforce that issue_latency == 1 or op_latency
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if (issue_latency > 1) {
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if (issue_latency > 1) {
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@ -315,9 +315,9 @@ class OzoneCPU : public BaseCPU
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void scheduleTickEvent(int delay)
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void scheduleTickEvent(int delay)
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{
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{
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if (tickEvent.squashed())
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + cycles(delay));
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tickEvent.reschedule(curTick + ticks(delay));
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else if (!tickEvent.scheduled())
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + cycles(delay));
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tickEvent.schedule(curTick + ticks(delay));
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}
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}
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/// Unschedule tick event, regardless of its current state.
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/// Unschedule tick event, regardless of its current state.
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@ -613,7 +613,7 @@ OzoneCPU<Impl>::tick()
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comInstEventQueue[0]->serviceEvents(numInst);
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comInstEventQueue[0]->serviceEvents(numInst);
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if (!tickEvent.scheduled() && _status == Running)
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if (!tickEvent.scheduled() && _status == Running)
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tickEvent.schedule(curTick + cycles(1));
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tickEvent.schedule(curTick + ticks(1));
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}
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}
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template <class Impl>
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template <class Impl>
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@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency)
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TrapEvent *trap = new TrapEvent(this);
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TrapEvent *trap = new TrapEvent(this);
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trap->schedule(curTick + cpu->cycles(latency));
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trap->schedule(curTick + cpu->ticks(latency));
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thread->trapPending = true;
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thread->trapPending = true;
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}
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}
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@ -254,7 +254,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
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notIdleFraction++;
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notIdleFraction++;
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//Make sure ticks are still on multiples of cycles
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//Make sure ticks are still on multiples of cycles
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tickEvent.schedule(nextCycle(curTick + cycles(delay)));
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tickEvent.schedule(nextCycle(curTick + ticks(delay)));
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_status = Running;
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_status = Running;
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}
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}
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@ -584,7 +584,7 @@ AtomicSimpleCPU::tick()
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{
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{
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DPRINTF(SimpleCPU, "Tick\n");
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DPRINTF(SimpleCPU, "Tick\n");
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Tick latency = cycles(1); // instruction takes one cycle by default
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Tick latency = ticks(1); // instruction takes one cycle by default
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for (int i = 0; i < width; ++i) {
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for (int i = 0; i < width; ++i) {
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numCycles++;
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numCycles++;
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@ -642,14 +642,14 @@ AtomicSimpleCPU::tick()
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if (simulate_stalls) {
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if (simulate_stalls) {
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Tick icache_stall =
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Tick icache_stall =
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icache_access ? icache_latency - cycles(1) : 0;
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icache_access ? icache_latency - ticks(1) : 0;
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Tick dcache_stall =
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Tick dcache_stall =
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dcache_access ? dcache_latency - cycles(1) : 0;
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dcache_access ? dcache_latency - ticks(1) : 0;
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Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
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Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
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if (cycles(stall_cycles) < (icache_stall + dcache_stall))
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if (ticks(stall_cycles) < (icache_stall + dcache_stall))
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latency += cycles(stall_cycles+1);
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latency += ticks(stall_cycles+1);
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else
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else
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latency += cycles(stall_cycles);
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latency += ticks(stall_cycles);
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}
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}
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}
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}
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@ -222,7 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
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_status = Running;
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_status = Running;
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// kick things off by initiating the fetch of the next instruction
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// kick things off by initiating the fetch of the next instruction
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fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
|
fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -110,10 +110,10 @@ TraceCPU::tick()
|
||||||
if (mainEventQueue.empty()) {
|
if (mainEventQueue.empty()) {
|
||||||
exitSimLoop("end of memory trace reached");
|
exitSimLoop("end of memory trace reached");
|
||||||
} else {
|
} else {
|
||||||
tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
|
tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
tickEvent.schedule(max(curTick + cycles(1), nextCycle));
|
tickEvent.schedule(max(curTick + ticks(1), nextCycle));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -107,7 +107,7 @@ class TraceCPU : public SimObject
|
||||||
MemInterface *dcache_interface,
|
MemInterface *dcache_interface,
|
||||||
MemTraceReader *data_trace);
|
MemTraceReader *data_trace);
|
||||||
|
|
||||||
inline Tick cycles(int numCycles) { return numCycles; }
|
inline Tick ticks(int numCycles) { return numCycles; }
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Perform all the accesses for one cycle.
|
* Perform all the accesses for one cycle.
|
||||||
|
|
|
@ -1104,7 +1104,7 @@ IGbE::restartClock()
|
||||||
{
|
{
|
||||||
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
|
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
|
||||||
SimObject::Running)
|
SimObject::Running)
|
||||||
tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1));
|
tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned int
|
unsigned int
|
||||||
|
@ -1400,7 +1400,7 @@ IGbE::tick()
|
||||||
|
|
||||||
|
|
||||||
if (rxTick || txTick || txFifoTick)
|
if (rxTick || txTick || txFifoTick)
|
||||||
tickEvent.schedule(curTick + cycles(1));
|
tickEvent.schedule(curTick + ticks(1));
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
|
@ -614,7 +614,7 @@ class IGbE : public EtherDevice
|
||||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
||||||
|
|
||||||
Tick clock;
|
Tick clock;
|
||||||
inline Tick cycles(int numCycles) const { return numCycles * clock; }
|
inline Tick ticks(int numCycles) const { return numCycles * clock; }
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
virtual Tick read(PacketPtr pkt);
|
||||||
virtual Tick write(PacketPtr pkt);
|
virtual Tick write(PacketPtr pkt);
|
||||||
|
|
|
@ -1469,7 +1469,7 @@ NSGigE::rxKick()
|
||||||
}
|
}
|
||||||
|
|
||||||
// Go to the next state machine clock tick.
|
// Go to the next state machine clock tick.
|
||||||
rxKickTick = curTick + cycles(1);
|
rxKickTick = curTick + ticks(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
switch(rxDmaState) {
|
switch(rxDmaState) {
|
||||||
|
@ -1916,7 +1916,7 @@ NSGigE::txKick()
|
||||||
}
|
}
|
||||||
|
|
||||||
// Go to the next state machine clock tick.
|
// Go to the next state machine clock tick.
|
||||||
txKickTick = curTick + cycles(1);
|
txKickTick = curTick + ticks(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
switch(txDmaState) {
|
switch(txDmaState) {
|
||||||
|
@ -2322,7 +2322,7 @@ NSGigE::transferDone()
|
||||||
|
|
||||||
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
|
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
|
||||||
|
|
||||||
txEvent.reschedule(curTick + cycles(1), true);
|
txEvent.reschedule(curTick + ticks(1), true);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
|
|
|
@ -199,7 +199,7 @@ class NSGigE : public EtherDevice
|
||||||
|
|
||||||
/* state machine cycle time */
|
/* state machine cycle time */
|
||||||
Tick clock;
|
Tick clock;
|
||||||
inline Tick cycles(int numCycles) const { return numCycles * clock; }
|
inline Tick ticks(int numCycles) const { return numCycles * clock; }
|
||||||
|
|
||||||
/* tx State Machine */
|
/* tx State Machine */
|
||||||
TxState txState;
|
TxState txState;
|
||||||
|
|
|
@ -1211,7 +1211,7 @@ Device::transferDone()
|
||||||
|
|
||||||
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
|
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
|
||||||
|
|
||||||
txEvent.reschedule(curTick + cycles(1), true);
|
txEvent.reschedule(curTick + ticks(1), true);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
|
|
|
@ -51,7 +51,7 @@ class Base : public PciDev
|
||||||
bool rxEnable;
|
bool rxEnable;
|
||||||
bool txEnable;
|
bool txEnable;
|
||||||
Tick clock;
|
Tick clock;
|
||||||
inline Tick cycles(int numCycles) const { return numCycles * clock; }
|
inline Tick ticks(int numCycles) const { return numCycles * clock; }
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
Tick intrDelay;
|
Tick intrDelay;
|
||||||
|
|
|
@ -105,7 +105,7 @@ namespace PseudoInst
|
||||||
|
|
||||||
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
|
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
|
||||||
|
|
||||||
Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
|
Tick resume = curTick + tc->getCpuPtr()->ticks(cycles);
|
||||||
|
|
||||||
quiesceEvent->reschedule(resume, true);
|
quiesceEvent->reschedule(resume, true);
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue