ARM: Add BKPT instruction
--HG-- rename : src/arch/arm/isa/formats/unknown.isa => src/arch/arm/isa/formats/breakpoint.isa
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3 changed files with 98 additions and 0 deletions
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@ -73,6 +73,7 @@ format DataOp {
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0x9: ArmBlxReg::armBlxReg();
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}
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0x5: ArmSatAddSub::armSatAddSub();
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0x7: Breakpoint::bkpt();
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}
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0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
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}
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94
src/arch/arm/isa/formats/breakpoint.isa
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94
src/arch/arm/isa/formats/breakpoint.isa
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@ -0,0 +1,94 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// Breakpoint instructions
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//
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output header {{
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/**
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* Static instruction class for Breakpoint (illegal) instructions.
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* These cause simulator termination if they are executed in a
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* non-speculative mode. This is a leaf class.
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*/
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class Breakpoint : public ArmStaticInst
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{
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public:
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/// Constructor
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Breakpoint(ExtMachInst _machInst)
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: ArmStaticInst("Breakpoint", _machInst, No_OpClass)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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Breakpoint::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
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"Breakpoint", machInst, OPCODE, inst2string(machInst));
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}
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}};
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output exec {{
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Fault
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Breakpoint::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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return new PrefetchAbort(xc->readPC(), ArmFault::DebugEvent);
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}
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}};
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def format Breakpoint() {{
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decode_block = 'return new Breakpoint(machInst);\n'
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}};
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@ -68,6 +68,9 @@
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//Include the unknown format
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##include "unknown.isa"
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//Include the breakpoint format
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##include "breakpoint.isa"
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//Include the formats for data processing instructions
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##include "data.isa"
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