config: Use shared cache config for regressions

This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.

configs/common/Caches.py

@@ -40,32 +40,29 @@
 
 from m5.objects import *
 
-class L1Cache(BaseCache):
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+class L1(BaseCache):
     assoc = 2
-    block_size = 64
     hit_latency = 2
     response_latency = 2
-    mshrs = 10
+    block_size = 64
+    mshrs = 4
     tgts_per_mshr = 20
     is_top_level = True
 
-class L2Cache(BaseCache):
+class L2(BaseCache):
     assoc = 8
     block_size = 64
     hit_latency = 20
     response_latency = 20
-    mshrs = 20
+    mshrs = 92
-    tgts_per_mshr = 12
+    tgts_per_mshr = 16
-
+    write_buffers = 8
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-    is_top_level = True
 
 class IOCache(BaseCache):
     assoc = 8
@@ -77,3 +74,14 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     forward_snoops = False
     is_top_level = True
+
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    hit_latency = 2
+    response_latency = 2
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+    is_top_level = True
+

tests/configs/o3-timing-mp.py

@@ -29,30 +29,7 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
 
 nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]

tests/configs/pc-o3-timing.py

@@ -31,59 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
 #the system
@@ -94,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/pc-simple-atomic.py

@@ -31,61 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-    is_top_level = True
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-    is_top_level = True
-
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
 #the system
@@ -96,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/pc-simple-timing.py

@@ -31,60 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
-
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
 #the system
@@ -95,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-o3-checker.py

@@ -39,45 +39,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
@@ -89,7 +51,7 @@ system.cpu = cpu
 cpu.addCheckerCpu()
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-o3-dual.py

@@ -31,50 +31,13 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 from Benchmarks import *
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-o3.py

@@ -30,45 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-simple-atomic-dual.py

@@ -31,50 +31,13 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 from Benchmarks import *
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-simple-atomic.py

@@ -30,44 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
@@ -77,7 +40,7 @@ system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-simple-timing-dual.py

@@ -31,50 +31,13 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 from Benchmarks import *
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/realview-simple-timing.py

@@ -30,45 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='256MB')]
-    forward_snoops = False
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-inorder.py

@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpu = InOrderCPU(cpu_id=0)
@@ -82,7 +43,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-o3-dual.py

@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpus
 #create the l1/l2 bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-o3.py

@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 20
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-simple-atomic-dual.py

@@ -30,51 +30,13 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-simple-atomic.py

@@ -30,45 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-simple-timing-dual.py

@@ -30,51 +30,13 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('timing')
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 

tests/configs/tsunami-simple-timing.py

@@ -30,46 +30,7 @@ import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
-
+from Caches import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size='8GB')]
-    forward_snoops = False
-    is_top_level = True
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
@@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave