ARM: Fix issue with m5.fast and ARM
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1 changed files with 1 additions and 4 deletions
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@ -424,10 +424,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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flags = TLB::MustBeOne | TLB::UserMode;
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mode = BaseTLB::Write;
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break;
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case MISCREG_V2POWPR:
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case MISCREG_V2POWPW:
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case MISCREG_V2POWUR:
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case MISCREG_V2POWUW:
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default:
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panic("Security Extensions not implemented!");
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}
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req->setVirt(0, val, 1, flags, tc->readPC());
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