X86: Move address based decode caching in front of the predecoder.
The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Gabe Black
parent
63b10907ef
commit
d1965af220
4 changed files with 245 additions and 71 deletions
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@ -38,10 +38,15 @@
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namespace X86ISA
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{
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void Decoder::doReset()
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Decoder::State
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Decoder::doResetState()
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{
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origPC = basePC + offset;
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DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
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instBytes = &decodePages->lookup(origPC);
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chunkIdx = 0;
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emi.rex = 0;
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emi.legacy = 0;
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emi.opcode.num = 0;
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@ -55,12 +60,17 @@ void Decoder::doReset()
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emi.modRM = 0;
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emi.sib = 0;
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m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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emi.mode.mode = m5Reg.mode;
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emi.mode.submode = m5Reg.submode;
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if (instBytes->si) {
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return FromCacheState;
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} else {
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instBytes->chunks.clear();
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return PrefixState;
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}
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}
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void Decoder::process()
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void
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Decoder::process()
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{
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//This function drives the decoder state machine.
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@ -70,15 +80,18 @@ void Decoder::process()
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assert(!outOfBytes);
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assert(!instDone);
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if (state == ResetState)
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state = doResetState();
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if (state == FromCacheState) {
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state = doFromCacheState();
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} else {
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instBytes->chunks.push_back(fetchChunk);
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}
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//While there's still something to do...
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while(!instDone && !outOfBytes)
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{
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while (!instDone && !outOfBytes) {
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uint8_t nextByte = getNextByte();
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switch(state)
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{
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case ResetState:
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doReset();
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state = PrefixState;
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switch (state) {
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case PrefixState:
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state = doPrefixState(nextByte);
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break;
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@ -105,9 +118,42 @@ void Decoder::process()
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}
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}
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Decoder::State
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Decoder::doFromCacheState()
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{
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DPRINTF(Decoder, "Looking at cache state.\n");
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if ((fetchChunk & instBytes->masks[chunkIdx]) !=
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instBytes->chunks[chunkIdx]) {
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DPRINTF(Decoder, "Decode cache miss.\n");
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// The chached chunks didn't match what was fetched. Fall back to the
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// predecoder.
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instBytes->chunks[chunkIdx] = fetchChunk;
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instBytes->chunks.resize(chunkIdx + 1);
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instBytes->si = NULL;
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chunkIdx = 0;
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fetchChunk = instBytes->chunks[0];
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offset = origPC % sizeof(MachInst);
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basePC = origPC - offset;
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return PrefixState;
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} else if (chunkIdx == instBytes->chunks.size() - 1) {
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// We matched the cache, so use its value.
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instDone = true;
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offset = instBytes->lastOffset;
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if (offset == sizeof(MachInst))
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outOfBytes = true;
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return ResetState;
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} else {
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// We matched so far, but need to check more chunks.
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chunkIdx++;
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outOfBytes = true;
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return FromCacheState;
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}
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}
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//Either get a prefix and record it in the ExtMachInst, or send the
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//state machine on to get the opcode(s).
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Decoder::State Decoder::doPrefixState(uint8_t nextByte)
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Decoder::State
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Decoder::doPrefixState(uint8_t nextByte)
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{
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uint8_t prefix = Prefixes[nextByte];
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State nextState = PrefixState;
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@ -164,7 +210,8 @@ Decoder::State Decoder::doPrefixState(uint8_t nextByte)
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//Load all the opcodes (currently up to 2) and then figure out
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//what immediate and/or ModRM is needed.
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Decoder::State Decoder::doOpcodeState(uint8_t nextByte)
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Decoder::State
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Decoder::doOpcodeState(uint8_t nextByte)
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{
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State nextState = ErrorState;
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emi.opcode.num++;
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@ -194,9 +241,9 @@ Decoder::State Decoder::doOpcodeState(uint8_t nextByte)
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if (emi.rex.w)
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logOpSize = 3; // 64 bit operand size
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else if (emi.legacy.op)
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logOpSize = m5Reg.altOp;
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logOpSize = altOp;
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else
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logOpSize = m5Reg.defOp;
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logOpSize = defOp;
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//Set the actual op size
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emi.opSize = 1 << logOpSize;
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@ -205,16 +252,16 @@ Decoder::State Decoder::doOpcodeState(uint8_t nextByte)
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//a fixed value at the decoder level.
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int logAddrSize;
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if(emi.legacy.addr)
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logAddrSize = m5Reg.altAddr;
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logAddrSize = altAddr;
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else
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logAddrSize = m5Reg.defAddr;
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logAddrSize = defAddr;
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//Set the actual address size
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emi.addrSize = 1 << logAddrSize;
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//Figure out the effective stack width. This can be overriden to
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//a fixed value at the decoder level.
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emi.stackSize = 1 << m5Reg.stack;
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emi.stackSize = 1 << stack;
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//Figure out how big of an immediate we'll retreive based
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//on the opcode.
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@ -242,13 +289,14 @@ Decoder::State Decoder::doOpcodeState(uint8_t nextByte)
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//Get the ModRM byte and determine what displacement, if any, there is.
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//Also determine whether or not to get the SIB byte, displacement, or
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//immediate next.
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Decoder::State Decoder::doModRMState(uint8_t nextByte)
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Decoder::State
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Decoder::doModRMState(uint8_t nextByte)
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{
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State nextState = ErrorState;
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ModRM modRM;
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modRM = nextByte;
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DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
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if (m5Reg.defOp == 1) {
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if (defOp == 1) {
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//figure out 16 bit displacement size
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if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
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displacementSize = 2;
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@ -297,7 +345,8 @@ Decoder::State Decoder::doModRMState(uint8_t nextByte)
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//Get the SIB byte. We don't do anything with it at this point, other
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//than storing it in the ExtMachInst. Determine if we need to get a
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//displacement or immediate next.
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Decoder::State Decoder::doSIBState(uint8_t nextByte)
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Decoder::State
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Decoder::doSIBState(uint8_t nextByte)
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{
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State nextState = ErrorState;
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emi.sib = nextByte;
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@ -318,7 +367,8 @@ Decoder::State Decoder::doSIBState(uint8_t nextByte)
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//Gather up the displacement, or at least as much of it
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//as we can get.
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Decoder::State Decoder::doDisplacementState()
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Decoder::State
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Decoder::doDisplacementState()
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{
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State nextState = ErrorState;
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@ -365,7 +415,8 @@ Decoder::State Decoder::doDisplacementState()
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//Gather up the immediate, or at least as much of it
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//as we can get
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Decoder::State Decoder::doImmediateState()
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Decoder::State
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Decoder::doImmediateState()
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{
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State nextState = ErrorState;
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@ -408,24 +459,62 @@ Decoder::State Decoder::doImmediateState()
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return nextState;
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}
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DecodeCache::InstMap Decoder::instMap;
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DecodeCache::AddrMap<StaticInstPtr> Decoder::decodePages;
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Decoder::InstBytes Decoder::dummy;
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Decoder::InstCacheMap Decoder::instCacheMap;
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StaticInstPtr
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Decoder::decode(ExtMachInst mach_inst, Addr addr)
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{
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StaticInstPtr &si = decodePages.lookup(addr);
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if (si && (si->machInst == mach_inst))
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DecodeCache::InstMap::iterator iter = instMap->find(mach_inst);
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if (iter != instMap->end())
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return iter->second;
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StaticInstPtr si = decodeInst(mach_inst);
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(*instMap)[mach_inst] = si;
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return si;
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}
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StaticInstPtr
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Decoder::decode(PCState &nextPC)
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{
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if (!instDone)
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return NULL;
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instDone = false;
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updateNPC(nextPC);
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StaticInstPtr &si = instBytes->si;
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if (si)
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return si;
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DecodeCache::InstMap::iterator iter = instMap.find(mach_inst);
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if (iter != instMap.end()) {
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si = iter->second;
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return si;
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// We didn't match in the AddrMap, but we still populated an entry. Fix
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// up its byte masks.
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const int chunkSize = sizeof(MachInst);
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instBytes->lastOffset = offset;
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Addr firstBasePC = basePC - (instBytes->chunks.size() - 1) * chunkSize;
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Addr firstOffset = origPC - firstBasePC;
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Addr totalSize = instBytes->lastOffset - firstOffset +
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(instBytes->chunks.size() - 1) * chunkSize;
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int start = firstOffset;
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instBytes->masks.clear();
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while (totalSize) {
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int end = start + totalSize;
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end = (chunkSize < end) ? chunkSize : end;
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int size = end - start;
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int idx = instBytes->masks.size();
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MachInst maskVal = mask(size * 8) << (start * 8);
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assert(maskVal);
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instBytes->masks.push_back(maskVal);
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instBytes->chunks[idx] &= instBytes->masks[idx];
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totalSize -= size;
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start = 0;
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}
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si = decodeInst(mach_inst);
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instMap[mach_inst] = si;
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si = decode(emi, origPC);
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return si;
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}
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@ -32,6 +32,7 @@
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#define __ARCH_X86_DECODER_HH__
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#include <cassert>
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#include <vector>
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#include "arch/x86/regs/misc.hh"
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#include "arch/x86/types.hh"
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@ -58,9 +59,24 @@ class Decoder
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static const uint8_t SizeTypeToSize[3][10];
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protected:
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struct InstBytes
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{
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StaticInstPtr si;
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std::vector<MachInst> chunks;
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std::vector<MachInst> masks;
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int lastOffset;
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InstBytes() : lastOffset(0)
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{}
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};
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static InstBytes dummy;
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ThreadContext * tc;
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//The bytes to be predecoded
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MachInst fetchChunk;
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InstBytes *instBytes;
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int chunkIdx;
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//The pc of the start of fetchChunk
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Addr basePC;
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//The pc the current instruction started at
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@ -69,9 +85,16 @@ class Decoder
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int offset;
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//The extended machine instruction being generated
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ExtMachInst emi;
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HandyM5Reg m5Reg;
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//Predecoding state
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X86Mode mode;
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X86SubMode submode;
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uint8_t altOp;
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uint8_t defOp;
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uint8_t altAddr;
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uint8_t defAddr;
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uint8_t stack;
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inline uint8_t getNextByte()
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uint8_t getNextByte()
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{
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return ((uint8_t *)&fetchChunk)[offset];
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}
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@ -99,24 +122,35 @@ class Decoder
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consumeBytes(toGet);
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}
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inline void consumeByte()
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void updateOffsetState()
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{
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assert(offset <= sizeof(MachInst));
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if (offset == sizeof(MachInst)) {
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DPRINTF(Decoder, "At the end of a chunk, idx = %d, chunks = %d.\n",
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chunkIdx, instBytes->chunks.size());
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chunkIdx++;
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if (chunkIdx == instBytes->chunks.size()) {
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outOfBytes = true;
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} else {
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offset = 0;
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fetchChunk = instBytes->chunks[chunkIdx];
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basePC += sizeof(MachInst);
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}
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}
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}
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void consumeByte()
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{
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offset++;
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assert(offset <= sizeof(MachInst));
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if(offset == sizeof(MachInst))
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outOfBytes = true;
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updateOffsetState();
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}
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inline void consumeBytes(int numBytes)
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void consumeBytes(int numBytes)
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{
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offset += numBytes;
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assert(offset <= sizeof(MachInst));
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if(offset == sizeof(MachInst))
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outOfBytes = true;
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updateOffsetState();
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}
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void doReset();
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//State machine state
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protected:
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//Whether or not we're out of bytes
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@ -133,6 +167,7 @@ class Decoder
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enum State {
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ResetState,
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FromCacheState,
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PrefixState,
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OpcodeState,
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ModRMState,
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@ -146,6 +181,8 @@ class Decoder
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State state;
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//Functions to handle each of the states
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State doResetState();
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State doFromCacheState();
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State doPrefixState(uint8_t);
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State doOpcodeState(uint8_t);
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State doModRMState(uint8_t);
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@ -153,6 +190,20 @@ class Decoder
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State doDisplacementState();
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State doImmediateState();
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protected:
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/// Caching for decoded instruction objects.
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typedef MiscReg CacheKey;
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typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
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DecodePages *decodePages;
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typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap;
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AddrCacheMap addrCacheMap;
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DecodeCache::InstMap *instMap;
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typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
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static InstCacheMap instCacheMap;
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public:
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Decoder(ThreadContext * _tc) :
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tc(_tc), basePC(0), origPC(0), offset(0),
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@ -160,9 +211,47 @@ class Decoder
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state(ResetState)
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{
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memset(&emi, 0, sizeof(emi));
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emi.mode.mode = LongMode;
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emi.mode.submode = SixtyFourBitMode;
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m5Reg = 0;
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mode = LongMode;
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submode = SixtyFourBitMode;
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emi.mode.mode = mode;
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emi.mode.submode = submode;
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altOp = 0;
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defOp = 0;
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altAddr = 0;
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defAddr = 0;
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stack = 0;
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instBytes = &dummy;
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decodePages = NULL;
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instMap = NULL;
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}
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void setM5Reg(HandyM5Reg m5Reg)
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{
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mode = (X86Mode)(uint64_t)m5Reg.mode;
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submode = (X86SubMode)(uint64_t)m5Reg.submode;
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emi.mode.mode = mode;
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emi.mode.submode = submode;
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altOp = m5Reg.altOp;
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defOp = m5Reg.defOp;
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altAddr = m5Reg.altAddr;
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defAddr = m5Reg.defAddr;
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stack = m5Reg.stack;
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AddrCacheMap::iterator amIter = addrCacheMap.find(m5Reg);
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if (amIter != addrCacheMap.end()) {
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decodePages = amIter->second;
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} else {
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decodePages = new DecodePages;
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addrCacheMap[m5Reg] = decodePages;
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}
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InstCacheMap::iterator imIter = instCacheMap.find(m5Reg);
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if (imIter != instCacheMap.end()) {
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instMap = imIter->second;
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} else {
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instMap = new DecodeCache::InstMap;
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instCacheMap[m5Reg] = instMap;
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}
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}
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void reset()
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@ -218,11 +307,6 @@ class Decoder
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}
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}
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protected:
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/// Caching for decoded instruction objects.
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static DecodeCache::InstMap instMap;
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static DecodeCache::AddrMap<StaticInstPtr> decodePages;
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public:
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StaticInstPtr decodeInst(ExtMachInst mach_inst);
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@ -230,16 +314,7 @@ class Decoder
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
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StaticInstPtr
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decode(X86ISA::PCState &nextPC)
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{
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if (!instDone)
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return NULL;
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instDone = false;
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updateNPC(nextPC);
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return decode(emi, origPC);
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}
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StaticInstPtr decode(X86ISA::PCState &nextPC);
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};
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} // namespace X86ISA
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@ -28,6 +28,7 @@
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* Authors: Gabe Black
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*/
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#include "arch/x86/decoder.hh"
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#include "arch/x86/isa.hh"
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#include "arch/x86/tlb.hh"
|
||||
#include "cpu/base.hh"
|
||||
|
|
@ -39,7 +40,8 @@ namespace X86ISA
|
|||
|
||||
void
|
||||
ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
|
||||
ThreadContext *tc)
|
||||
{
|
||||
HandyM5Reg m5reg = 0;
|
||||
if (efer.lma) {
|
||||
|
|
@ -94,6 +96,8 @@ ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
|
|||
}
|
||||
|
||||
regVal[MISCREG_M5_REG] = m5reg;
|
||||
if (tc)
|
||||
tc->getDecoderPtr()->setM5Reg(m5reg);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -184,7 +188,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
|
|||
newCR0,
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
regVal[MISCREG_RFLAGS],
|
||||
tc);
|
||||
}
|
||||
break;
|
||||
case MISCREG_CR2:
|
||||
|
|
@ -225,7 +230,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
|
|||
regVal[MISCREG_CR0],
|
||||
newCSAttr,
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
regVal[MISCREG_RFLAGS],
|
||||
tc);
|
||||
}
|
||||
break;
|
||||
case MISCREG_SS_ATTR:
|
||||
|
|
@ -233,7 +239,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
|
|||
regVal[MISCREG_CR0],
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
val,
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
regVal[MISCREG_RFLAGS],
|
||||
tc);
|
||||
break;
|
||||
// These segments always actually use their bases, or in other words
|
||||
// their effective bases must stay equal to their actual bases.
|
||||
|
|
@ -340,7 +347,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
|
|||
regVal[MISCREG_CR0],
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
regVal[MISCREG_RFLAGS],
|
||||
tc);
|
||||
return;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -363,7 +371,8 @@ ISA::unserialize(EventManager *em, Checkpoint * cp,
|
|||
regVal[MISCREG_CR0],
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
regVal[MISCREG_RFLAGS],
|
||||
NULL);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,7 +50,8 @@ namespace X86ISA
|
|||
protected:
|
||||
MiscReg regVal[NUM_MISCREGS];
|
||||
void updateHandyM5Reg(Efer efer, CR0 cr0,
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
|
||||
ThreadContext *tc);
|
||||
|
||||
public:
|
||||
void clear();
|
||||
|
|
|
|||
Loading…
Reference in a new issue