dev: Add 'OSC' oscillator sys control reg support to VersatileExpress
The VE motherboard provides a set of system control registers through which various motherboard and coretile registers are accessed. Voltage regulators and oscillator (DLL/PLL) config are examples. These registers must be impleted to boot Linux 3.9+ kernels.
This commit is contained in:
Matt Evans
parent
c32fbb7c00
commit
d17529b046
3 changed files with 112 additions and 7 deletions
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@ -63,3 +63,4 @@ if env['TARGET_ISA'] == 'arm':
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DebugFlag('PL111')
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DebugFlag('Pl050')
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DebugFlag('GIC')
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DebugFlag('RVCTRL')
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010,2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -38,12 +38,13 @@
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*/
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#include "base/trace.hh"
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#include "debug/RVCTRL.hh"
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#include "dev/arm/rv_ctrl.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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RealViewCtrl::RealViewCtrl(Params *p)
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: BasicPioDevice(p, 0xD4), flags(0)
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: BasicPioDevice(p, 0xD4), flags(0), scData(0)
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{
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}
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@ -105,9 +106,18 @@ RealViewCtrl::read(PacketPtr pkt)
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case CfgStat:
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pkt->set<uint32_t>(1);
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break;
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case CfgData:
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pkt->set<uint32_t>(scData);
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DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
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break;
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case CfgCtrl:
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pkt->set<uint32_t>(0); // not busy
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DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
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break;
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default:
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warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
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daddr);
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pkt->set<uint32_t>(0);
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break;
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}
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pkt->makeAtomicResponse();
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@ -139,9 +149,99 @@ RealViewCtrl::write(PacketPtr pkt)
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case FlagsClr:
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flags = 0;
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break;
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case CfgData:
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scData = pkt->get<uint32_t>();
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break;
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case CfgCtrl: {
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// A request is being submitted to read/write the system control
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// registers. See
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// http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
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// For now, model as much of the OSC regs (can't find docs) as Linux
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// seems to require (can't find docs); some clocks are deemed to be 0,
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// giving all kinds of /0 problems booting Linux 3.9. Return a
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// vaguely plausible number within the range the device trees state:
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uint32_t data = pkt->get<uint32_t>();
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uint16_t dev = bits(data, 11, 0);
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uint8_t pos = bits(data, 15, 12);
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uint8_t site = bits(data, 17, 16);
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uint8_t func = bits(data, 25, 20);
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uint8_t dcc = bits(data, 29, 26);
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bool wr = bits(data, 30);
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bool start = bits(data, 31);
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if (start) {
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if (wr) {
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warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n",
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scData, dcc, site, pos, func, dev);
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// Only really support reading, for now!
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} else {
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// Only deal with function 1 (oscillators) so far!
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if (dcc != 0 || pos != 0 || func != 1) {
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warn("SCReg: read from unknown area "
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"(dcc %d:site%d:pos%d:fn%d:dev%d)\n",
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dcc, site, pos, func, dev);
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} else {
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switch (site) {
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case 0: { // Motherboard regs
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switch(dev) {
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case 0: // MCC clk
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scData = 25000000;
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break;
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case 1: // CLCD clk
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scData = 25000000;
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break;
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case 2: // PeriphClk 24MHz
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scData = 24000000;
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break;
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default:
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scData = 0;
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warn("SCReg: read from unknown dev %d "
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"(site%d:pos%d:fn%d)\n",
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dev, site, pos, func);
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}
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} break;
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case 1: { // Coretile 1 regs
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switch(dev) {
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case 0: // CPU PLL ref
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scData = 50000000;
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break;
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case 4: // Muxed AXI master clock
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scData = 40000000;
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break;
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case 5: // HDLCD clk
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scData = 50000000;
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break;
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case 6: // SMB clock
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scData = 35000000;
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break;
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case 7: // SYS PLL (also used for pl011 UART!)
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scData = 40000000;
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break;
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case 8: // DDR PLL 40MHz fixed
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scData = 40000000;
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break;
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default:
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scData = 0;
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warn("SCReg: read from unknown dev %d "
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"(site%d:pos%d:fn%d)\n",
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dev, site, pos, func);
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}
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} break;
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default:
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warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n",
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site, pos, func, dev);
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}
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DPRINTF(RVCTRL, "SCReg: Will read %#x (ctrlWr %#x)\n", scData, data);
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}
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}
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} else {
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DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", data);
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}
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} break;
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case CfgStat: // Weird to write this
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default:
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warn("Tried to write RVIO at offset %#x that doesn't exist\n",
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daddr);
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warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
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daddr, pkt->get<uint32_t>());
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break;
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}
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pkt->makeAtomicResponse();
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010,2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -80,8 +80,8 @@ class RealViewCtrl : public BasicPioDevice
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IoSel = 0x70,
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ProcId0 = 0x84,
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ProcId1 = 0x88,
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CfgCtrl = 0xA0,
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CfgData = 0xA4,
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CfgData = 0xA0,
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CfgCtrl = 0xA4,
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CfgStat = 0xA8,
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TestOsc0 = 0xC0,
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TestOsc1 = 0xC4,
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@ -105,6 +105,10 @@ class RealViewCtrl : public BasicPioDevice
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*/
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uint32_t flags;
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/** This register contains the result from a system control reg access
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*/
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uint32_t scData;
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public:
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typedef RealViewCtrlParams Params;
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const Params *
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