ARM: Clean up the ISA desc portion of the ARM memory instructions.
This commit is contained in:
Gabe Black
parent
ef3a3dc28a
commit
d1362d582a
4 changed files with 585 additions and 649 deletions
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@ -43,100 +43,64 @@ let {{
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decoder_output = ""
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decoder_output = ""
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exec_output = ""
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exec_output = ""
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def loadImmClassName(post, add, writeback, \
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class LoadInst(LoadStoreInst):
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size=4, sign=False, user=False):
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execBase = 'Load'
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return memClassName("LOAD_IMM", post, add, writeback,
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size, sign, user)
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def loadRegClassName(post, add, writeback, \
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def __init__(self, mnem, post, add, writeback,
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size=4, sign=False, user=False):
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size=4, sign=False, user=False, flavor="normal"):
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return memClassName("LOAD_REG", post, add, writeback,
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super(LoadInst, self).__init__()
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size, sign, user)
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def loadDoubleImmClassName(post, add, writeback):
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self.name = mnem
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return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
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self.post = post
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self.add = add
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self.writeback = writeback
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self.size = size
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self.sign = sign
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self.user = user
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self.flavor = flavor
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def loadDoubleRegClassName(post, add, writeback):
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if self.add:
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return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
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self.op = " +"
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else:
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self.op = " -"
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self.memFlags = ["ArmISA::TLB::MustBeOne"]
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self.codeBlobs = {"postacc_code" : ""}
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def emitHelper(self, base = 'Memory'):
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def emitLoad(name, Name, imm, eaCode, accCode, \
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memFlags, instFlags, base, double=False):
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global header_output, decoder_output, exec_output
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global header_output, decoder_output, exec_output
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codeBlobs = self.codeBlobs
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codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
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(newHeader,
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(newHeader,
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newDecoder,
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newDecoder,
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newExec) = loadStoreBase(name, Name, imm,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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eaCode, accCode, "",
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self.memFlags, [], base)
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memFlags, instFlags, double, False,
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base, execTemplateBase = 'Load')
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header_output += newHeader
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header_output += newHeader
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decoder_output += newDecoder
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decoder_output += newDecoder
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exec_output += newExec
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exec_output += newExec
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def buildImmLoad(mnem, post, add, writeback, \
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class RfeInst(LoadInst):
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size=4, sign=False, user=False, \
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decConstBase = 'Rfe'
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prefetch=False, ldrex=False, vldr=False):
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name = mnem
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Name = loadImmClassName(post, add, writeback, \
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size, sign, user)
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if add:
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def __init__(self, mnem, post, add, writeback):
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op = " +"
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super(RfeInst, self).__init__(mnem, post, add, writeback)
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else:
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self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
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op = " -"
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offset = op + " imm"
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self.memFlags.append("ArmISA::TLB::AlignWord")
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eaCode = "EA = Base"
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if not post:
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eaCode += offset
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eaCode += ";"
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memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
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if user:
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memFlags.append("ArmISA::TLB::UserMode")
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if prefetch:
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Name = "%s_%s" % (mnem.upper(), Name)
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memFlags.append("Request::PREFETCH")
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accCode = '''
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uint64_t temp = Mem%s;\n
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temp = temp;
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''' % buildMemSuffix(sign, size)
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elif vldr:
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Name = "%s_%s" % (mnem.upper(), Name)
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accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" % \
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buildMemSuffix(sign, size)
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else:
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if ldrex:
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memFlags.append("Request::LLSC")
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Name = "%s_%s" % (mnem.upper(), Name)
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accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \
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buildMemSuffix(sign, size)
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if not prefetch and not ldrex and not vldr:
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memFlags.append("ArmISA::TLB::AllowUnaligned")
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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base = buildMemBase("MemoryImm", post, writeback)
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emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
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def buildRfeLoad(mnem, post, add, writeback):
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name = mnem
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Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
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def emit(self):
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offset = 0
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offset = 0
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if post != add:
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if self.post != self.add:
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offset += 4
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offset += 4
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if not add:
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if not self.add:
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offset -= 8
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offset -= 8
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self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset
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eaCode = "EA = Base + %d;" % offset
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wbDiff = -8
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wbDiff = -8
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if add:
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if self.add:
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wbDiff = 8
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wbDiff = 8
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accCode = '''
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accCode = '''
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CPSR cpsr = Cpsr;
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CPSR cpsr = Cpsr;
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@ -149,80 +113,115 @@ let {{
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Cpsr = ~CondCodesMask & newCpsr;
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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'''
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if writeback:
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if self.writeback:
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accCode += "Base = Base + %s;\n" % wbDiff
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accCode += "Base = Base + %s;\n" % wbDiff
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self.codeBlobs["memacc_code"] = accCode
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global header_output, decoder_output, exec_output
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self.emitHelper('RfeOp')
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(newHeader,
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class LoadImmInst(LoadInst):
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newDecoder,
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def __init__(self, *args, **kargs):
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newExec) = RfeBase(name, Name, eaCode, accCode,
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super(LoadImmInst, self).__init__(*args, **kargs)
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["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [])
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self.offset = self.op + " imm"
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header_output += newHeader
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class LoadRegInst(LoadInst):
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decoder_output += newDecoder
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def __init__(self, *args, **kargs):
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exec_output += newExec
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super(LoadRegInst, self).__init__(*args, **kargs)
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self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
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def buildRegLoad(mnem, post, add, writeback, size=4, sign=False, \
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user=False, prefetch=False):
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name = mnem
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Name = loadRegClassName(post, add, writeback,
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size, sign, user)
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if add:
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op = " +"
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else:
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op = " -"
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offset = op + " shift_rm_imm(Index, shiftAmt," + \
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" shiftType, CondCodes<29:>)"
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" shiftType, CondCodes<29:>)"
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class LoadSingle(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadSingle, self).__init__(*args, **kargs)
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# Build the default class name
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self.Name = self.nameFunc(self.post, self.add, self.writeback,
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self.size, self.sign, self.user)
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# Add memory request flags where necessary
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self.memFlags.append("%d" % (self.size - 1))
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if self.user:
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self.memFlags.append("ArmISA::TLB::UserMode")
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if self.flavor == "prefetch":
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self.memFlags.append("Request::PREFETCH")
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elif self.flavor == "exclusive":
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self.memFlags.append("Request::LLSC")
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elif self.flavor == "normal":
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self.memFlags.append("ArmISA::TLB::AllowUnaligned")
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# Disambiguate the class name for different flavors of loads
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if self.flavor != "normal":
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self.Name = "%s_%s" % (self.name.upper(), self.Name)
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def emit(self):
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# Address compuation code
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eaCode = "EA = Base"
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eaCode = "EA = Base"
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if not post:
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if not self.post:
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eaCode += offset
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eaCode += self.offset
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eaCode += ";"
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eaCode += ";"
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self.codeBlobs["ea_code"] = eaCode
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memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"]
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# Code that actually handles the access
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if user:
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if self.flavor == "prefetch":
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memFlags.append("ArmISA::TLB::UserMode")
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accCode = 'uint64_t temp = Mem%s; temp = temp;'
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elif self.flavor == "fp":
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if prefetch:
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accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
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Name = "%s_%s" % (mnem.upper(), Name)
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memFlags.append("Request::PREFETCH")
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accCode = '''
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uint64_t temp = Mem%s;\n
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temp = temp;
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''' % buildMemSuffix(sign, size)
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else:
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else:
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accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \
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accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
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buildMemSuffix(sign, size)
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accCode = accCode % buildMemSuffix(self.sign, self.size)
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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if not prefetch:
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if self.writeback:
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memFlags.append("ArmISA::TLB::AllowUnaligned")
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accCode += "Base = Base %s;\n" % self.offset
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base = buildMemBase("MemoryReg", post, writeback)
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self.codeBlobs["memacc_code"] = accCode
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emitLoad(name, Name, False, eaCode, accCode, \
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# Push it out to the output files
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memFlags, [], base)
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base = buildMemBase(self.basePrefix, self.post, self.writeback)
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self.emitHelper(base)
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def buildDoubleImmLoad(mnem, post, add, writeback, \
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def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
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ldrex=False, vldr=False):
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return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
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name = mnem
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Name = loadDoubleImmClassName(post, add, writeback)
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if add:
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class LoadImm(LoadImmInst, LoadSingle):
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op = " +"
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decConstBase = 'LoadStoreImm'
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else:
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basePrefix = 'MemoryImm'
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op = " -"
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nameFunc = staticmethod(loadImmClassName)
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offset = op + " imm"
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def loadRegClassName(post, add, writeback, size=4, sign=False, user=False):
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return memClassName("LOAD_REG", post, add, writeback, size, sign, user)
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class LoadReg(LoadRegInst, LoadSingle):
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decConstBase = 'LoadStoreReg'
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basePrefix = 'MemoryReg'
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nameFunc = staticmethod(loadRegClassName)
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class LoadDouble(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadDouble, self).__init__(*args, **kargs)
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# Build the default class name
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self.Name = self.nameFunc(self.post, self.add, self.writeback)
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# Add memory request flags where necessary
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if self.flavor == "exclusive":
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self.memFlags.append("Request::LLSC")
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self.memFlags.append("ArmISA::TLB::AlignWord")
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# Disambiguate the class name for different flavors of loads
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if self.flavor != "normal":
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self.Name = "%s_%s" % (self.name.upper(), self.Name)
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def emit(self):
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# Address computation code
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eaCode = "EA = Base"
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eaCode = "EA = Base"
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if not post:
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if not self.post:
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eaCode += offset
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eaCode += self.offset
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eaCode += ";"
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eaCode += ";"
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self.codeBlobs["ea_code"] = eaCode
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if not vldr:
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# Code that actually handles the access
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if self.flavor != "fp":
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accCode = '''
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accCode = '''
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CPSR cpsr = Cpsr;
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CPSR cpsr = Cpsr;
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Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
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Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
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@ -234,94 +233,75 @@ let {{
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FpDest.uw = (uint32_t)swappedMem;
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FpDest.uw = (uint32_t)swappedMem;
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FpDest2.uw = (uint32_t)(swappedMem >> 32);
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FpDest2.uw = (uint32_t)(swappedMem >> 32);
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'''
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'''
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if ldrex:
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memFlags = ["Request::LLSC"]
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else:
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memFlags = []
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if ldrex or vldr:
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Name = "%s_%s" % (mnem.upper(), Name)
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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base = buildMemBase("MemoryDImm", post, writeback)
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memFlags.extend(["ArmISA::TLB::MustBeOne",
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if self.writeback:
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"ArmISA::TLB::AlignWord"])
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accCode += "Base = Base %s;\n" % self.offset
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emitLoad(name, Name, True, eaCode, accCode, \
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self.codeBlobs["memacc_code"] = accCode
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memFlags, [], base, double=True)
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def buildDoubleRegLoad(mnem, post, add, writeback):
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# Push it out to the output files
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name = mnem
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base = buildMemBase(self.basePrefix, self.post, self.writeback)
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Name = loadDoubleRegClassName(post, add, writeback)
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self.emitHelper(base)
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if add:
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def loadDoubleImmClassName(post, add, writeback):
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op = " +"
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return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
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else:
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op = " -"
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offset = op + " shift_rm_imm(Index, shiftAmt," + \
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class LoadDoubleImm(LoadImmInst, LoadDouble):
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" shiftType, CondCodes<29:>)"
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decConstBase = 'LoadStoreDImm'
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eaCode = "EA = Base"
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basePrefix = 'MemoryDImm'
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if not post:
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nameFunc = staticmethod(loadDoubleImmClassName)
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eaCode += offset
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eaCode += ";"
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accCode = '''
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def loadDoubleRegClassName(post, add, writeback):
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CPSR cpsr = Cpsr;
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return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
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Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
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Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
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'''
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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base = buildMemBase("MemoryDReg", post, writeback)
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emitLoad(name, Name, False, eaCode, accCode,
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class LoadDoubleReg(LoadRegInst, LoadDouble):
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["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"],
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decConstBase = 'LoadStoreDReg'
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[], base, double=True)
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basePrefix = 'MemoryDReg'
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nameFunc = staticmethod(loadDoubleRegClassName)
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def buildLoads(mnem, size=4, sign=False, user=False):
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def buildLoads(mnem, size=4, sign=False, user=False):
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buildImmLoad(mnem, True, True, True, size, sign, user)
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LoadImm(mnem, True, True, True, size, sign, user).emit()
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buildRegLoad(mnem, True, True, True, size, sign, user)
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LoadReg(mnem, True, True, True, size, sign, user).emit()
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buildImmLoad(mnem, True, False, True, size, sign, user)
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LoadImm(mnem, True, False, True, size, sign, user).emit()
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buildRegLoad(mnem, True, False, True, size, sign, user)
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LoadReg(mnem, True, False, True, size, sign, user).emit()
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buildImmLoad(mnem, False, True, True, size, sign, user)
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LoadImm(mnem, False, True, True, size, sign, user).emit()
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buildRegLoad(mnem, False, True, True, size, sign, user)
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LoadReg(mnem, False, True, True, size, sign, user).emit()
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||||||
buildImmLoad(mnem, False, False, True, size, sign, user)
|
LoadImm(mnem, False, False, True, size, sign, user).emit()
|
||||||
buildRegLoad(mnem, False, False, True, size, sign, user)
|
LoadReg(mnem, False, False, True, size, sign, user).emit()
|
||||||
buildImmLoad(mnem, False, True, False, size, sign, user)
|
LoadImm(mnem, False, True, False, size, sign, user).emit()
|
||||||
buildRegLoad(mnem, False, True, False, size, sign, user)
|
LoadReg(mnem, False, True, False, size, sign, user).emit()
|
||||||
buildImmLoad(mnem, False, False, False, size, sign, user)
|
LoadImm(mnem, False, False, False, size, sign, user).emit()
|
||||||
buildRegLoad(mnem, False, False, False, size, sign, user)
|
LoadReg(mnem, False, False, False, size, sign, user).emit()
|
||||||
|
|
||||||
def buildDoubleLoads(mnem):
|
def buildDoubleLoads(mnem):
|
||||||
buildDoubleImmLoad(mnem, True, True, True)
|
LoadDoubleImm(mnem, True, True, True).emit()
|
||||||
buildDoubleRegLoad(mnem, True, True, True)
|
LoadDoubleReg(mnem, True, True, True).emit()
|
||||||
buildDoubleImmLoad(mnem, True, False, True)
|
LoadDoubleImm(mnem, True, False, True).emit()
|
||||||
buildDoubleRegLoad(mnem, True, False, True)
|
LoadDoubleReg(mnem, True, False, True).emit()
|
||||||
buildDoubleImmLoad(mnem, False, True, True)
|
LoadDoubleImm(mnem, False, True, True).emit()
|
||||||
buildDoubleRegLoad(mnem, False, True, True)
|
LoadDoubleReg(mnem, False, True, True).emit()
|
||||||
buildDoubleImmLoad(mnem, False, False, True)
|
LoadDoubleImm(mnem, False, False, True).emit()
|
||||||
buildDoubleRegLoad(mnem, False, False, True)
|
LoadDoubleReg(mnem, False, False, True).emit()
|
||||||
buildDoubleImmLoad(mnem, False, True, False)
|
LoadDoubleImm(mnem, False, True, False).emit()
|
||||||
buildDoubleRegLoad(mnem, False, True, False)
|
LoadDoubleReg(mnem, False, True, False).emit()
|
||||||
buildDoubleImmLoad(mnem, False, False, False)
|
LoadDoubleImm(mnem, False, False, False).emit()
|
||||||
buildDoubleRegLoad(mnem, False, False, False)
|
LoadDoubleReg(mnem, False, False, False).emit()
|
||||||
|
|
||||||
def buildRfeLoads(mnem):
|
def buildRfeLoads(mnem):
|
||||||
buildRfeLoad(mnem, True, True, True)
|
RfeInst(mnem, True, True, True).emit()
|
||||||
buildRfeLoad(mnem, True, True, False)
|
RfeInst(mnem, True, True, False).emit()
|
||||||
buildRfeLoad(mnem, True, False, True)
|
RfeInst(mnem, True, False, True).emit()
|
||||||
buildRfeLoad(mnem, True, False, False)
|
RfeInst(mnem, True, False, False).emit()
|
||||||
buildRfeLoad(mnem, False, True, True)
|
RfeInst(mnem, False, True, True).emit()
|
||||||
buildRfeLoad(mnem, False, True, False)
|
RfeInst(mnem, False, True, False).emit()
|
||||||
buildRfeLoad(mnem, False, False, True)
|
RfeInst(mnem, False, False, True).emit()
|
||||||
buildRfeLoad(mnem, False, False, False)
|
RfeInst(mnem, False, False, False).emit()
|
||||||
|
|
||||||
def buildPrefetches(mnem):
|
def buildPrefetches(mnem):
|
||||||
buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
|
LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit()
|
||||||
buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
|
LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit()
|
||||||
buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
|
LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit()
|
||||||
buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
|
LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit()
|
||||||
|
|
||||||
buildLoads("ldr")
|
buildLoads("ldr")
|
||||||
buildLoads("ldrt", user=True)
|
buildLoads("ldrt", user=True)
|
||||||
|
|
@ -342,13 +322,13 @@ let {{
|
||||||
buildPrefetches("pldw")
|
buildPrefetches("pldw")
|
||||||
buildPrefetches("pli")
|
buildPrefetches("pli")
|
||||||
|
|
||||||
buildImmLoad("ldrex", False, True, False, size=4, ldrex=True)
|
LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
|
||||||
buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True)
|
LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()
|
||||||
buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True)
|
LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit()
|
||||||
buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True)
|
LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit()
|
||||||
|
|
||||||
buildImmLoad("vldr", False, True, False, size=4, vldr=True)
|
LoadImm("vldr", False, True, False, size=4, flavor="fp").emit()
|
||||||
buildImmLoad("vldr", False, False, False, size=4, vldr=True)
|
LoadImm("vldr", False, False, False, size=4, flavor="fp").emit()
|
||||||
buildDoubleImmLoad("vldr", False, True, False, vldr=True)
|
LoadDoubleImm("vldr", False, True, False, flavor="fp").emit()
|
||||||
buildDoubleImmLoad("vldr", False, False, False, vldr=True)
|
LoadDoubleImm("vldr", False, False, False, flavor="fp").emit()
|
||||||
}};
|
}};
|
||||||
|
|
|
||||||
|
|
@ -38,9 +38,17 @@
|
||||||
// Authors: Gabe Black
|
// Authors: Gabe Black
|
||||||
|
|
||||||
let {{
|
let {{
|
||||||
def loadStoreBaseWork(name, Name, imm, swp, rfe, srs, codeBlobs,
|
|
||||||
memFlags, instFlags, double, strex,
|
class LoadStoreInst(object):
|
||||||
base = 'Memory', execTemplateBase = ''):
|
def __init__(self):
|
||||||
|
self.fullExecTemplate = eval(self.execBase + 'Execute')
|
||||||
|
self.initiateAccTemplate = eval(self.execBase + 'InitiateAcc')
|
||||||
|
self.completeAccTemplate = eval(self.execBase + 'CompleteAcc')
|
||||||
|
self.declareTemplate = eval(self.decConstBase + 'Declare')
|
||||||
|
self.constructTemplate = eval(self.decConstBase + 'Constructor')
|
||||||
|
|
||||||
|
def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
|
||||||
|
base = 'Memory'):
|
||||||
# Make sure flags are in lists (convert to lists if not).
|
# Make sure flags are in lists (convert to lists if not).
|
||||||
memFlags = makeList(memFlags)
|
memFlags = makeList(memFlags)
|
||||||
instFlags = makeList(instFlags)
|
instFlags = makeList(instFlags)
|
||||||
|
|
@ -56,46 +64,12 @@ let {{
|
||||||
|
|
||||||
iop = InstObjParams(name, Name, base, codeBlobs, instFlags)
|
iop = InstObjParams(name, Name, base, codeBlobs, instFlags)
|
||||||
|
|
||||||
fullExecTemplate = eval(execTemplateBase + 'Execute')
|
|
||||||
initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc')
|
|
||||||
completeAccTemplate = eval(execTemplateBase + 'CompleteAcc')
|
|
||||||
|
|
||||||
if swp:
|
|
||||||
declareTemplate = SwapDeclare
|
|
||||||
constructTemplate = SwapConstructor
|
|
||||||
elif rfe:
|
|
||||||
declareTemplate = RfeDeclare
|
|
||||||
constructTemplate = RfeConstructor
|
|
||||||
elif srs:
|
|
||||||
declareTemplate = SrsDeclare
|
|
||||||
constructTemplate = SrsConstructor
|
|
||||||
elif imm:
|
|
||||||
if double:
|
|
||||||
declareTemplate = LoadStoreDImmDeclare
|
|
||||||
constructTemplate = LoadStoreDImmConstructor
|
|
||||||
if strex:
|
|
||||||
declareTemplate = StoreExDImmDeclare
|
|
||||||
constructTemplate = StoreExDImmConstructor
|
|
||||||
elif strex:
|
|
||||||
declareTemplate = StoreExImmDeclare
|
|
||||||
constructTemplate = StoreExImmConstructor
|
|
||||||
else:
|
|
||||||
declareTemplate = LoadStoreImmDeclare
|
|
||||||
constructTemplate = LoadStoreImmConstructor
|
|
||||||
else:
|
|
||||||
if double:
|
|
||||||
declareTemplate = LoadStoreDRegDeclare
|
|
||||||
constructTemplate = LoadStoreDRegConstructor
|
|
||||||
else:
|
|
||||||
declareTemplate = LoadStoreRegDeclare
|
|
||||||
constructTemplate = LoadStoreRegConstructor
|
|
||||||
|
|
||||||
# (header_output, decoder_output, decode_block, exec_output)
|
# (header_output, decoder_output, decode_block, exec_output)
|
||||||
return (declareTemplate.subst(iop),
|
return (self.declareTemplate.subst(iop),
|
||||||
constructTemplate.subst(iop),
|
self.constructTemplate.subst(iop),
|
||||||
fullExecTemplate.subst(iop)
|
self.fullExecTemplate.subst(iop)
|
||||||
+ initiateAccTemplate.subst(iop)
|
+ self.initiateAccTemplate.subst(iop)
|
||||||
+ completeAccTemplate.subst(iop))
|
+ self.completeAccTemplate.subst(iop))
|
||||||
|
|
||||||
def pickPredicate(blobs):
|
def pickPredicate(blobs):
|
||||||
for val in blobs.values():
|
for val in blobs.values():
|
||||||
|
|
@ -103,75 +77,21 @@ let {{
|
||||||
return condPredicateTest
|
return condPredicateTest
|
||||||
return predicateTest
|
return predicateTest
|
||||||
|
|
||||||
def loadStoreBase(name, Name, imm, eaCode, accCode, postAccCode,
|
|
||||||
memFlags, instFlags, double, strex, base = 'Memory',
|
|
||||||
execTemplateBase = ''):
|
|
||||||
codeBlobs = { "ea_code": eaCode,
|
|
||||||
"memacc_code": accCode,
|
|
||||||
"postacc_code": postAccCode }
|
|
||||||
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
|
||||||
return loadStoreBaseWork(name, Name, imm, False, False, False,
|
|
||||||
codeBlobs, memFlags, instFlags, double,
|
|
||||||
strex, base, execTemplateBase)
|
|
||||||
|
|
||||||
def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
|
|
||||||
codeBlobs = { "ea_code": eaCode,
|
|
||||||
"memacc_code": accCode }
|
|
||||||
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
|
||||||
return loadStoreBaseWork(name, Name, False, False, True, False,
|
|
||||||
codeBlobs, memFlags, instFlags, False, False,
|
|
||||||
'RfeOp', 'Load')
|
|
||||||
|
|
||||||
def SrsBase(name, Name, eaCode, accCode, memFlags, instFlags):
|
|
||||||
codeBlobs = { "ea_code": eaCode,
|
|
||||||
"memacc_code": accCode,
|
|
||||||
"postacc_code": "" }
|
|
||||||
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
|
||||||
return loadStoreBaseWork(name, Name, False, False, False, True,
|
|
||||||
codeBlobs, memFlags, instFlags, False, False,
|
|
||||||
'SrsOp', 'Store')
|
|
||||||
|
|
||||||
def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
|
|
||||||
instFlags):
|
|
||||||
codeBlobs = { "ea_code": eaCode,
|
|
||||||
"preacc_code": preAccCode,
|
|
||||||
"postacc_code": postAccCode }
|
|
||||||
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
|
||||||
return loadStoreBaseWork(name, Name, False, True, False, False,
|
|
||||||
codeBlobs, memFlags, instFlags, False, False,
|
|
||||||
'Swap', 'Swap')
|
|
||||||
|
|
||||||
def memClassName(base, post, add, writeback, \
|
def memClassName(base, post, add, writeback, \
|
||||||
size=4, sign=False, user=False):
|
size=4, sign=False, user=False):
|
||||||
Name = base
|
Name = base
|
||||||
|
|
||||||
if post:
|
parts = { "P" : post, "A" : add, "W" : writeback,
|
||||||
Name += '_PY'
|
"S" : sign, "U" : user }
|
||||||
else:
|
|
||||||
Name += '_PN'
|
|
||||||
|
|
||||||
if add:
|
for (letter, val) in parts.items():
|
||||||
Name += '_AY'
|
if val:
|
||||||
|
Name += "_%sY" % letter
|
||||||
else:
|
else:
|
||||||
Name += '_AN'
|
Name += "_%sN" % letter
|
||||||
|
|
||||||
if writeback:
|
|
||||||
Name += '_WY'
|
|
||||||
else:
|
|
||||||
Name += '_WN'
|
|
||||||
|
|
||||||
Name += ('_SZ%d' % size)
|
Name += ('_SZ%d' % size)
|
||||||
|
|
||||||
if sign:
|
|
||||||
Name += '_SY'
|
|
||||||
else:
|
|
||||||
Name += '_SN'
|
|
||||||
|
|
||||||
if user:
|
|
||||||
Name += '_UY'
|
|
||||||
else:
|
|
||||||
Name += '_UN'
|
|
||||||
|
|
||||||
return Name
|
return Name
|
||||||
|
|
||||||
def buildMemSuffix(sign, size):
|
def buildMemSuffix(sign, size):
|
||||||
|
|
@ -188,7 +108,7 @@ let {{
|
||||||
else:
|
else:
|
||||||
memSuffix = '.ub'
|
memSuffix = '.ub'
|
||||||
else:
|
else:
|
||||||
raise Exception, "Unrecognized size for load %d" % size
|
raise Exception, "Unrecognized size for access %d" % size
|
||||||
|
|
||||||
return memSuffix
|
return memSuffix
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -43,176 +43,206 @@ let {{
|
||||||
decoder_output = ""
|
decoder_output = ""
|
||||||
exec_output = ""
|
exec_output = ""
|
||||||
|
|
||||||
def storeImmClassName(post, add, writeback, \
|
class StoreInst(LoadStoreInst):
|
||||||
size=4, sign=False, user=False):
|
execBase = 'Store'
|
||||||
return memClassName("STORE_IMM", post, add, writeback,
|
|
||||||
size, sign, user)
|
|
||||||
|
|
||||||
def storeRegClassName(post, add, writeback, \
|
def __init__(self, mnem, post, add, writeback, size=4,
|
||||||
size=4, sign=False, user=False):
|
sign=False, user=False, flavor="normal"):
|
||||||
return memClassName("STORE_REG", post, add, writeback,
|
super(StoreInst, self).__init__()
|
||||||
size, sign, user)
|
|
||||||
|
|
||||||
def storeDoubleImmClassName(post, add, writeback):
|
self.name = mnem
|
||||||
return memClassName("STORE_IMMD", post, add, writeback,
|
self.post = post
|
||||||
4, False, False)
|
self.add = add
|
||||||
|
self.writeback = writeback
|
||||||
|
self.size = size
|
||||||
|
self.sign = sign
|
||||||
|
self.user = user
|
||||||
|
self.flavor = flavor
|
||||||
|
|
||||||
def storeDoubleRegClassName(post, add, writeback):
|
if self.add:
|
||||||
return memClassName("STORE_REGD", post, add, writeback,
|
self.op = " +"
|
||||||
4, False, False)
|
else:
|
||||||
|
self.op = " -"
|
||||||
|
|
||||||
|
self.memFlags = ["ArmISA::TLB::MustBeOne"]
|
||||||
|
self.codeBlobs = { "postacc_code" : "" }
|
||||||
|
|
||||||
|
def emitHelper(self, base = 'Memory'):
|
||||||
|
|
||||||
def emitStore(name, Name, imm, eaCode, accCode, postAccCode, \
|
|
||||||
memFlags, instFlags, base, double=False, strex=False,
|
|
||||||
execTemplateBase = 'Store'):
|
|
||||||
global header_output, decoder_output, exec_output
|
global header_output, decoder_output, exec_output
|
||||||
|
|
||||||
|
codeBlobs = self.codeBlobs
|
||||||
|
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
||||||
(newHeader,
|
(newHeader,
|
||||||
newDecoder,
|
newDecoder,
|
||||||
newExec) = loadStoreBase(name, Name, imm,
|
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
|
||||||
eaCode, accCode, postAccCode,
|
self.memFlags, [], base)
|
||||||
memFlags, instFlags, double, strex,
|
|
||||||
base, execTemplateBase = execTemplateBase)
|
|
||||||
|
|
||||||
header_output += newHeader
|
header_output += newHeader
|
||||||
decoder_output += newDecoder
|
decoder_output += newDecoder
|
||||||
exec_output += newExec
|
exec_output += newExec
|
||||||
|
|
||||||
def buildImmStore(mnem, post, add, writeback, \
|
class SrsInst(LoadStoreInst):
|
||||||
size=4, sign=False, user=False, \
|
execBase = 'Store'
|
||||||
strex=False, vstr=False):
|
decConstBase = 'Srs'
|
||||||
name = mnem
|
|
||||||
Name = storeImmClassName(post, add, writeback, \
|
|
||||||
size, sign, user)
|
|
||||||
|
|
||||||
if add:
|
def __init__(self, mnem, post, add, writeback):
|
||||||
op = " +"
|
super(SrsInst, self).__init__()
|
||||||
else:
|
self.name = mnem
|
||||||
op = " -"
|
self.post = post
|
||||||
|
self.add = add
|
||||||
|
self.writeback = writeback
|
||||||
|
|
||||||
offset = op + " imm"
|
self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
|
||||||
eaCode = "EA = Base"
|
|
||||||
if not post:
|
|
||||||
eaCode += offset
|
|
||||||
eaCode += ";"
|
|
||||||
|
|
||||||
if vstr:
|
|
||||||
accCode = '''
|
|
||||||
Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);
|
|
||||||
''' % { "suffix" : buildMemSuffix(sign, size) }
|
|
||||||
else:
|
|
||||||
accCode = '''
|
|
||||||
Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);
|
|
||||||
''' % { "suffix" : buildMemSuffix(sign, size) }
|
|
||||||
if writeback:
|
|
||||||
accCode += "Base = Base %s;\n" % offset
|
|
||||||
|
|
||||||
memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
|
|
||||||
if user:
|
|
||||||
memFlags.append("ArmISA::TLB::UserMode")
|
|
||||||
|
|
||||||
if strex:
|
|
||||||
memFlags.append("Request::LLSC")
|
|
||||||
Name = "%s_%s" % (mnem.upper(), Name)
|
|
||||||
base = buildMemBase("MemoryExImm", post, writeback)
|
|
||||||
postAccCode = "Result = !writeResult;"
|
|
||||||
execTemplateBase = 'StoreEx'
|
|
||||||
else:
|
|
||||||
if vstr:
|
|
||||||
Name = "%s_%s" % (mnem.upper(), Name)
|
|
||||||
else:
|
|
||||||
memFlags.append("ArmISA::TLB::AllowUnaligned")
|
|
||||||
base = buildMemBase("MemoryImm", post, writeback)
|
|
||||||
postAccCode = ""
|
|
||||||
execTemplateBase = 'Store'
|
|
||||||
|
|
||||||
emitStore(name, Name, True, eaCode, accCode, postAccCode, \
|
|
||||||
memFlags, [], base, strex=strex,
|
|
||||||
execTemplateBase = execTemplateBase)
|
|
||||||
|
|
||||||
def buildSrsStore(mnem, post, add, writeback):
|
|
||||||
name = mnem
|
|
||||||
Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
|
|
||||||
|
|
||||||
|
def emit(self):
|
||||||
offset = 0
|
offset = 0
|
||||||
if post != add:
|
if self.post != self.add:
|
||||||
offset += 4
|
offset += 4
|
||||||
if not add:
|
if not self.add:
|
||||||
offset -= 8
|
offset -= 8
|
||||||
|
|
||||||
eaCode = "EA = SpMode + %d;" % offset
|
eaCode = "EA = SpMode + %d;" % offset
|
||||||
|
|
||||||
wbDiff = -8
|
wbDiff = -8
|
||||||
if add:
|
if self.add:
|
||||||
wbDiff = 8
|
wbDiff = 8
|
||||||
accCode = '''
|
accCode = '''
|
||||||
CPSR cpsr = Cpsr;
|
CPSR cpsr = Cpsr;
|
||||||
Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
|
Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
|
||||||
((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
|
((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
|
||||||
'''
|
'''
|
||||||
if writeback:
|
if self.writeback:
|
||||||
accCode += "SpMode = SpMode + %s;\n" % wbDiff
|
accCode += "SpMode = SpMode + %s;\n" % wbDiff
|
||||||
|
|
||||||
global header_output, decoder_output, exec_output
|
global header_output, decoder_output, exec_output
|
||||||
|
|
||||||
|
codeBlobs = { "ea_code": eaCode,
|
||||||
|
"memacc_code": accCode,
|
||||||
|
"postacc_code": "" }
|
||||||
|
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
||||||
|
|
||||||
(newHeader,
|
(newHeader,
|
||||||
newDecoder,
|
newDecoder,
|
||||||
newExec) = SrsBase(name, Name, eaCode, accCode,
|
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
|
||||||
["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [])
|
["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
|
||||||
|
base = 'SrsOp')
|
||||||
|
|
||||||
header_output += newHeader
|
header_output += newHeader
|
||||||
decoder_output += newDecoder
|
decoder_output += newDecoder
|
||||||
exec_output += newExec
|
exec_output += newExec
|
||||||
|
|
||||||
def buildRegStore(mnem, post, add, writeback, \
|
class StoreImmInst(StoreInst):
|
||||||
size=4, sign=False, user=False, strex=False):
|
def __init__(self, *args, **kargs):
|
||||||
name = mnem
|
super(StoreImmInst, self).__init__(*args, **kargs)
|
||||||
Name = storeRegClassName(post, add, writeback,
|
self.offset = self.op + " imm"
|
||||||
size, sign, user)
|
|
||||||
|
|
||||||
if add:
|
class StoreRegInst(StoreInst):
|
||||||
op = " +"
|
def __init__(self, *args, **kargs):
|
||||||
else:
|
super(StoreRegInst, self).__init__(*args, **kargs)
|
||||||
op = " -"
|
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
|
||||||
|
|
||||||
offset = op + " shift_rm_imm(Index, shiftAmt," + \
|
|
||||||
" shiftType, CondCodes<29:>)"
|
" shiftType, CondCodes<29:>)"
|
||||||
|
|
||||||
|
class StoreSingle(StoreInst):
|
||||||
|
def __init__(self, *args, **kargs):
|
||||||
|
super(StoreSingle, self).__init__(*args, **kargs)
|
||||||
|
|
||||||
|
# Build the default class name
|
||||||
|
self.Name = self.nameFunc(self.post, self.add, self.writeback,
|
||||||
|
self.size, self.sign, self.user)
|
||||||
|
|
||||||
|
# Add memory request flags where necessary
|
||||||
|
self.memFlags.append("%d" % (self.size - 1))
|
||||||
|
if self.user:
|
||||||
|
self.memFlags.append("ArmISA::TLB::UserMode")
|
||||||
|
|
||||||
|
if self.flavor == "exclusive":
|
||||||
|
self.memFlags.append("Request::LLSC")
|
||||||
|
elif self.flavor != "fp":
|
||||||
|
self.memFlags.append("ArmISA::TLB::AllowUnaligned")
|
||||||
|
|
||||||
|
# Disambiguate the class name for different flavors of stores
|
||||||
|
if self.flavor != "normal":
|
||||||
|
self.Name = "%s_%s" % (self.name.upper(), self.Name)
|
||||||
|
|
||||||
|
def emit(self):
|
||||||
|
# Address computation
|
||||||
eaCode = "EA = Base"
|
eaCode = "EA = Base"
|
||||||
if not post:
|
if not self.post:
|
||||||
eaCode += offset
|
eaCode += self.offset
|
||||||
eaCode += ";"
|
eaCode += ";"
|
||||||
|
self.codeBlobs["ea_code"] = eaCode
|
||||||
|
|
||||||
accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
|
# Code that actually handles the access
|
||||||
{ "suffix" : buildMemSuffix(sign, size) }
|
if self.flavor == "fp":
|
||||||
if writeback:
|
accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
|
||||||
accCode += "Base = Base %s;\n" % offset
|
|
||||||
base = buildMemBase("MemoryReg", post, writeback)
|
|
||||||
|
|
||||||
memFlags = ["ArmISA::TLB::MustBeOne", \
|
|
||||||
"ArmISA::TLB::AllowUnaligned", \
|
|
||||||
"%d" % (size - 1)]
|
|
||||||
if user:
|
|
||||||
memFlags.append("ArmISA::TLB::UserMode")
|
|
||||||
|
|
||||||
emitStore(name, Name, False, eaCode, accCode, "",\
|
|
||||||
memFlags, [], base)
|
|
||||||
|
|
||||||
def buildDoubleImmStore(mnem, post, add, writeback, \
|
|
||||||
strex=False, vstr=False):
|
|
||||||
name = mnem
|
|
||||||
Name = storeDoubleImmClassName(post, add, writeback)
|
|
||||||
|
|
||||||
if add:
|
|
||||||
op = " +"
|
|
||||||
else:
|
else:
|
||||||
op = " -"
|
accCode = \
|
||||||
|
'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
|
||||||
|
accCode = accCode % \
|
||||||
|
{ "suffix" : buildMemSuffix(self.sign, self.size) }
|
||||||
|
|
||||||
offset = op + " imm"
|
if self.writeback:
|
||||||
|
accCode += "Base = Base %s;\n" % self.offset
|
||||||
|
|
||||||
|
self.codeBlobs["memacc_code"] = accCode
|
||||||
|
|
||||||
|
# Push it out to the output files
|
||||||
|
base = buildMemBase(self.basePrefix, self.post, self.writeback)
|
||||||
|
self.emitHelper(base)
|
||||||
|
|
||||||
|
def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
|
||||||
|
return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
|
||||||
|
|
||||||
|
class StoreImmEx(StoreImmInst, StoreSingle):
|
||||||
|
execBase = 'StoreEx'
|
||||||
|
decConstBase = 'StoreExImm'
|
||||||
|
basePrefix = 'MemoryExImm'
|
||||||
|
nameFunc = staticmethod(storeImmClassName)
|
||||||
|
|
||||||
|
def __init__(self, *args, **kargs):
|
||||||
|
super(StoreImmEx, self).__init__(*args, **kargs)
|
||||||
|
self.codeBlobs["postacc_code"] = "Result = !writeResult;"
|
||||||
|
|
||||||
|
class StoreImm(StoreImmInst, StoreSingle):
|
||||||
|
decConstBase = 'LoadStoreImm'
|
||||||
|
basePrefix = 'MemoryImm'
|
||||||
|
nameFunc = staticmethod(storeImmClassName)
|
||||||
|
|
||||||
|
def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
|
||||||
|
return memClassName("STORE_REG", post, add, writeback, size, sign, user)
|
||||||
|
|
||||||
|
class StoreReg(StoreRegInst, StoreSingle):
|
||||||
|
decConstBase = 'LoadStoreReg'
|
||||||
|
basePrefix = 'MemoryReg'
|
||||||
|
nameFunc = staticmethod(storeRegClassName)
|
||||||
|
|
||||||
|
class StoreDouble(StoreInst):
|
||||||
|
def __init__(self, *args, **kargs):
|
||||||
|
super(StoreDouble, self).__init__(*args, **kargs)
|
||||||
|
|
||||||
|
# Build the default class name
|
||||||
|
self.Name = self.nameFunc(self.post, self.add, self.writeback)
|
||||||
|
|
||||||
|
# Add memory request flags where necessary
|
||||||
|
self.memFlags.append("ArmISA::TLB::AlignWord")
|
||||||
|
if self.flavor == "exclusive":
|
||||||
|
self.memFlags.append("Request::LLSC")
|
||||||
|
|
||||||
|
# Disambiguate the class name for different flavors of stores
|
||||||
|
if self.flavor != "normal":
|
||||||
|
self.Name = "%s_%s" % (self.name.upper(), self.Name)
|
||||||
|
|
||||||
|
def emit(self):
|
||||||
|
# Address computation code
|
||||||
eaCode = "EA = Base"
|
eaCode = "EA = Base"
|
||||||
if not post:
|
if not self.post:
|
||||||
eaCode += offset
|
eaCode += self.offset
|
||||||
eaCode += ";"
|
eaCode += ";"
|
||||||
|
self.codeBlobs["ea_code"] = eaCode
|
||||||
|
|
||||||
if vstr:
|
# Code that actually handles the access
|
||||||
|
if self.flavor == "fp":
|
||||||
accCode = '''
|
accCode = '''
|
||||||
uint64_t swappedMem = (uint64_t)FpDest.uw |
|
uint64_t swappedMem = (uint64_t)FpDest.uw |
|
||||||
((uint64_t)FpDest2.uw << 32);
|
((uint64_t)FpDest2.uw << 32);
|
||||||
|
|
@ -224,92 +254,79 @@ let {{
|
||||||
Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
|
Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
|
||||||
((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
|
((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
|
||||||
'''
|
'''
|
||||||
if writeback:
|
|
||||||
accCode += "Base = Base %s;\n" % offset
|
|
||||||
|
|
||||||
memFlags = ["ArmISA::TLB::MustBeOne",
|
if self.writeback:
|
||||||
"ArmISA::TLB::AlignWord"]
|
accCode += "Base = Base %s;\n" % self.offset
|
||||||
if strex:
|
|
||||||
memFlags.append("Request::LLSC")
|
|
||||||
base = buildMemBase("MemoryExDImm", post, writeback)
|
|
||||||
postAccCode = "Result = !writeResult;"
|
|
||||||
else:
|
|
||||||
base = buildMemBase("MemoryDImm", post, writeback)
|
|
||||||
postAccCode = ""
|
|
||||||
if vstr or strex:
|
|
||||||
Name = "%s_%s" % (mnem.upper(), Name)
|
|
||||||
|
|
||||||
emitStore(name, Name, True, eaCode, accCode, postAccCode, \
|
self.codeBlobs["memacc_code"] = accCode
|
||||||
memFlags, [], base, double=True, strex=strex)
|
|
||||||
|
|
||||||
def buildDoubleRegStore(mnem, post, add, writeback):
|
# Push it out to the output files
|
||||||
name = mnem
|
base = buildMemBase(self.basePrefix, self.post, self.writeback)
|
||||||
Name = storeDoubleRegClassName(post, add, writeback)
|
self.emitHelper(base)
|
||||||
|
|
||||||
if add:
|
def storeDoubleImmClassName(post, add, writeback):
|
||||||
op = " +"
|
return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
|
||||||
else:
|
|
||||||
op = " -"
|
|
||||||
|
|
||||||
offset = op + " shift_rm_imm(Index, shiftAmt," + \
|
class StoreDoubleImmEx(StoreImmInst, StoreDouble):
|
||||||
" shiftType, CondCodes<29:>)"
|
execBase = 'StoreEx'
|
||||||
eaCode = "EA = Base"
|
decConstBase = 'StoreExDImm'
|
||||||
if not post:
|
basePrefix = 'MemoryExDImm'
|
||||||
eaCode += offset
|
nameFunc = staticmethod(storeDoubleImmClassName)
|
||||||
eaCode += ";"
|
|
||||||
|
|
||||||
accCode = '''
|
def __init__(self, *args, **kargs):
|
||||||
CPSR cpsr = Cpsr;
|
super(StoreDoubleImmEx, self).__init__(*args, **kargs)
|
||||||
Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
|
self.codeBlobs["postacc_code"] = "Result = !writeResult;"
|
||||||
((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
|
|
||||||
'''
|
|
||||||
if writeback:
|
|
||||||
accCode += "Base = Base %s;\n" % offset
|
|
||||||
base = buildMemBase("MemoryDReg", post, writeback)
|
|
||||||
|
|
||||||
memFlags = ["ArmISA::TLB::MustBeOne",
|
class StoreDoubleImm(StoreImmInst, StoreDouble):
|
||||||
"ArmISA::TLB::AlignWord"]
|
decConstBase = 'LoadStoreDImm'
|
||||||
|
basePrefix = 'MemoryDImm'
|
||||||
|
nameFunc = staticmethod(storeDoubleImmClassName)
|
||||||
|
|
||||||
emitStore(name, Name, False, eaCode, accCode, "", \
|
def storeDoubleRegClassName(post, add, writeback):
|
||||||
memFlags, [], base, double=True)
|
return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
|
||||||
|
|
||||||
|
class StoreDoubleReg(StoreRegInst, StoreDouble):
|
||||||
|
decConstBase = 'LoadStoreDReg'
|
||||||
|
basePrefix = 'MemoryDReg'
|
||||||
|
nameFunc = staticmethod(storeDoubleRegClassName)
|
||||||
|
|
||||||
def buildStores(mnem, size=4, sign=False, user=False):
|
def buildStores(mnem, size=4, sign=False, user=False):
|
||||||
buildImmStore(mnem, True, True, True, size, sign, user)
|
StoreImm(mnem, True, True, True, size, sign, user).emit()
|
||||||
buildRegStore(mnem, True, True, True, size, sign, user)
|
StoreReg(mnem, True, True, True, size, sign, user).emit()
|
||||||
buildImmStore(mnem, True, False, True, size, sign, user)
|
StoreImm(mnem, True, False, True, size, sign, user).emit()
|
||||||
buildRegStore(mnem, True, False, True, size, sign, user)
|
StoreReg(mnem, True, False, True, size, sign, user).emit()
|
||||||
buildImmStore(mnem, False, True, True, size, sign, user)
|
StoreImm(mnem, False, True, True, size, sign, user).emit()
|
||||||
buildRegStore(mnem, False, True, True, size, sign, user)
|
StoreReg(mnem, False, True, True, size, sign, user).emit()
|
||||||
buildImmStore(mnem, False, False, True, size, sign, user)
|
StoreImm(mnem, False, False, True, size, sign, user).emit()
|
||||||
buildRegStore(mnem, False, False, True, size, sign, user)
|
StoreReg(mnem, False, False, True, size, sign, user).emit()
|
||||||
buildImmStore(mnem, False, True, False, size, sign, user)
|
StoreImm(mnem, False, True, False, size, sign, user).emit()
|
||||||
buildRegStore(mnem, False, True, False, size, sign, user)
|
StoreReg(mnem, False, True, False, size, sign, user).emit()
|
||||||
buildImmStore(mnem, False, False, False, size, sign, user)
|
StoreImm(mnem, False, False, False, size, sign, user).emit()
|
||||||
buildRegStore(mnem, False, False, False, size, sign, user)
|
StoreReg(mnem, False, False, False, size, sign, user).emit()
|
||||||
|
|
||||||
def buildDoubleStores(mnem):
|
def buildDoubleStores(mnem):
|
||||||
buildDoubleImmStore(mnem, True, True, True)
|
StoreDoubleImm(mnem, True, True, True).emit()
|
||||||
buildDoubleRegStore(mnem, True, True, True)
|
StoreDoubleReg(mnem, True, True, True).emit()
|
||||||
buildDoubleImmStore(mnem, True, False, True)
|
StoreDoubleImm(mnem, True, False, True).emit()
|
||||||
buildDoubleRegStore(mnem, True, False, True)
|
StoreDoubleReg(mnem, True, False, True).emit()
|
||||||
buildDoubleImmStore(mnem, False, True, True)
|
StoreDoubleImm(mnem, False, True, True).emit()
|
||||||
buildDoubleRegStore(mnem, False, True, True)
|
StoreDoubleReg(mnem, False, True, True).emit()
|
||||||
buildDoubleImmStore(mnem, False, False, True)
|
StoreDoubleImm(mnem, False, False, True).emit()
|
||||||
buildDoubleRegStore(mnem, False, False, True)
|
StoreDoubleReg(mnem, False, False, True).emit()
|
||||||
buildDoubleImmStore(mnem, False, True, False)
|
StoreDoubleImm(mnem, False, True, False).emit()
|
||||||
buildDoubleRegStore(mnem, False, True, False)
|
StoreDoubleReg(mnem, False, True, False).emit()
|
||||||
buildDoubleImmStore(mnem, False, False, False)
|
StoreDoubleImm(mnem, False, False, False).emit()
|
||||||
buildDoubleRegStore(mnem, False, False, False)
|
StoreDoubleReg(mnem, False, False, False).emit()
|
||||||
|
|
||||||
def buildSrsStores(mnem):
|
def buildSrsStores(mnem):
|
||||||
buildSrsStore(mnem, True, True, True)
|
SrsInst(mnem, True, True, True).emit()
|
||||||
buildSrsStore(mnem, True, True, False)
|
SrsInst(mnem, True, True, False).emit()
|
||||||
buildSrsStore(mnem, True, False, True)
|
SrsInst(mnem, True, False, True).emit()
|
||||||
buildSrsStore(mnem, True, False, False)
|
SrsInst(mnem, True, False, False).emit()
|
||||||
buildSrsStore(mnem, False, True, True)
|
SrsInst(mnem, False, True, True).emit()
|
||||||
buildSrsStore(mnem, False, True, False)
|
SrsInst(mnem, False, True, False).emit()
|
||||||
buildSrsStore(mnem, False, False, True)
|
SrsInst(mnem, False, False, True).emit()
|
||||||
buildSrsStore(mnem, False, False, False)
|
SrsInst(mnem, False, False, False).emit()
|
||||||
|
|
||||||
buildStores("str")
|
buildStores("str")
|
||||||
buildStores("strt", user=True)
|
buildStores("strt", user=True)
|
||||||
|
|
@ -322,13 +339,13 @@ let {{
|
||||||
|
|
||||||
buildDoubleStores("strd")
|
buildDoubleStores("strd")
|
||||||
|
|
||||||
buildImmStore("strex", False, True, False, size=4, strex=True)
|
StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
|
||||||
buildImmStore("strexh", False, True, False, size=2, strex=True)
|
StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
|
||||||
buildImmStore("strexb", False, True, False, size=1, strex=True)
|
StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
|
||||||
buildDoubleImmStore("strexd", False, True, False, strex=True)
|
StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
|
||||||
|
|
||||||
buildImmStore("vstr", False, True, False, size=4, vstr=True)
|
StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
|
||||||
buildImmStore("vstr", False, False, False, size=4, vstr=True)
|
StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
|
||||||
buildDoubleImmStore("vstr", False, True, False, vstr=True)
|
StoreDoubleImm("vstr", False, True, False, flavor="fp").emit()
|
||||||
buildDoubleImmStore("vstr", False, False, False, vstr=True)
|
StoreDoubleImm("vstr", False, False, False, flavor="fp").emit()
|
||||||
}};
|
}};
|
||||||
|
|
|
||||||
|
|
@ -41,27 +41,46 @@ let {{
|
||||||
|
|
||||||
header_output = decoder_output = exec_output = ""
|
header_output = decoder_output = exec_output = ""
|
||||||
|
|
||||||
|
class SwapInst(LoadStoreInst):
|
||||||
|
execBase = 'Swap'
|
||||||
|
decConstBase = 'Swap'
|
||||||
|
|
||||||
|
def __init__(self, name, Name, eaCode,
|
||||||
|
preAccCode, postAccCode, memFlags):
|
||||||
|
super(SwapInst, self).__init__()
|
||||||
|
self.name = name
|
||||||
|
self.Name = Name
|
||||||
|
self.eaCode = eaCode
|
||||||
|
self.preAccCode = preAccCode
|
||||||
|
self.postAccCode = postAccCode
|
||||||
|
self.memFlags = memFlags
|
||||||
|
|
||||||
|
def emit(self):
|
||||||
|
global header_output, decoder_output, exec_output
|
||||||
|
codeBlobs = { "ea_code": self.eaCode,
|
||||||
|
"preacc_code": self.preAccCode,
|
||||||
|
"postacc_code": self.postAccCode }
|
||||||
|
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
|
||||||
|
|
||||||
(newHeader,
|
(newHeader,
|
||||||
newDecoder,
|
newDecoder,
|
||||||
newExec) = SwapBase("swp", "Swp", "EA = Base;",
|
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
|
||||||
"Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);",
|
self.memFlags, [], base = 'Swap')
|
||||||
"Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);",
|
|
||||||
["Request::MEM_SWAP",
|
|
||||||
"ArmISA::TLB::AlignWord",
|
|
||||||
"ArmISA::TLB::MustBeOne"], [])
|
|
||||||
header_output += newHeader
|
header_output += newHeader
|
||||||
decoder_output += newDecoder
|
decoder_output += newDecoder
|
||||||
exec_output += newExec
|
exec_output += newExec
|
||||||
|
|
||||||
(newHeader,
|
SwapInst('swp', 'Swp', 'EA = Base;',
|
||||||
newDecoder,
|
'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);',
|
||||||
newExec) = SwapBase("swpb", "Swpb", "EA = Base;",
|
'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
|
||||||
"Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);",
|
['Request::MEM_SWAP',
|
||||||
"Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);",
|
'ArmISA::TLB::AlignWord',
|
||||||
["Request::MEM_SWAP",
|
'ArmISA::TLB::MustBeOne']).emit()
|
||||||
"ArmISA::TLB::AlignByte",
|
|
||||||
"ArmISA::TLB::MustBeOne"], [])
|
SwapInst('swpb', 'Swpb', 'EA = Base;',
|
||||||
header_output += newHeader
|
'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
|
||||||
decoder_output += newDecoder
|
'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
|
||||||
exec_output += newExec
|
['Request::MEM_SWAP',
|
||||||
|
'ArmISA::TLB::AlignByte',
|
||||||
|
'ArmISA::TLB::MustBeOne']).emit()
|
||||||
}};
|
}};
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue