diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 36fe42115..6d78dd89d 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -231,6 +231,7 @@ def create_system(options, full_system, system, piobus = None, dma_ports = []): if buildEnv['TARGET_ISA'] == "x86": cpu_seq.pio_slave_port = piobus.master + ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks ruby._cpu_ports = cpu_sequencers ruby.num_of_sequencers = len(cpu_sequencers) diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc index 7decd497a..b3b37e5a6 100644 --- a/src/mem/ruby/profiler/Profiler.cc +++ b/src/mem/ruby/profiler/Profiler.cc @@ -61,11 +61,10 @@ using namespace std; using m5::stl_helpers::operator<<; Profiler::Profiler(const RubySystemParams *p, RubySystem *rs) - : m_ruby_system(rs) + : m_ruby_system(rs), m_hot_lines(p->hot_lines), + m_all_instructions(p->all_instructions), + m_num_vnets(p->number_of_virtual_networks) { - m_hot_lines = p->hot_lines; - m_all_instructions = p->all_instructions; - m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this); m_address_profiler_ptr->setHotLines(m_hot_lines); m_address_profiler_ptr->setAllInstructions(m_all_instructions); @@ -98,8 +97,7 @@ Profiler::regStats(const std::string &pName) .desc("delay histogram for all message") .flags(Stats::nozero | Stats::pdf | Stats::oneline); - uint32_t numVNets = Network::getNumberOfVirtualNetworks(); - for (int i = 0; i < numVNets; i++) { + for (int i = 0; i < m_num_vnets; i++) { delayVCHistogram.push_back(new Stats::Histogram()); delayVCHistogram[i] ->init(10) @@ -251,7 +249,6 @@ Profiler::collateStats() m_inst_profiler_ptr->collateStats(); } - uint32_t numVNets = Network::getNumberOfVirtualNetworks(); for (uint32_t i = 0; i < MachineType_NUM; i++) { for (map::iterator it = m_ruby_system->m_abstract_controls[i].begin(); @@ -260,7 +257,7 @@ Profiler::collateStats() AbstractController *ctr = (*it).second; delayHistogram.add(ctr->getDelayHist()); - for (uint32_t i = 0; i < numVNets; i++) { + for (uint32_t i = 0; i < m_num_vnets; i++) { delayVCHistogram[i]->add(ctr->getDelayVCHist(i)); } } diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 146beadd6..6cfdab1d5 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -80,8 +80,8 @@ class Profiler void addAddressTraceSample(const RubyRequest& msg, NodeID id); // added by SS - bool getHotLines() { return m_hot_lines; } - bool getAllInstructions() { return m_all_instructions; } + bool getHotLines() const { return m_hot_lines; } + bool getAllInstructions() const { return m_all_instructions; } private: // Private copy constructor and assignment operator @@ -129,8 +129,9 @@ class Profiler Stats::Scalar m_IncompleteTimes[MachineType_NUM]; //added by SS - bool m_hot_lines; - bool m_all_instructions; + const bool m_hot_lines; + const bool m_all_instructions; + const uint32_t m_num_vnets; }; #endif // __MEM_RUBY_PROFILER_PROFILER_HH__ diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py index c10f8117f..9ffaa5702 100644 --- a/src/mem/ruby/system/RubySystem.py +++ b/src/mem/ruby/system/RubySystem.py @@ -41,11 +41,13 @@ class RubySystem(ClockedObject): memory_size_bits = Param.UInt32(64, "number of bits that a memory address requires"); - # Profiler related configuration variables - hot_lines = Param.Bool(False, "") - all_instructions = Param.Bool(False, "") - num_of_sequencers = Param.Int("") phys_mem = Param.SimpleMemory(NULL, "") access_backing_store = Param.Bool(False, "Use phys_mem as the functional \ store and only use ruby for timing.") + + # Profiler related configuration variables + hot_lines = Param.Bool(False, "") + all_instructions = Param.Bool(False, "") + num_of_sequencers = Param.Int("") + number_of_virtual_networks = Param.Unsigned("")