Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df

build_opts/SPARC_FS

@@ -1,2 +1,3 @@
 TARGET_ISA = 'sparc'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
 FULL_SYSTEM = 1

build_opts/SPARC_SE

@@ -1,2 +1,3 @@
 TARGET_ISA = 'sparc'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
 FULL_SYSTEM = 0

src/cpu/o3/commit_impl.hh

@@ -1197,16 +1197,16 @@ DefaultCommit<Impl>::getInsts()
              rename_idx < fromRename->size;
              rename_idx++) {
             DynInstPtr inst = fromRename->insts[rename_idx];
-            int tid = inst->threadNumber;
 
             if (!inst->isSquashed()) {
                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
-                        "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
+                        inst->threadNumber);
                 skidBuffer.push(inst);
             } else {
                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
                         "squashed, skipping.\n",
-                        inst->readPC(), inst->seqNum, tid);
+                        inst->readPC(), inst->seqNum, inst->threadNumber);
             }
         }
     }

util/regress

@@ -43,7 +43,7 @@ optparser.add_option('--builds', dest='builds',
                      help='comma-separated list of build targets to test  '
                      " (default: '%default')" )
 optparser.add_option('--variants', dest='variants',
-                     default='opt',
+                     default='fast',
                      help='comma-separated list of build variants to test '
                      " (default: '%default')" )
 optparser.add_option('--scons-opts', dest='scons_opts', default='',