Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : cbf8da2fe5c4155d9ed8318597d543ff105449d3
This commit is contained in:
commit
cfa4221e19
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@ -877,6 +877,10 @@ class Tru64 {
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*configptr_ptr = config_addr;
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*configptr_ptr = config_addr;
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configptr_ptr.copyOut(xc->mem);
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configptr_ptr.copyOut(xc->mem);
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// Register this as a valid address range with the process
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process->nxm_start = base_addr;
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process->nxm_end = cur_addr;
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return 0;
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return 0;
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}
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}
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@ -5,12 +5,12 @@ if 'SYSTEM' not in env:
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if env['SYSTEM'] == 'Simple':
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if env['SYSTEM'] == 'Simple':
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from SimpleConfig import *
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from SimpleConfig import *
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BaseCPU.workload = Super.workload
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BaseCPU.workload = parent.workload
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SimpleStandAlone.cpu = [ CPU() for i in xrange(int(env['NP'])) ]
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SimpleStandAlone.cpu = [ CPU() for i in xrange(int(env['NP'])) ]
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root = SimpleStandAlone
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root = SimpleStandAlone
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elif env['SYSTEM'] == 'Detailed':
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elif env['SYSTEM'] == 'Detailed':
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from DetailedConfig import *
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from DetailedConfig import *
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BaseCPU.workload = Super.workload
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BaseCPU.workload = parent.workload
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DetailedStandAlone.cpu = [ DetailedCPU() for i in xrange(int(env['NP'])) ]
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DetailedStandAlone.cpu = [ DetailedCPU() for i in xrange(int(env['NP'])) ]
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root = DetailedStandAlone
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root = DetailedStandAlone
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else:
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else:
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@ -393,13 +393,11 @@ template <class T>
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Fault
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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{
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if (status() == DcacheMissStall) {
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if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
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Fault fault = xc->read(memReq,data);
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Fault fault = xc->read(memReq,data);
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if (traceData) {
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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}
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return fault;
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return fault;
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}
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}
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@ -428,21 +426,11 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
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// do functional access
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// do functional access
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fault = xc->read(memReq, data);
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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}
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}
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} else if(fault == No_Fault) {
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} else if(fault == No_Fault) {
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// do functional access
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// do functional access
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fault = xc->read(memReq, data);
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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}
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}
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if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
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if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
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@ -498,11 +486,6 @@ template <class T>
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Fault
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Fault
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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{
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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memReq->reset(addr, sizeof(T), flags);
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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// translate to physical address
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@ -602,6 +585,8 @@ SimpleCPU::processCacheCompletion()
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case DcacheMissStall:
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case DcacheMissStall:
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if (memReq->cmd.isRead()) {
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if (memReq->cmd.isRead()) {
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curStaticInst->execute(this,traceData);
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curStaticInst->execute(this,traceData);
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if (traceData)
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traceData->finalize();
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}
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}
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dcacheStallCycles += curTick - lastDcacheStall;
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dcacheStallCycles += curTick - lastDcacheStall;
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_status = Running;
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_status = Running;
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@ -610,6 +595,8 @@ SimpleCPU::processCacheCompletion()
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case DcacheMissSwitch:
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case DcacheMissSwitch:
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if (memReq->cmd.isRead()) {
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if (memReq->cmd.isRead()) {
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curStaticInst->execute(this,traceData);
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curStaticInst->execute(this,traceData);
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if (traceData)
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traceData->finalize();
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}
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}
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_status = SwitchedOut;
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_status = SwitchedOut;
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sampler->signalSwitched();
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sampler->signalSwitched();
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@ -782,8 +769,12 @@ SimpleCPU::tick()
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comLoadEventQueue[0]->serviceEvents(numLoad);
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comLoadEventQueue[0]->serviceEvents(numLoad);
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}
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}
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if (traceData)
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// If we have a dcache miss, then we can't finialize the instruction
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// trace yet because we want to populate it with the data later
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if (traceData &&
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!(status() == DcacheMissStall && memReq->cmd.isRead())) {
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traceData->finalize();
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traceData->finalize();
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}
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traceFunctions(xc->regs.pc);
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traceFunctions(xc->regs.pc);
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@ -1597,8 +1597,10 @@ NSGigE::rxKick()
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DPRINTF(Ethernet, "ID is %d\n", ip->id());
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DPRINTF(Ethernet, "ID is %d\n", ip->id());
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TcpPtr tcp(ip);
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TcpPtr tcp(ip);
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if (tcp) {
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if (tcp) {
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DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
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DPRINTF(Ethernet,
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tcp->sport(), tcp->dport());
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"Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
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tcp->sport(), tcp->dport(), tcp->seq(),
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tcp->ack());
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}
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}
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}
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}
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}
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}
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@ -1803,14 +1805,15 @@ NSGigE::transmit()
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DPRINTF(Ethernet, "ID is %d\n", ip->id());
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DPRINTF(Ethernet, "ID is %d\n", ip->id());
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TcpPtr tcp(ip);
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TcpPtr tcp(ip);
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if (tcp) {
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if (tcp) {
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DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
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DPRINTF(Ethernet,
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tcp->sport(), tcp->dport());
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"Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
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tcp->sport(), tcp->dport(), tcp->seq(), tcp->ack());
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}
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}
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}
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}
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}
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}
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#endif
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#endif
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DDUMP(Ethernet, txFifo.front()->data, txFifo.front()->length);
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DDUMP(EthernetData, txFifo.front()->data, txFifo.front()->length);
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txBytes += txFifo.front()->length;
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txBytes += txFifo.front()->length;
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txPackets++;
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txPackets++;
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@ -2296,8 +2299,18 @@ NSGigE::recvPacket(PacketPtr packet)
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}
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}
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if (rxFifo.avail() < packet->length) {
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if (rxFifo.avail() < packet->length) {
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DPRINTF(Ethernet,
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#if TRACING_ON
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"packet will not fit in receive buffer...packet dropped\n");
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IpPtr ip(packet);
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TcpPtr tcp(ip);
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if (ip) {
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DPRINTF(Ethernet,
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"packet won't fit in receive buffer...pkt ID %d dropped\n",
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ip->id());
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if (tcp) {
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DPRINTF(Ethernet, "Seq=%d\n", tcp->seq());
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}
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}
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#endif
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droppedPackets++;
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droppedPackets++;
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devIntrPost(ISR_RXORN);
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devIntrPost(ISR_RXORN);
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return false;
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return false;
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@ -27,6 +27,7 @@
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from __future__ import generators
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from __future__ import generators
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import os, re, sys, types, inspect
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import os, re, sys, types, inspect
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from m5 import panic
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from convert import *
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from convert import *
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noDot = False
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noDot = False
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@ -139,25 +140,91 @@ class Singleton(type):
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#####################################################################
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#####################################################################
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class Proxy(object):
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class Proxy(object):
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def __init__(self, path = ()):
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def __init__(self, path):
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self._object = None
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self._object = None
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self._path = path
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if path == 'any':
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self._path = None
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else:
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# path is a list of (attr,index) tuples
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self._path = [(path,None)]
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self._index = None
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self._multiplier = None
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def __getattr__(self, attr):
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def __getattr__(self, attr):
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return Proxy(self._path + (attr, ))
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if attr == '__bases__':
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return super(Proxy, self).__getattr__(self, attr)
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self._path.append((attr,None))
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return self
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def __setattr__(self, attr, value):
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def __setattr__(self, attr, value):
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if not attr.startswith('_'):
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if not attr.startswith('_'):
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raise AttributeError, 'cannot set attribute %s' % attr
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raise AttributeError, 'cannot set attribute %s' % attr
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super(Proxy, self).__setattr__(attr, value)
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super(Proxy, self).__setattr__(attr, value)
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def _convert(self):
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# support indexing on proxies (e.g., parent.cpu[0])
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obj = self._object
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def __getitem__(self, key):
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for attr in self._path:
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if not isinstance(key, int):
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obj = obj.__getattribute__(attr)
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raise TypeError, "Proxy object requires integer index"
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return obj
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if self._path == None:
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raise IndexError, "Index applied to 'any' proxy"
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# replace index portion of last path element with new index
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self._path[-1] = (self._path[-1][0], key)
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return self
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Super = Proxy()
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# support multiplying proxies by constants
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def __mul__(self, other):
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if not isinstance(other, int):
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raise TypeError, "Proxy multiplier must be integer"
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|
if self._multiplier == None:
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self._multiplier = other
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else:
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# support chained multipliers
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self._multiplier *= other
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return self
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def _mulcheck(self, result):
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|
if self._multiplier == None:
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return result
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if not isinstance(result, int):
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|
raise TypeError, "Proxy with multiplier resolves to " \
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"non-integer value"
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return result * self._multiplier
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def unproxy(self, base, ptype):
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obj = base
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|
done = False
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|
while not done:
|
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|
if obj is None:
|
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|
raise AttributeError, \
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|
'Parent of %s type %s not found at path %s' \
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|
% (base.name, ptype, self._path)
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|
result, done = obj.find(ptype, self._path)
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|
obj = obj.parent
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|
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|
if isinstance(result, Proxy):
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|
result = result.unproxy(obj, ptype)
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|
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|
return self._mulcheck(result)
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|
|
||||||
|
def getindex(obj, index):
|
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|
if index == None:
|
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|
return obj
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|
try:
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|
obj = obj[index]
|
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|
except TypeError:
|
||||||
|
if index != 0:
|
||||||
|
raise
|
||||||
|
# if index is 0 and item is not subscriptable, just
|
||||||
|
# use item itself (so cpu[0] works on uniprocessors)
|
||||||
|
return obj
|
||||||
|
getindex = staticmethod(getindex)
|
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|
|
||||||
|
class ProxyFactory(object):
|
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|
def __getattr__(self, attr):
|
||||||
|
return Proxy(attr)
|
||||||
|
|
||||||
|
# global object for handling parent.foo proxies
|
||||||
|
parent = ProxyFactory()
|
||||||
|
|
||||||
def isSubClass(value, cls):
|
def isSubClass(value, cls):
|
||||||
try:
|
try:
|
||||||
|
@ -643,50 +710,40 @@ class Node(object):
|
||||||
if issubclass(child.realtype, realtype):
|
if issubclass(child.realtype, realtype):
|
||||||
if obj is not None:
|
if obj is not None:
|
||||||
raise AttributeError, \
|
raise AttributeError, \
|
||||||
'Super matched more than one: %s %s' % \
|
'parent.any matched more than one: %s %s' % \
|
||||||
(obj.path, child.path)
|
(obj.path, child.path)
|
||||||
obj = child
|
obj = child
|
||||||
return obj, obj is not None
|
return obj, obj is not None
|
||||||
|
|
||||||
try:
|
try:
|
||||||
obj = self
|
obj = self
|
||||||
for node in path[:-1]:
|
for (node,index) in path[:-1]:
|
||||||
obj = obj.child_names[node]
|
if obj.child_names.has_key(node):
|
||||||
|
obj = obj.child_names[node]
|
||||||
|
else:
|
||||||
|
obj = obj.top_child_names[node]
|
||||||
|
obj = Proxy.getindex(obj, index)
|
||||||
|
|
||||||
last = path[-1]
|
(last,index) = path[-1]
|
||||||
if obj.child_names.has_key(last):
|
if obj.child_names.has_key(last):
|
||||||
value = obj.child_names[last]
|
value = obj.child_names[last]
|
||||||
if issubclass(value.realtype, realtype):
|
return Proxy.getindex(value, index), True
|
||||||
return value, True
|
elif obj.top_child_names.has_key(last):
|
||||||
|
value = obj.top_child_names[last]
|
||||||
|
return Proxy.getindex(value, index), True
|
||||||
elif obj.param_names.has_key(last):
|
elif obj.param_names.has_key(last):
|
||||||
value = obj.param_names[last]
|
value = obj.param_names[last]
|
||||||
realtype._convert(value.value)
|
realtype._convert(value.value)
|
||||||
return value.value, True
|
return Proxy.getindex(value.value, index), True
|
||||||
except KeyError:
|
except KeyError:
|
||||||
pass
|
pass
|
||||||
|
|
||||||
return None, False
|
return None, False
|
||||||
|
|
||||||
def unproxy(self, ptype, value):
|
def unproxy(self, param, ptype):
|
||||||
if not isinstance(value, Proxy):
|
if not isinstance(param, Proxy):
|
||||||
return value
|
return param
|
||||||
|
return param.unproxy(self, ptype)
|
||||||
if value is None:
|
|
||||||
raise AttributeError, 'Error while fixing up %s' % self.path
|
|
||||||
|
|
||||||
obj = self
|
|
||||||
done = False
|
|
||||||
while not done:
|
|
||||||
if obj is None:
|
|
||||||
raise AttributeError, \
|
|
||||||
'Parent of %s type %s not found at path %s' \
|
|
||||||
% (self.name, ptype, value._path)
|
|
||||||
found, done = obj.find(ptype, value._path)
|
|
||||||
if isinstance(found, Proxy):
|
|
||||||
done = False
|
|
||||||
obj = obj.parent
|
|
||||||
|
|
||||||
return found
|
|
||||||
|
|
||||||
def fixup(self):
|
def fixup(self):
|
||||||
self.all[self.path] = self
|
self.all[self.path] = self
|
||||||
|
@ -697,9 +754,9 @@ class Node(object):
|
||||||
|
|
||||||
try:
|
try:
|
||||||
if isinstance(pval, (list, tuple)):
|
if isinstance(pval, (list, tuple)):
|
||||||
param.value = [ self.unproxy(ptype, pv) for pv in pval ]
|
param.value = [ self.unproxy(pv, ptype) for pv in pval ]
|
||||||
else:
|
else:
|
||||||
param.value = self.unproxy(ptype, pval)
|
param.value = self.unproxy(pval, ptype)
|
||||||
except:
|
except:
|
||||||
print 'Error while fixing up %s:%s' % (self.path, param.name)
|
print 'Error while fixing up %s:%s' % (self.path, param.name)
|
||||||
raise
|
raise
|
||||||
|
@ -840,6 +897,9 @@ class Value(object):
|
||||||
def __str__(self):
|
def __str__(self):
|
||||||
return str(self._getattr())
|
return str(self._getattr())
|
||||||
|
|
||||||
|
def __len__(self):
|
||||||
|
return len(self._getattr())
|
||||||
|
|
||||||
# Regular parameter.
|
# Regular parameter.
|
||||||
class _Param(object):
|
class _Param(object):
|
||||||
def __init__(self, ptype, *args, **kwargs):
|
def __init__(self, ptype, *args, **kwargs):
|
||||||
|
@ -1337,7 +1397,7 @@ class SimObject(ConfigNode, ParamType):
|
||||||
# 'from config import *' is invoked. Try to keep this reasonably
|
# 'from config import *' is invoked. Try to keep this reasonably
|
||||||
# short to avoid polluting other namespaces.
|
# short to avoid polluting other namespaces.
|
||||||
__all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam',
|
__all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam',
|
||||||
'Super', 'Enum',
|
'parent', 'Enum',
|
||||||
'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
|
'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
|
||||||
'Int32', 'UInt32', 'Int64', 'UInt64',
|
'Int32', 'UInt32', 'Int64', 'UInt64',
|
||||||
'Counter', 'Addr', 'Tick', 'Percent',
|
'Counter', 'Addr', 'Tick', 'Percent',
|
||||||
|
|
|
@ -2,8 +2,8 @@ from Device import PioDevice
|
||||||
|
|
||||||
simobj AlphaConsole(PioDevice):
|
simobj AlphaConsole(PioDevice):
|
||||||
type = 'AlphaConsole'
|
type = 'AlphaConsole'
|
||||||
cpu = Param.BaseCPU(Super, "Processor")
|
cpu = Param.BaseCPU(parent.any, "Processor")
|
||||||
disk = Param.SimpleDisk("Simple Disk")
|
disk = Param.SimpleDisk("Simple Disk")
|
||||||
num_cpus = Param.Int(1, "Number of CPUs")
|
num_cpus = Param.Int(1, "Number of CPUs")
|
||||||
sim_console = Param.SimConsole(Super, "The Simulator Console")
|
sim_console = Param.SimConsole(parent.any, "The Simulator Console")
|
||||||
system = Param.BaseSystem(Super, "system object")
|
system = Param.BaseSystem(parent.any, "system object")
|
||||||
|
|
|
@ -8,7 +8,7 @@ simobj BaseCPU(SimObject):
|
||||||
dtb = Param.AlphaDTB("Data TLB")
|
dtb = Param.AlphaDTB("Data TLB")
|
||||||
itb = Param.AlphaITB("Instruction TLB")
|
itb = Param.AlphaITB("Instruction TLB")
|
||||||
mem = Param.FunctionalMemory("memory")
|
mem = Param.FunctionalMemory("memory")
|
||||||
system = Param.BaseSystem(Super, "system object")
|
system = Param.BaseSystem(parent.any, "system object")
|
||||||
else:
|
else:
|
||||||
workload = VectorParam.Process("processes to run")
|
workload = VectorParam.Process("processes to run")
|
||||||
|
|
||||||
|
|
|
@ -1,8 +1,8 @@
|
||||||
simobj BaseSystem(SimObject):
|
simobj BaseSystem(SimObject):
|
||||||
type = 'BaseSystem'
|
type = 'BaseSystem'
|
||||||
abstract = True
|
abstract = True
|
||||||
memctrl = Param.MemoryController(Super, "memory controller")
|
memctrl = Param.MemoryController(parent.any, "memory controller")
|
||||||
physmem = Param.PhysicalMemory(Super, "phsyical memory")
|
physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
|
||||||
kernel = Param.String("file that contains the kernel code")
|
kernel = Param.String("file that contains the kernel code")
|
||||||
console = Param.String("file that contains the console code")
|
console = Param.String("file that contains the console code")
|
||||||
pal = Param.String("file that contains palcode")
|
pal = Param.String("file that contains palcode")
|
||||||
|
|
|
@ -14,7 +14,7 @@ simobj FooPioDevice(FunctionalMemory):
|
||||||
type = 'PioDevice'
|
type = 'PioDevice'
|
||||||
abstract = True
|
abstract = True
|
||||||
addr = Param.Addr("Device Address")
|
addr = Param.Addr("Device Address")
|
||||||
mmu = Param.MemoryController(Super, "Memory Controller")
|
mmu = Param.MemoryController(parent.any, "Memory Controller")
|
||||||
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
|
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
|
||||||
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
|
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
|
||||||
|
|
||||||
|
@ -25,7 +25,7 @@ simobj FooDmaDevice(FooPioDevice):
|
||||||
simobj PioDevice(FooPioDevice):
|
simobj PioDevice(FooPioDevice):
|
||||||
type = 'PioDevice'
|
type = 'PioDevice'
|
||||||
abstract = True
|
abstract = True
|
||||||
platform = Param.Platform(Super, "Platform")
|
platform = Param.Platform(parent.any, "Platform")
|
||||||
|
|
||||||
simobj DmaDevice(PioDevice):
|
simobj DmaDevice(PioDevice):
|
||||||
type = 'DmaDevice'
|
type = 'DmaDevice'
|
||||||
|
|
|
@ -49,8 +49,8 @@ simobj EtherDev(DmaDevice):
|
||||||
|
|
||||||
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
|
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
|
||||||
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
|
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
|
||||||
physmem = Param.PhysicalMemory(Super, "Physical Memory")
|
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
|
||||||
tlaser = Param.Turbolaser(Super, "Turbolaser")
|
tlaser = Param.Turbolaser(parent.any, "Turbolaser")
|
||||||
|
|
||||||
simobj NSGigE(PciDevice):
|
simobj NSGigE(PciDevice):
|
||||||
type = 'NSGigE'
|
type = 'NSGigE'
|
||||||
|
@ -73,7 +73,7 @@ simobj NSGigE(PciDevice):
|
||||||
|
|
||||||
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
|
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
|
||||||
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
|
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
|
||||||
physmem = Param.PhysicalMemory(Super, "Physical Memory")
|
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
|
||||||
|
|
||||||
simobj EtherDevInt(EtherInt):
|
simobj EtherDevInt(EtherInt):
|
||||||
type = 'EtherDevInt'
|
type = 'EtherDevInt'
|
||||||
|
|
|
@ -7,7 +7,7 @@ simobj IdeDisk(SimObject):
|
||||||
delay = Param.Tick(1, "Fixed disk delay in microseconds")
|
delay = Param.Tick(1, "Fixed disk delay in microseconds")
|
||||||
driveID = Param.IdeID('master', "Drive ID")
|
driveID = Param.IdeID('master', "Drive ID")
|
||||||
image = Param.DiskImage("Disk image")
|
image = Param.DiskImage("Disk image")
|
||||||
physmem = Param.PhysicalMemory(Super, "Physical memory")
|
physmem = Param.PhysicalMemory(parent.any, "Physical memory")
|
||||||
|
|
||||||
simobj IdeController(PciDevice):
|
simobj IdeController(PciDevice):
|
||||||
type = 'IdeController'
|
type = 'IdeController'
|
||||||
|
|
|
@ -1,3 +1,3 @@
|
||||||
simobj IntrControl(SimObject):
|
simobj IntrControl(SimObject):
|
||||||
type = 'IntrControl'
|
type = 'IntrControl'
|
||||||
cpu = Param.BaseCPU(Super, "the cpu")
|
cpu = Param.BaseCPU(parent.any, "the cpu")
|
||||||
|
|
|
@ -47,5 +47,5 @@ simobj PciDevice(DmaDevice):
|
||||||
pci_bus = Param.Int("PCI bus")
|
pci_bus = Param.Int("PCI bus")
|
||||||
pci_dev = Param.Int("PCI device number")
|
pci_dev = Param.Int("PCI device number")
|
||||||
pci_func = Param.Int("PCI function code")
|
pci_func = Param.Int("PCI function code")
|
||||||
configdata = Param.PciConfigData(Super, "PCI Config data")
|
configdata = Param.PciConfigData(parent.any, "PCI Config data")
|
||||||
configspace = Param.PciConfigAll(Super, "PCI Configspace")
|
configspace = Param.PciConfigAll(parent.any, "PCI Configspace")
|
||||||
|
|
|
@ -4,4 +4,4 @@ simobj PhysicalMemory(FunctionalMemory):
|
||||||
type = 'PhysicalMemory'
|
type = 'PhysicalMemory'
|
||||||
range = Param.AddrRange("Device Address")
|
range = Param.AddrRange("Device Address")
|
||||||
file = Param.String('', "memory mapped file")
|
file = Param.String('', "memory mapped file")
|
||||||
mmu = Param.MemoryController(Super, "Memory Controller")
|
mmu = Param.MemoryController(parent.any, "Memory Controller")
|
||||||
|
|
|
@ -2,4 +2,4 @@ simobj Platform(SimObject):
|
||||||
type = 'Platform'
|
type = 'Platform'
|
||||||
abstract = True
|
abstract = True
|
||||||
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
|
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
|
||||||
intrctrl = Param.IntrControl(Super, "interrupt controller")
|
intrctrl = Param.IntrControl(parent.any, "interrupt controller")
|
||||||
|
|
|
@ -5,7 +5,7 @@ simobj ConsoleListener(SimObject):
|
||||||
simobj SimConsole(SimObject):
|
simobj SimConsole(SimObject):
|
||||||
type = 'SimConsole'
|
type = 'SimConsole'
|
||||||
append_name = Param.Bool(True, "append name() to filename")
|
append_name = Param.Bool(True, "append name() to filename")
|
||||||
intr_control = Param.IntrControl(Super, "interrupt controller")
|
intr_control = Param.IntrControl(parent.any, "interrupt controller")
|
||||||
listener = Param.ConsoleListener("console listener")
|
listener = Param.ConsoleListener("console listener")
|
||||||
number = Param.Int(0, "console number")
|
number = Param.Int(0, "console number")
|
||||||
output = Param.String('console', "file to dump output to")
|
output = Param.String('console', "file to dump output to")
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
simobj SimpleDisk(SimObject):
|
simobj SimpleDisk(SimObject):
|
||||||
type = 'SimpleDisk'
|
type = 'SimpleDisk'
|
||||||
disk = Param.DiskImage("Disk Image")
|
disk = Param.DiskImage("Disk Image")
|
||||||
physmem = Param.PhysicalMemory(Super, "Physical Memory")
|
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
|
||||||
|
|
|
@ -4,12 +4,12 @@ from Platform import Platform
|
||||||
simobj Tsunami(Platform):
|
simobj Tsunami(Platform):
|
||||||
type = 'Tsunami'
|
type = 'Tsunami'
|
||||||
pciconfig = Param.PciConfigAll("PCI configuration")
|
pciconfig = Param.PciConfigAll("PCI configuration")
|
||||||
system = Param.BaseSystem(Super, "system")
|
system = Param.BaseSystem(parent.any, "system")
|
||||||
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
|
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
|
||||||
|
|
||||||
simobj TsunamiCChip(FooPioDevice):
|
simobj TsunamiCChip(FooPioDevice):
|
||||||
type = 'TsunamiCChip'
|
type = 'TsunamiCChip'
|
||||||
tsunami = Param.Tsunami(Super, "Tsunami")
|
tsunami = Param.Tsunami(parent.any, "Tsunami")
|
||||||
|
|
||||||
simobj TsunamiFake(FooPioDevice):
|
simobj TsunamiFake(FooPioDevice):
|
||||||
type = 'TsunamiFake'
|
type = 'TsunamiFake'
|
||||||
|
@ -18,8 +18,8 @@ simobj TsunamiIO(FooPioDevice):
|
||||||
type = 'TsunamiIO'
|
type = 'TsunamiIO'
|
||||||
time = Param.UInt64(1136073600,
|
time = Param.UInt64(1136073600,
|
||||||
"System time to use (0 for actual time, default is 1/1/06)")
|
"System time to use (0 for actual time, default is 1/1/06)")
|
||||||
tsunami = Param.Tsunami(Super, "Tsunami")
|
tsunami = Param.Tsunami(parent.any, "Tsunami")
|
||||||
|
|
||||||
simobj TsunamiPChip(FooPioDevice):
|
simobj TsunamiPChip(FooPioDevice):
|
||||||
type = 'TsunamiPChip'
|
type = 'TsunamiPChip'
|
||||||
tsunami = Param.Tsunami(Super, "Tsunami")
|
tsunami = Param.Tsunami(parent.any, "Tsunami")
|
||||||
|
|
|
@ -2,5 +2,5 @@ from Device import PioDevice
|
||||||
|
|
||||||
simobj Uart(PioDevice):
|
simobj Uart(PioDevice):
|
||||||
type = 'Uart'
|
type = 'Uart'
|
||||||
console = Param.SimConsole(Super, "The console")
|
console = Param.SimConsole(parent.any, "The console")
|
||||||
size = Param.Addr(0x8, "Device size")
|
size = Param.Addr(0x8, "Device size")
|
||||||
|
|
|
@ -74,6 +74,12 @@ class SmartDict(dict):
|
||||||
return other / self.convert(other)
|
return other / self.convert(other)
|
||||||
|
|
||||||
|
|
||||||
|
# __getitem__ uses dict.get() to return 'False' if the key is not
|
||||||
|
# found (rather than raising KeyError). Note that this does *not*
|
||||||
|
# set the key's value to 'False' in the dict, so that even after
|
||||||
|
# we call env['foo'] we still get a meaningful answer from "'foo'
|
||||||
|
# in env" (which calls dict.__contains__, which we do not
|
||||||
|
# override).
|
||||||
def __getitem__(self, key):
|
def __getitem__(self, key):
|
||||||
return self.Proxy(dict.get(self, key, 'False'))
|
return self.Proxy(dict.get(self, key, 'False'))
|
||||||
|
|
||||||
|
|
|
@ -89,6 +89,7 @@ Process::Process(const string &nm,
|
||||||
}
|
}
|
||||||
|
|
||||||
mmap_start = mmap_end = 0;
|
mmap_start = mmap_end = 0;
|
||||||
|
nxm_start = nxm_end = 0;
|
||||||
// other parameters will be initialized when the program is loaded
|
// other parameters will be initialized when the program is loaded
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -97,6 +97,10 @@ class Process : public SimObject
|
||||||
Addr mmap_start;
|
Addr mmap_start;
|
||||||
Addr mmap_end;
|
Addr mmap_end;
|
||||||
|
|
||||||
|
// Base of region for nxm data
|
||||||
|
Addr nxm_start;
|
||||||
|
Addr nxm_end;
|
||||||
|
|
||||||
std::string prog_fname; // file name
|
std::string prog_fname; // file name
|
||||||
Addr prog_entry; // entry point (initial PC)
|
Addr prog_entry; // entry point (initial PC)
|
||||||
|
|
||||||
|
@ -159,9 +163,10 @@ class Process : public SimObject
|
||||||
bool validDataAddr(Addr addr)
|
bool validDataAddr(Addr addr)
|
||||||
{
|
{
|
||||||
return ((data_base <= addr && addr < brk_point) ||
|
return ((data_base <= addr && addr < brk_point) ||
|
||||||
((stack_base - 16*1024*1024) <= addr && addr < stack_base) ||
|
(next_thread_stack_base <= addr && addr < stack_base) ||
|
||||||
(text_base <= addr && addr < (text_base + text_size)) ||
|
(text_base <= addr && addr < (text_base + text_size)) ||
|
||||||
(mmap_start <= addr && addr < mmap_end));
|
(mmap_start <= addr && addr < mmap_end) ||
|
||||||
|
(nxm_start <= addr && addr < nxm_end));
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual void syscall(ExecContext *xc) = 0;
|
virtual void syscall(ExecContext *xc) = 0;
|
||||||
|
|
|
@ -412,6 +412,10 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
|
||||||
// user didn't give an address... pick one from our "mmap region"
|
// user didn't give an address... pick one from our "mmap region"
|
||||||
start = p->mmap_end;
|
start = p->mmap_end;
|
||||||
p->mmap_end += RoundUp<Addr>(length, VMPageSize);
|
p->mmap_end += RoundUp<Addr>(length, VMPageSize);
|
||||||
|
if (p->nxm_start != 0) {
|
||||||
|
//If we have an nxm space, make sure we haven't colided
|
||||||
|
assert(p->mmap_end < p->nxm_start);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!(flags & OS::TGT_MAP_ANONYMOUS)) {
|
if (!(flags & OS::TGT_MAP_ANONYMOUS)) {
|
||||||
|
|
Loading…
Reference in a new issue