Configs: Add support for the InOrder CPU model
This commit is contained in:
Korey Sewell
parent
973d8b8b13
commit
cf4a00ca41
6 changed files with 182 additions and 159 deletions
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@ -29,6 +29,7 @@
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# system options
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parser.add_option("-d", "--detailed", action="store_true")
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parser.add_option("-t", "--timing", action="store_true")
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parser.add_option("--inorder", action="store_true")
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parser.add_option("-n", "--num-cpus", type="int", default=1)
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parser.add_option("--caches", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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@ -43,6 +43,11 @@ def setCPUClass(options):
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print "O3 CPU must be used with caches"
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sys.exit(1)
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class TmpClass(DerivO3CPU): pass
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elif options.inorder:
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if not options.caches:
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print "InOrder CPU must be used with caches"
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sys.exit(1)
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class TmpClass(InOrderCPU): pass
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else:
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class TmpClass(AtomicSimpleCPU): pass
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atomic = True
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@ -312,6 +312,13 @@ class InOrderCPU : public BaseCPU
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void deallocateThread(unsigned tid);
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void deactivateThread(unsigned tid);
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int
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contextId()
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{
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hack_once("return a bogus context id");
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return 0;
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}
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/** Remove Thread from Active Threads List &&
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* Remove Thread Context from CPU.
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*/
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@ -414,20 +421,20 @@ class InOrderCPU : public BaseCPU
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int width = TheISA::SingleWidth);
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/** Reads a miscellaneous register. */
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MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
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MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0);
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/** Reads a misc. register, including any side effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscReg(int misc_reg, unsigned tid);
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MiscReg readMiscReg(int misc_reg, unsigned tid = 0);
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/** Sets a miscellaneous register. */
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid);
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
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/** Sets a misc. register, including any side effects the write
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* might have as defined by the architecture.
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*/
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void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
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void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0);
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/** Reads a int/fp/misc reg. from another thread depending on ISA-defined
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* target thread
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@ -454,9 +454,8 @@ InOrderDynInst::readMiscRegNoEffect(int misc_reg)
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MiscReg
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InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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{
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return this->cpu->readMiscRegNoEffect(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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this->threadNumber);
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int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return cpu->readMiscRegNoEffect(reg, this->threadNumber);
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}
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/** Reads a misc. register, including any side-effects the read
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@ -465,9 +464,8 @@ InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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MiscReg
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InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
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{
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return this->cpu->readMiscReg(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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this->threadNumber);
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int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return this->cpu->readMiscReg(reg, this->threadNumber);
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}
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/** Sets a misc. register. */
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@ -43,7 +43,6 @@ using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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Tick
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CacheUnit::CachePort::recvAtomic(PacketPtr pkt)
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{
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@ -92,9 +91,8 @@ CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
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cacheBlocked = false;
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}
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Port *
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CacheUnit::getPort(const std::string &if_name, int idx)
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CacheUnit::getPort(const string &if_name, int idx)
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{
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if (if_name == resName)
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return cachePort;
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@ -106,7 +104,7 @@ int
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CacheUnit::getSlot(DynInstPtr inst)
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{
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if (!inst->validMemAddr()) {
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panic("Mem. Addr. must be set before requesting cache access.\n");
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panic("Mem. Addr. must be set before requesting cache access\n");
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}
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Addr req_addr = inst->getMemAddr();
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@ -116,20 +114,19 @@ CacheUnit::getSlot(DynInstPtr inst)
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int new_slot = Resource::getSlot(inst);
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if (new_slot != -1) {
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if (new_slot == -1)
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return -1;
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inst->memTime = curTick;
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addrList.push_back(req_addr);
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addrMap[req_addr] = inst->seqNum;
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DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Address %08p added to dependency list.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
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inst->readTid(), inst->seqNum, req_addr);
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return new_slot;
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} else {
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return -1;
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}
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} else {
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DPRINTF(InOrderCachePort,"Denying request because there is an outstanding"
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DPRINTF(InOrderCachePort,
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"Denying request because there is an outstanding"
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" request to/for addr. %08p. by [sn:%i] @ tick %i\n",
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req_addr, addrMap[req_addr], inst->memTime);
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return -1;
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@ -139,11 +136,12 @@ CacheUnit::getSlot(DynInstPtr inst)
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void
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CacheUnit::freeSlot(int slot_num)
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{
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std::vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(),
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vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(),
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reqMap[slot_num]->inst->getMemAddr());
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assert(vect_it != addrList.end());
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DPRINTF(InOrderCachePort, "[tid:%i]: Address %08p removed from dependency list.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Address %08p removed from dependency list\n",
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reqMap[slot_num]->inst->readTid(), (*vect_it));
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addrList.erase(vect_it);
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@ -158,7 +156,7 @@ CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
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ScheduleEntry* sched_entry = inst->resSched.top();
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if (!inst->validMemAddr()) {
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panic("Mem. Addr. must be set before requesting cache access.\n");
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panic("Mem. Addr. must be set before requesting cache access\n");
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}
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int req_size = 0;
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@ -168,23 +166,26 @@ CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
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pkt_cmd = MemCmd::ReadReq;
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req_size = inst->getMemAccSize();
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DPRINTF(InOrderCachePort, "[tid:%i]: %i byte Read request from [sn:%i] for addr %08p.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: %i byte Read request from [sn:%i] for addr %08p\n",
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inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
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} else if (sched_entry->cmd == InitiateWriteData) {
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pkt_cmd = MemCmd::WriteReq;
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req_size = inst->getMemAccSize();
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DPRINTF(InOrderCachePort, "[tid:%i]: %i byte Write request from [sn:%i] for addr %08p.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: %i byte Write request from [sn:%i] for addr %08p\n",
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inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
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} else if (sched_entry->cmd == InitiateFetch){
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pkt_cmd = MemCmd::ReadReq;
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req_size = sizeof(MachInst); //@TODO: mips16e
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DPRINTF(InOrderCachePort, "[tid:%i]: %i byte Fetch request from [sn:%i] for addr %08p.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: %i byte Fetch request from [sn:%i] for addr %08p\n",
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inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
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} else {
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panic("%i: Unexpected request type (%i) to %s", curTick, sched_entry->cmd, name());
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panic("%i: Unexpected request type (%i) to %s", curTick,
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sched_entry->cmd, name());
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}
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return new CacheRequest(this, inst, stage_num, id, slot_num,
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@ -205,26 +206,27 @@ CacheUnit::requestAgain(DynInstPtr inst, bool &service_request)
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if (cache_req->cmd != inst->resSched.top()->cmd) {
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// If different, then update command in the request
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cache_req->cmd = inst->resSched.top()->cmd;
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DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Updating the command for this "
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"instruction.\n", inst->readTid(), inst->seqNum);
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: the command for this instruction\n",
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inst->readTid(), inst->seqNum);
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service_request = true;
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} else {
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// If same command, just check to see if memory access was completed
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// but dont try to re-execute
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DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: requesting this resource again.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: requesting this resource again\n",
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inst->readTid(), inst->seqNum);
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service_request = true;
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}
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}
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void
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CacheUnit::execute(int slot_num)
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{
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if (cacheBlocked) {
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DPRINTF(InOrderCachePort, "Cache Blocked. Cannot Access.\n");
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DPRINTF(InOrderCachePort, "Cache Blocked. Cannot Access\n");
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return;
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}
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@ -243,7 +245,6 @@ CacheUnit::execute(int slot_num)
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switch (cache_req->cmd)
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{
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case InitiateFetch:
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{
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DPRINTF(InOrderCachePort,
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"[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
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tid, name(), cache_req->inst->getMemAddr());
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@ -254,11 +255,9 @@ CacheUnit::execute(int slot_num)
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inst->setCurResSlot(slot_num);
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doDataAccess(inst);
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}
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break;
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case CompleteFetch:
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{
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if (cache_req->isMemAccComplete()) {
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Completing Fetch Access for [sn:%i]\n",
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@ -266,15 +265,17 @@ CacheUnit::execute(int slot_num)
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MachInst mach_inst = cache_req->dataPkt->get<MachInst>();
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//@TODO: May Need This Function for Endianness-Compatibility
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//mach_inst = gtoh(*reinterpret_cast<MachInst *>(&cacheData[tid][offset]));
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/**
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* @TODO: May Need This Function for Endianness-Compatibility
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* mach_inst =
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* gtoh(*reinterpret_cast<MachInst *>(&cacheData[tid][offset]));
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*/
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DPRINTF(InOrderCachePort,
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"[tid:%i]: Fetched instruction is %08p\n",
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tid, mach_inst);
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//ExtMachInst ext_inst
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// = TheISA::makeExtMI(mach_inst, cpu->tcBase(tid));
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// ExtMachInst ext_inst = makeExtMI(mach_inst, cpu->tcBase(tid));
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inst->setMachInst(mach_inst);
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inst->setASID(tid);
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@ -291,33 +292,31 @@ CacheUnit::execute(int slot_num)
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cache_req->done();
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} else {
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DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access.\n",
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
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tid, inst->seqNum);
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DPRINTF(InOrderStall, "STALL: [tid:%i]: Fetch miss from %08p.\n",
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DPRINTF(InOrderStall,
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"STALL: [tid:%i]: Fetch miss from %08p\n",
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tid, cache_req->inst->readPC());
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cache_req->setCompleted(false);
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}
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}
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break;
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case InitiateReadData:
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case InitiateWriteData:
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{
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DPRINTF(InOrderCachePort, "[tid:%u]: Initiating data access to %s "
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"for addr. %08p\n",
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DPRINTF(InOrderCachePort,
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"[tid:%u]: Initiating data access to %s for addr. %08p\n",
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tid, name(), cache_req->inst->getMemAddr());
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inst->setCurResSlot(slot_num);
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//inst->memAccess();
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inst->initiateAcc();
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}
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break;
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case CompleteReadData:
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case CompleteWriteData:
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{
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Trying to Complete Data Access.\n",
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"[tid:%i]: [sn:%i]: Trying to Complete Data Access\n",
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tid, inst->seqNum);
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if (cache_req->isMemAccComplete()) {
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cache_req->done();
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@ -326,7 +325,6 @@ CacheUnit::execute(int slot_num)
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tid, cache_req->inst->getMemAddr());
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cache_req->setCompleted(false);
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}
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}
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break;
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default:
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@ -364,12 +362,13 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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if (cache_req->dataPkt->isWrite() && memReq->isLocked()) {
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assert(cache_req->inst->isStoreConditional());
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DPRINTF(InOrderCachePort, "Evaluating Store Conditional access.\n");
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DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n");
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do_access = TheISA::handleLockedWrite(cpu, memReq);
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}
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DPRINTF(InOrderCachePort, "[tid:%i] [sn:%i] attempting to access cache..\n", tid, inst->seqNum);
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DPRINTF(InOrderCachePort,
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"[tid:%i] [sn:%i] attempting to access cache\n",
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tid, inst->seqNum);
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//@TODO: If you want to ignore failed store conditional accesses, then
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// enable this. However, this might skew memory stats because
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@ -377,7 +376,9 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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// - Remove optionality here ...
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if (1/*do_access*/) {
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if (!cachePort->sendTiming(cache_req->dataPkt)) {
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DPRINTF(InOrderCachePort, "[tid:%i] [sn:%i] is waiting to retry request.\n", tid, inst->seqNum);
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DPRINTF(InOrderCachePort,
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"[tid:%i] [sn:%i] is waiting to retry request\n",
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tid, inst->seqNum);
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retrySlot = cache_req->getSlot();
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retryReq = cache_req;
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@ -391,7 +392,9 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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cache_req->setCompleted(false);
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} else {
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DPRINTF(InOrderCachePort, "[tid:%i] [sn:%i] is now waiting for cache response.\n", tid, inst->seqNum);
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DPRINTF(InOrderCachePort,
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"[tid:%i] [sn:%i] is now waiting for cache response\n",
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tid, inst->seqNum);
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cache_req->setCompleted();
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cache_req->setMemAccPending();
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cacheStatus = cacheWaitResponse;
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@ -402,7 +405,8 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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assert(cache_req->inst->isStoreConditional());
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cache_req->setCompleted(true);
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DPRINTF(LLSC, "[tid:%i]: T%i Ignoring Failed Store Conditional Access.\n",
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DPRINTF(LLSC,
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"[tid:%i]: T%i Ignoring Failed Store Conditional Access\n",
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tid, tid);
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cache_req->dataPkt->req->setExtraData(0);
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@ -431,19 +435,19 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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if (cache_pkt->cacheReq->isSquashed()) {
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DPRINTF(InOrderCachePort,
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"Ignoring completion of squashed access, [tid:%i] [sn:%i].\n",
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"Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
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cache_pkt->cacheReq->getInst()->readTid(),
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cache_pkt->cacheReq->getInst()->seqNum);
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cache_pkt->cacheReq->done();
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return;
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} else {
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}
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Waking from cache access to addr. %08p.\n",
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"[tid:%u]: [sn:%i]: Waking from cache access to addr. %08p\n",
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cache_pkt->cacheReq->getInst()->readTid(),
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cache_pkt->cacheReq->getInst()->seqNum,
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cache_pkt->cacheReq->getInst()->getMemAddr());
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}
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// Cast to correct request type
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CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
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@ -462,11 +466,11 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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if (!cache_req->isSquashed()) {
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if (inst->resSched.top()->cmd == CompleteFetch) {
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Processing fetch access.\n",
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"[tid:%u]: [sn:%i]: Processing fetch access\n",
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tid, inst->seqNum);
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} else if (inst->staticInst && inst->isMemRef()) {
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Processing cache access.\n",
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"[tid:%u]: [sn:%i]: Processing cache access\n",
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tid, inst->seqNum);
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inst->completeAcc(pkt);
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@ -475,21 +479,22 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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assert(cache_pkt->isRead());
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if (cache_pkt->req->isLocked()) {
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DPRINTF(InOrderCachePort, "[tid:%u]: Handling Load-Linked "
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"access for [sn:%u].\n", tid, inst->seqNum);
|
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DPRINTF(InOrderCachePort,
|
||||
"[tid:%u]: Handling Load-Linked for [sn:%u]\n",
|
||||
tid, inst->seqNum);
|
||||
TheISA::handleLockedRead(cpu, cache_pkt->req);
|
||||
}
|
||||
|
||||
// @TODO: Hardcoded to for load instructions. Assumes that
|
||||
// the dest. idx 0 is always where the data is loaded to.
|
||||
DPRINTF(InOrderCachePort,
|
||||
"[tid:%u]: [sn:%i]: Data loaded was: %08p.\n",
|
||||
"[tid:%u]: [sn:%i]: Data loaded was: %08p\n",
|
||||
tid, inst->seqNum, inst->readIntResult(0));
|
||||
} else if(inst->isStore()) {
|
||||
assert(cache_pkt->isWrite());
|
||||
|
||||
DPRINTF(InOrderCachePort,
|
||||
"[tid:%u]: [sn:%i]: Data stored was: %08p.\n",
|
||||
"[tid:%u]: [sn:%i]: Data stored was: %08p\n",
|
||||
tid, inst->seqNum,
|
||||
getMemData(cache_pkt));
|
||||
|
||||
|
|
@ -509,8 +514,8 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
|
|||
cpu->switchToActive(stage_num);
|
||||
} else {
|
||||
DPRINTF(InOrderCachePort,
|
||||
"[tid:%u] Cache miss on memory access to block @ %08p "
|
||||
"completed, but squashed.\n", tid, cache_req->inst->readPC());
|
||||
"[tid:%u] Miss on block @ %08p completed, but squashed\n",
|
||||
tid, cache_req->inst->readPC());
|
||||
cache_req->setMemAccCompleted();
|
||||
}
|
||||
|
||||
|
|
@ -520,7 +525,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
|
|||
void
|
||||
CacheUnit::recvRetry()
|
||||
{
|
||||
DPRINTF(InOrderCachePort, "Retrying Request for [tid:%i] [sn:%i].\n",
|
||||
DPRINTF(InOrderCachePort, "Retrying Request for [tid:%i] [sn:%i]\n",
|
||||
retryReq->inst->readTid(), retryReq->inst->seqNum);
|
||||
|
||||
assert(retryPkt != NULL);
|
||||
|
|
@ -532,20 +537,20 @@ CacheUnit::recvRetry()
|
|||
retryPkt = NULL;
|
||||
cacheBlocked = false;
|
||||
} else {
|
||||
DPRINTF(InOrderCachePort, "Retry Request for [tid:%i] [sn:%i] failed.\n",
|
||||
DPRINTF(InOrderCachePort,
|
||||
"Retry Request for [tid:%i] [sn:%i] failed\n",
|
||||
retryReq->inst->readTid(), retryReq->inst->seqNum);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
CacheUnit::squash(DynInstPtr inst, int stage_num,
|
||||
InstSeqNum squash_seq_num, unsigned tid)
|
||||
{
|
||||
std::vector<int> slot_remove_list;
|
||||
vector<int> slot_remove_list;
|
||||
|
||||
std::map<int, ResReqPtr>::iterator map_it = reqMap.begin();
|
||||
std::map<int, ResReqPtr>::iterator map_end = reqMap.end();
|
||||
map<int, ResReqPtr>::iterator map_it = reqMap.begin();
|
||||
map<int, ResReqPtr>::iterator map_end = reqMap.end();
|
||||
|
||||
while (map_it != map_end) {
|
||||
ResReqPtr req_ptr = (*map_it).second;
|
||||
|
|
@ -555,7 +560,7 @@ CacheUnit::squash(DynInstPtr inst, int stage_num,
|
|||
req_ptr->getInst()->seqNum > squash_seq_num) {
|
||||
|
||||
DPRINTF(InOrderCachePort,
|
||||
"[tid:%i] Squashing request from [sn:%i].\n",
|
||||
"[tid:%i] Squashing request from [sn:%i]\n",
|
||||
req_ptr->getInst()->readTid(), req_ptr->getInst()->seqNum);
|
||||
|
||||
req_ptr->setSquashed();
|
||||
|
|
@ -578,13 +583,13 @@ CacheUnit::squash(DynInstPtr inst, int stage_num,
|
|||
}
|
||||
|
||||
// Now Delete Slot Entry from Req. Map
|
||||
for (int i = 0; i < slot_remove_list.size(); i++) {
|
||||
for (int i = 0; i < slot_remove_list.size(); i++)
|
||||
freeSlot(slot_remove_list[i]);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
uint64_t CacheUnit::getMemData(Packet *packet) {
|
||||
uint64_t
|
||||
CacheUnit::getMemData(Packet *packet)
|
||||
{
|
||||
switch (packet->getSize())
|
||||
{
|
||||
case 8:
|
||||
|
|
@ -600,10 +605,7 @@ uint64_t CacheUnit::getMemData(Packet *packet) {
|
|||
return packet->get<uint64_t>();
|
||||
|
||||
default:
|
||||
std::cerr << "bad store data size = " << packet->getSize() << std::endl;
|
||||
|
||||
assert(0);
|
||||
return 0;
|
||||
panic("bad store data size = %d\n", packet->getSize());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,8 @@ typedef CacheRequest* CacheReqPtr;
|
|||
class CacheReqPacket;
|
||||
typedef CacheReqPacket* CacheReqPktPtr;
|
||||
|
||||
class CacheUnit : public Resource {
|
||||
class CacheUnit : public Resource
|
||||
{
|
||||
public:
|
||||
typedef ThePipeline::DynInstPtr DynInstPtr;
|
||||
|
||||
|
|
@ -88,7 +89,8 @@ class CacheUnit : public Resource {
|
|||
public:
|
||||
/** Default constructor. */
|
||||
CachePort(CacheUnit *_cachePortUnit)
|
||||
: Port(_cachePortUnit->name() + "-cache-port", (MemObject*)_cachePortUnit->cpu),
|
||||
: Port(_cachePortUnit->name() + "-cache-port",
|
||||
(MemObject*)_cachePortUnit->cpu),
|
||||
cachePortUnit(_cachePortUnit)
|
||||
{ }
|
||||
|
||||
|
|
@ -214,15 +216,16 @@ class CacheUnit : public Resource {
|
|||
/** @todo: Add Resource Stats Here */
|
||||
};
|
||||
|
||||
struct CacheSchedEntry : public ThePipeline::ScheduleEntry {
|
||||
struct CacheSchedEntry : public ThePipeline::ScheduleEntry
|
||||
{
|
||||
enum EntryType {
|
||||
FetchAccess,
|
||||
DataAccess
|
||||
};
|
||||
|
||||
CacheSchedEntry(int stage_num, int _priority, int res_num, MemCmd::Command pkt_cmd,
|
||||
EntryType _type = FetchAccess) :
|
||||
ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
|
||||
CacheSchedEntry(int stage_num, int _priority, int res_num,
|
||||
MemCmd::Command pkt_cmd, EntryType _type = FetchAccess)
|
||||
: ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
|
||||
type(_type)
|
||||
{ }
|
||||
|
||||
|
|
@ -230,7 +233,8 @@ struct CacheSchedEntry : public ThePipeline::ScheduleEntry {
|
|||
EntryType type;
|
||||
};
|
||||
|
||||
class CacheRequest : public ResourceRequest {
|
||||
class CacheRequest : public ResourceRequest
|
||||
{
|
||||
public:
|
||||
CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
|
||||
int slot_num, unsigned cmd, int req_size,
|
||||
|
|
@ -246,10 +250,10 @@ class CacheRequest : public ResourceRequest {
|
|||
|
||||
virtual ~CacheRequest()
|
||||
{
|
||||
/*
|
||||
#if 0
|
||||
delete reqData;
|
||||
|
||||
Can get rid of packet and packet request now
|
||||
// Can get rid of packet and packet request now
|
||||
if (*dataPkt) {
|
||||
if (*dataPkt->req) {
|
||||
delete dataPkt->req;
|
||||
|
|
@ -263,17 +267,22 @@ class CacheRequest : public ResourceRequest {
|
|||
delete retryPkt->req;
|
||||
}
|
||||
delete retryPkt;
|
||||
}*/
|
||||
|
||||
if (memReq) {
|
||||
delete memReq;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (memReq)
|
||||
delete memReq;
|
||||
}
|
||||
|
||||
virtual PacketDataPtr getData()
|
||||
{ return reqData; }
|
||||
|
||||
void setMemAccCompleted(bool completed = true) { memAccComplete = completed; }
|
||||
void
|
||||
setMemAccCompleted(bool completed = true)
|
||||
{
|
||||
memAccComplete = completed;
|
||||
}
|
||||
|
||||
bool isMemAccComplete() { return memAccComplete; }
|
||||
|
||||
void setMemAccPending(bool pending = true) { memAccPending = pending; }
|
||||
|
|
@ -290,7 +299,8 @@ class CacheRequest : public ResourceRequest {
|
|||
bool memAccPending;
|
||||
};
|
||||
|
||||
class CacheReqPacket : public Packet {
|
||||
class CacheReqPacket : public Packet
|
||||
{
|
||||
public:
|
||||
CacheReqPacket(CacheRequest *_req,
|
||||
Command _cmd, short _dest)
|
||||
|
|
|
|||
Loading…
Reference in a new issue