Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
Hand merged
--HG--
extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
This commit is contained in:
Gabe Black
commit
cf2f7e13bc
6 changed files with 352 additions and 359 deletions
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@ -5,15 +5,19 @@
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output header {{
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struct condCodes
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union CondCodes
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{
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struct
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{
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uint8_t c:1;
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uint8_t v:1;
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uint8_t z:1;
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uint8_t n:1;
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};
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uint32_t bits;
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};
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enum condTest
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enum CondTest
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{
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Always=0x8,
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Never=0x0,
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@ -52,7 +56,28 @@ output header {{
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void printReg(std::ostream &os, int reg) const;
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};
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bool passesCondition(condCodes codes, condTest condition);
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bool passesCondition(uint32_t codes, uint32_t condition);
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}};
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def template ROrImmDecode {{
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{
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return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
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: (SparcStaticInst *)(new %(class_name)s(machInst)));
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}
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}};
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let {{
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def splitOutImm(code):
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matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})')
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rOrImmMatch = matcher.search(code)
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if (rOrImmMatch == None):
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return (False, CodeBlock(code), None, '', '')
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rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string)
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iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string)
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orig_code = code
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code = matcher.sub(r'Rs(?P<rNum>)', orig_code)
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imm_code = matcher.sub('imm', orig_code)
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return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString)
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}};
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output decoder {{
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@ -100,8 +125,10 @@ output decoder {{
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return ss.str();
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}
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bool passesCondition(condCodes codes, condTest condition)
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bool passesCondition(uint32_t codes, uint32_t condition)
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{
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CondCodes condCodes;
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condCodes.bits = codes;
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switch(condition)
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{
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case Always:
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@ -109,33 +136,33 @@ output decoder {{
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case Never:
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return false;
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case NotEqual:
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return !codes.z;
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return !condCodes.z;
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case Equal:
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return codes.z;
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return condCodes.z;
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case Greater:
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return !(codes.z | (codes.n ^ codes.v));
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return !(condCodes.z | (condCodes.n ^ condCodes.v));
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case LessOrEqual:
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return codes.z | (codes.n ^ codes.v);
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return condCodes.z | (condCodes.n ^ condCodes.v);
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case GreaterOrEqual:
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return !(codes.n ^ codes.v);
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return !(condCodes.n ^ condCodes.v);
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case Less:
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return (codes.n ^ codes.v);
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return (condCodes.n ^ condCodes.v);
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case GreaterUnsigned:
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return !(codes.c | codes.z);
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return !(condCodes.c | condCodes.z);
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case LessOrEqualUnsigned:
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return (codes.c | codes.z);
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return (condCodes.c | condCodes.z);
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case CarryClear:
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return !codes.c;
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return !condCodes.c;
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case CarrySet:
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return codes.c;
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return condCodes.c;
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case Positive:
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return !codes.n;
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return !condCodes.n;
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case Negative:
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return codes.n;
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return condCodes.n;
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case OverflowClear:
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return !codes.v;
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return !condCodes.v;
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case OverflowSet:
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return codes.v;
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return condCodes.v;
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}
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panic("Tried testing condition nonexistant "
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"condition code %d", condition);
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@ -6,187 +6,125 @@
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decode OP default Unknown::unknown()
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{
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0x0: decode OP2
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{
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format Branch
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{
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//Throw an illegal instruction acception
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0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
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0x1: Branch::bpcc({{
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switch(BPCC)
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0x1: decode BPCC
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{
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case 1:
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case 3:
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fault = new IllegalInstruction;
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case 0:
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0x0: bpcci({{
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if(passesCondition(CcrIcc, COND2))
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;//branchHere
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break;
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case 2:
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}});
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0x2: bpccx({{
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if(passesCondition(CcrXcc, COND2))
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;//branchHere
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break;
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}});
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}
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}});//BPcc
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0x2: Branch::bicc({{
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0x2: bicc({{
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if(passesCondition(CcrIcc, COND2))
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;//branchHere
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}});//Bicc
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0x3: Branch::bpr({{
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switch(RCOND2)
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}});
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0x3: decode RCOND2
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{
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case 0:
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case 4:
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fault = new IllegalInstruction;
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case 1:
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0x1: bpreq({{
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if(Rs1 == 0)
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;//branchHere
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break;
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case 2:
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}});
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0x2: bprle({{
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if(Rs1 <= 0)
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;//branchHere
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break;
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case 3:
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}});
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0x3: bprl({{
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if(Rs1 < 0)
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;//branchHere
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break;
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case 5:
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}});
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0x5: bprne({{
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if(Rs1 != 0)
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;//branchHere
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break;
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case 6:
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}});
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0x6: bprg({{
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if(Rs1 > 0)
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;//branchHere
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break;
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case 7:
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}});
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0x7: bprge({{
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if(Rs1 >= 0)
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;//branchHere
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break;
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}});
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}
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}}); //BPr
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//SETHI (or NOP if rd == 0 and imm == 0)
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0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
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0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
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0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
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0x6: Trap::fbfcc({{fault = new FpDisabled;}});
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}
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}
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0x1: Branch::call({{
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//branch here
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Rd = xc->pc;
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Rd = xc->readPC();
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}});
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0x2: decode OP3 {
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format IntegerOp {
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0x00: add({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
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Rd = Rs1.sdw + val2;
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}});//ADD
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0x01: and({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & val2;
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}});//AND
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0x02: or({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | val2;
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}});//OR
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0x03: xor({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw ^ val2;
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}});//XOR
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0x04: sub({{
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int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
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Rd = Rs1.sdw + val2;
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}});//SUB
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0x05: andn({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & ~val2;
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}});//ANDN
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0x06: orn({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | ~val2;
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}});//ORN
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0x07: xnor({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = ~(Rs1.udw ^ val2);
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}});//XNOR
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0x08: addc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
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int64_t carryin = CcrIccC;
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Rd = Rs1.sdw + val2 + carryin;
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}});//ADDC
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0x09: mulx({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 * val2;
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}});//MULX
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format IntOp {
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0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
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0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
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0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
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0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
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0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}});
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0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}});
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0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}});
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0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}});
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0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}});
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0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}});
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0x0A: umul({{
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uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;
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}});//UMUL
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Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>;
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YValue = Rd<63:32>;
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}});
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0x0B: smul({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
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rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;
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}});//SMUL
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0x0C: subc({{
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int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
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int64_t carryin = CcrIccC;
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Rd.sdw = Rs1.sdw + val2 + carryin;
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}});//SUBC
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Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>;
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YValue = Rd.sdw;
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}});
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0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}});
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0x0D: udivx({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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if(val2 == 0) fault = new DivisionByZero;
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else Rd.udw = Rs1.udw / val2;
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}});//UDIVX
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else Rd.udw = Rs1.udw / Rs2_or_imm;
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}});
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0x0E: udiv({{
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uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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if(val2 == 0)
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fault = new DivisionByZero;
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resTemp = (uint64_t)((YValue << 32)
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| Rs1.udw<31:0>) / val2;
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int32_t overflow = (resTemp<63:32> != 0);
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if(overflow)
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rd.udw = resTemp = 0xFFFFFFFF;
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uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
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if(Rs2_or_imm.udw == 0) fault = new DivisionByZero;
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else
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rd.udw = resTemp;
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}}); //UDIV
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{
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Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw;
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if(Rd.udw >> 32 != 0)
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Rd.udw = 0xFFFFFFFF;
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}
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}});
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0x0F: sdiv({{
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int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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if(val2 == 0)
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fault = new DivisionByZero;
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Rd.sdw = (int64_t)((YValue << 32) |
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Rs1.sdw<31:0>) / val2;
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resTemp = Rd.sdw;
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int32_t overflow = (resTemp<63:31> != 0);
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int32_t underflow =
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(resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow)
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rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow)
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rd.udw = resTemp = 0xFFFFFFFF80000000;
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else
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rd.udw = resTemp;
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{
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Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm;
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if(Rd.udw<63:31> != 0)
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Rd.udw = 0x7FFFFFFF;
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else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
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Rd.udw = 0xFFFFFFFF80000000;
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}
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}});//SDIV
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}
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format IntegerOpCc {
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format IntOpCc {
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0x10: addcc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
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Rd = resTemp = Rs1 + val2;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDcc
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0x11: andcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
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Rd = Rs1 & val2;}},
|
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{{0}},{{0}},{{0}},{{0}});//ANDcc
|
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0x12: orcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
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Rd = Rs1 | val2;}},
|
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{{0}},{{0}},{{0}},{{0}});//ORcc
|
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0x13: xorcc({{
|
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
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Rd = Rs1 ^ val2;}},
|
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{{0}},{{0}},{{0}},{{0}});//XORcc
|
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0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
|
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0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
|
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0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
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0x14: subcc({{
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int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
|
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int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
|
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Rd = resTemp = Rs1 - val2;}},
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{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
|
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
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|
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@ -194,20 +132,11 @@ decode OP default Unknown::unknown()
|
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((Rs1 | ~val2) & 0x1))<63:>}},
|
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
|
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);//SUBcc
|
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0x15: andncc({{
|
||||
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
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Rd = Rs1 & ~val2;}},
|
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{{0}},{{0}},{{0}},{{0}});//ANDNcc
|
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0x16: orncc({{
|
||||
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
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Rd = Rs1 | ~val2;}},
|
||||
{{0}},{{0}},{{0}},{{0}});//ORNcc
|
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0x17: xnorcc({{
|
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
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Rd = ~(Rs1 ^ val2);}},
|
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{{0}},{{0}},{{0}},{{0}});//XNORcc
|
||||
0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
|
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0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
|
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0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
|
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0x18: addccc({{
|
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
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int64_t carryin = CcrIccC;
|
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Rd = resTemp = Rs1 + val2 + carryin;}},
|
||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
|
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|
|
@ -218,17 +147,17 @@ decode OP default Unknown::unknown()
|
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//ADDCcc
|
||||
0x1A: umulcc({{
|
||||
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
uint64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
||||
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
|
||||
YValue = resTemp<63:32>;}},
|
||||
{{0}},{{0}},{{0}},{{0}});//UMULcc
|
||||
0x1B: smulcc({{
|
||||
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
||||
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
|
||||
YValue = resTemp<63:32>;}}
|
||||
,{{0}},{{0}},{{0}},{{0}});//SMULcc
|
||||
0x1C: subccc({{
|
||||
int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
|
||||
int64_t carryin = CcrIccC;
|
||||
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
|
||||
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
|
||||
|
|
@ -237,12 +166,12 @@ decode OP default Unknown::unknown()
|
|||
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
|
||||
);//SUBCcc
|
||||
0x1D: udivxcc({{
|
||||
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||
uint64_t val2 = (I ? SIMM13 : Rs2.udw);
|
||||
if(val2 == 0) fault = new DivisionByZero;
|
||||
else Rd.udw = Rs1.udw / val2;}}
|
||||
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
|
||||
0x1E: udivcc({{
|
||||
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
|
||||
uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
|
||||
if(val2 == 0) fault = new DivisionByZero;
|
||||
else
|
||||
{
|
||||
|
|
@ -257,7 +186,7 @@ decode OP default Unknown::unknown()
|
|||
{{0}}
|
||||
);//UDIVcc
|
||||
0x1F: sdivcc({{
|
||||
int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
|
||||
int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>);
|
||||
if(val2 == 0) fault = new DivisionByZero;
|
||||
else
|
||||
{
|
||||
|
|
@ -274,7 +203,7 @@ decode OP default Unknown::unknown()
|
|||
{{0}}
|
||||
);//SDIVcc
|
||||
0x20: taddcc({{
|
||||
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||
|
|
@ -283,7 +212,7 @@ decode OP default Unknown::unknown()
|
|||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TADDcc
|
||||
0x21: tsubcc({{
|
||||
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
||||
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||
|
|
@ -292,7 +221,7 @@ decode OP default Unknown::unknown()
|
|||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TSUBcc
|
||||
0x22: taddcctv({{
|
||||
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
||||
if(overflow) fault = new TagOverflow;}},
|
||||
|
|
@ -302,7 +231,7 @@ decode OP default Unknown::unknown()
|
|||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TADDccTV
|
||||
0x23: tsubcctv({{
|
||||
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
||||
if(overflow) fault = new TagOverflow;}},
|
||||
|
|
@ -312,7 +241,7 @@ decode OP default Unknown::unknown()
|
|||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TSUBccTV
|
||||
0x24: mulscc({{
|
||||
int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
|
||||
int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2);
|
||||
int32_t multiplier = Rs1<31:0>;
|
||||
int32_t savedLSB = Rs1<0:>;
|
||||
multiplier = multipler<31:1> |
|
||||
|
|
@ -328,18 +257,18 @@ decode OP default Unknown::unknown()
|
|||
{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
|
||||
);//MULScc
|
||||
}
|
||||
format IntegerOp
|
||||
format IntOp
|
||||
{
|
||||
0x25: decode X {
|
||||
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
|
||||
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
|
||||
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
|
||||
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
|
||||
}
|
||||
0x26: decode X {
|
||||
0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
|
||||
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
|
||||
0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
|
||||
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
|
||||
}
|
||||
0x27: decode X {
|
||||
0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
|
||||
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
|
||||
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
|
||||
}
|
||||
0x28: decode RS1 {
|
||||
|
|
@ -358,16 +287,16 @@ decode OP default Unknown::unknown()
|
|||
format Priv
|
||||
{
|
||||
0x0: rdprtpc({{
|
||||
Rd = xc->readMiscReg(MISCREG_TPC_BASE + tl);
|
||||
Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
|
||||
}});
|
||||
0x1: rdprtnpc({{
|
||||
Rd = xc->readMiscReg(MISCREG_TNPC_BASE + tl);
|
||||
Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
|
||||
}});
|
||||
0x2: rdprtstate({{
|
||||
Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + tl);
|
||||
Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
|
||||
}});
|
||||
0x3: rdprtt({{
|
||||
Rd = xc->readMiscReg(MISCREG_TT_BASE + tl);
|
||||
Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
|
||||
}});
|
||||
0x4: rdprtick({{Rd = Tick;}});
|
||||
0x5: rdprtba({{Rd = Tba;}});
|
||||
|
|
@ -385,110 +314,74 @@ decode OP default Unknown::unknown()
|
|||
0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
|
||||
0x1F: Priv::rdprver({{Rd = Ver;}});
|
||||
}
|
||||
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
|
||||
0x2C: movcc({{
|
||||
ccBank = (MOVCC3 << 2) | CC;
|
||||
switch(ccBank)
|
||||
0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW
|
||||
0x2C: decode MOVCC3
|
||||
{
|
||||
case 0: case 1: case 2: case 3:
|
||||
fault = new FpDisabled;
|
||||
break;
|
||||
case 5: case 7:
|
||||
fault = new IllegalInstruction;
|
||||
break;
|
||||
case 4:
|
||||
0x0: Trap::movccfcc({{fault = new FpDisabled}});
|
||||
0x1: decode CC
|
||||
{
|
||||
0x0: movcci({{
|
||||
if(passesCondition(CcrIcc, COND4))
|
||||
Rd = (I ? SIMM11.sdw : RS2);
|
||||
break;
|
||||
case 6:
|
||||
Rd = (I ? SIMM11 : RS2);
|
||||
}});
|
||||
0x2: movccx({{
|
||||
if(passesCondition(CcrXcc, COND4))
|
||||
Rd = (I ? SIMM11.sdw : RS2);
|
||||
break;
|
||||
Rd = (I ? SIMM11 : RS2);
|
||||
}});
|
||||
}
|
||||
}
|
||||
}});//MOVcc
|
||||
0x2D: sdivx({{
|
||||
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
if(val2 == 0) fault = new DivisionByZero;
|
||||
else Rd.sdw = Rs1.sdw / val2;
|
||||
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
|
||||
else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
|
||||
}});//SDIVX
|
||||
0x2E: decode RS1 {
|
||||
0x0: IntegerOp::popc({{
|
||||
int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
|
||||
0x0: IntOp::popc({{
|
||||
int64_t count = 0, val2 = Rs2_or_imm;
|
||||
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
|
||||
for(unsigned int x = 0; x < 16; x++)
|
||||
{
|
||||
count += oneBits[val2 & 0xF];
|
||||
count += oneBits[Rs2_or_imm13 & 0xF];
|
||||
val2 >> 4;
|
||||
}
|
||||
}});//POPC
|
||||
}
|
||||
0x2F: movr({{
|
||||
uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
|
||||
switch(RCOND3)
|
||||
0x2F: decode RCOND3
|
||||
{
|
||||
case 0: case 4:
|
||||
fault = IllegalInstruction;
|
||||
break;
|
||||
case 1:
|
||||
if(Rs1 == 0) Rd = val2;
|
||||
break;
|
||||
case 2:
|
||||
if(Rs1 <= 0) Rd = val2;
|
||||
break;
|
||||
case 3:
|
||||
if(Rs1 = 0) Rd = val2;
|
||||
break;
|
||||
case 5:
|
||||
if(Rs1 != 0) Rd = val2;
|
||||
break;
|
||||
case 6:
|
||||
if(Rs1 > 0) Rd = val2;
|
||||
break;
|
||||
case 7:
|
||||
if(Rs1 >= 0) Rd = val2;
|
||||
break;
|
||||
0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
|
||||
0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
|
||||
0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
|
||||
0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
|
||||
0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
|
||||
0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
|
||||
}
|
||||
}});//MOVR
|
||||
0x30: decode RD {
|
||||
0x0: wry({{
|
||||
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
Y = Rs1 ^ val2;
|
||||
}});//WRY
|
||||
0x2: wrccr({{
|
||||
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
Ccr = Rs1 ^ val2;
|
||||
}});//WRCCR
|
||||
0x3: wrasi({{
|
||||
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
Asi = Rs1 ^ val2;
|
||||
}});//WRASI
|
||||
0x6: wrfprs({{
|
||||
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
Asi = Rs1 ^ val2;
|
||||
}});//WRFPRS
|
||||
0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
|
||||
0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
|
||||
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
|
||||
}
|
||||
0x31: decode FCN {
|
||||
0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
|
||||
0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
|
||||
0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED
|
||||
0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED
|
||||
}
|
||||
0x32: decode RD {
|
||||
format Priv
|
||||
{
|
||||
0x0: wrprtpc({{
|
||||
xc->setMiscReg(MISCREG_TPC_BASE + tl,
|
||||
xc->setMiscReg(MISCREG_TPC_BASE + Tl,
|
||||
Rs1 ^ Rs2_or_imm13);
|
||||
}});
|
||||
0x1: wrprtnpc({{
|
||||
xc->setMiscReg(MISCREG_TNPC_BASE + tl,
|
||||
xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
|
||||
Rs1 ^ Rs2_or_imm13);
|
||||
}});
|
||||
0x2: wrprtstate({{
|
||||
xc->setMiscReg(MISCREG_TSTATE_BASE + tl,
|
||||
xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
|
||||
Rs1 ^ Rs2_or_imm13);
|
||||
}});
|
||||
0x3: wrprtt({{
|
||||
xc->setMiscReg(MISCREG_TT_BASE + tl,
|
||||
xc->setMiscReg(MISCREG_TT_BASE + Tl,
|
||||
Rs1 ^ Rs2_or_imm13);
|
||||
}});
|
||||
0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
|
||||
|
|
@ -508,7 +401,6 @@ decode OP default Unknown::unknown()
|
|||
0x34: Trap::fpop1({{fault = new FpDisabled;}});
|
||||
0x35: Trap::fpop2({{fault = new FpDisabled;}});
|
||||
|
||||
|
||||
0x38: Branch::jmpl({{//Stuff}}); //JMPL
|
||||
0x39: Branch::return({{//Other Stuff}}); //RETURN
|
||||
0x3A: decode CC
|
||||
|
|
@ -517,7 +409,7 @@ decode OP default Unknown::unknown()
|
|||
#if FULL_SYSTEM
|
||||
fault = new TrapInstruction;
|
||||
#else
|
||||
if(passesCondition(ccr_icc, machInst<25:28>))
|
||||
if(passesCondition(CcrIcc, machInst<25:28>))
|
||||
// At least glibc only uses trap 0,
|
||||
// solaris/sunos may use others
|
||||
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
|
||||
|
|
@ -528,7 +420,7 @@ decode OP default Unknown::unknown()
|
|||
#if FULL_SYSTEM
|
||||
fault = new TrapInstruction;
|
||||
#else
|
||||
if(passesCondition(ccr_xcc, machInst<25:28>))
|
||||
if(passesCondition(CcrXcc, machInst<25:28>))
|
||||
// At least glibc only uses trap 0,
|
||||
// solaris/sunos may use others
|
||||
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
|
||||
|
|
@ -637,8 +529,8 @@ decode OP default Unknown::unknown()
|
|||
Rd.uw = val;
|
||||
}}); //CASA
|
||||
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
|
||||
0x3E: Cas::casxa(
|
||||
{{uint64_t val = Mem.udw;
|
||||
0x3E: Cas::casxa({{
|
||||
uint64_t val = Mem.udw;
|
||||
if(Rs2 == val)
|
||||
Mem.udw = Rd;
|
||||
Rd = val;
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@ output header {{
|
|||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class IntegerOp : public SparcStaticInst
|
||||
class IntOp : public SparcStaticInst
|
||||
{
|
||||
protected:
|
||||
// Constructor
|
||||
IntegerOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
|
||||
IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
|
||||
SparcStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
|
@ -19,24 +19,68 @@ output header {{
|
|||
std::string generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for 10 bit immediate integer operations.
|
||||
*/
|
||||
class IntOpImm10 : public IntOp
|
||||
{
|
||||
protected:
|
||||
// Constructor
|
||||
IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
|
||||
IntOp(mnem, _machInst, __opClass), imm(SIMM10)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t imm;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for 13 bit immediate integer operations.
|
||||
*/
|
||||
class IntOpImm13 : public IntOp
|
||||
{
|
||||
protected:
|
||||
// Constructor
|
||||
IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
|
||||
IntOp(mnem, _machInst, __opClass), imm(SIMM13)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t imm;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string IntegerOp::generateDisassembly(Addr pc,
|
||||
std::string IntOp::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return "Integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template IntegerExecute {{
|
||||
def template IntOpExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
if(fault == NoFault)
|
||||
%(op_wb)s;
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template IntOpCcExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault;
|
||||
//These are set to constants when the execute method
|
||||
//is generated
|
||||
bool useCc = ;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
|
@ -46,8 +90,6 @@ def template IntegerExecute {{
|
|||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
if(useCc)
|
||||
{
|
||||
CcrIccN = Rd & (1 << 63);
|
||||
CcrIccZ = (Rd == 0);
|
||||
CcrIccV = ivValue;
|
||||
|
|
@ -57,35 +99,67 @@ def template IntegerExecute {{
|
|||
CcrXccV = xvValue;
|
||||
CcrXccC = xcValue;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template IntOpCcResExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
CcrIccN = Rd & (1 << 63);
|
||||
CcrIccZ = (Rd == 0);
|
||||
CcrXccN = Rd & (1 << 31);
|
||||
CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
|
||||
CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format IntegerOp(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
|
||||
('xvValue', '0'), ('xcValue', '0')):
|
||||
code.replace(marker, value)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
let {{
|
||||
def doIntFormat(code, execTemplate, name, Name, opt_flags):
|
||||
(usesImm, cblk, immCblk, rString, iString) = splitOutImm(code)
|
||||
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
exec_output = execTemplate.subst(iop)
|
||||
if usesImm:
|
||||
imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
|
||||
immCblk, opt_flags)
|
||||
header_output += BasicDeclare.subst(imm_iop)
|
||||
decoder_output += BasicConstructor.subst(imm_iop)
|
||||
exec_output += execTemplate.subst(imm_iop)
|
||||
decode_block = ROrImmDecode.subst(iop)
|
||||
else:
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = IntegerExecute.subst(iop)
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
def format IntOp(code, *opt_flags) {{
|
||||
doIntFormat(code, IntOpExecute, name, Name, opt_flags)
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
|
||||
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
|
||||
('xvValue', xvValue), ('xcValue', xcValue)):
|
||||
code.replace(marker, value)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = IntegerExecute.subst(iop)
|
||||
doIntFormat(code, IntOpCcExecute, name, Name, opt_flags)
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format IntOpCcRes(code, *opt_flags) {{
|
||||
doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags)
|
||||
}};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Privelege mode instructions
|
||||
// Privilege mode instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
|
|
@ -92,8 +92,8 @@ def template PrivExecute {{
|
|||
%(op_rd)s;
|
||||
|
||||
//If the processor isn't in privileged mode, fault out right away
|
||||
if(!pstate_priv)
|
||||
return new PrivilegedOpCode
|
||||
if(!PstatePriv)
|
||||
return new PrivilegedOpcode
|
||||
|
||||
%(code)s;
|
||||
%(op_wb)s;
|
||||
|
|
@ -108,7 +108,7 @@ def template PrivTickExecute {{
|
|||
%(op_rd)s;
|
||||
|
||||
//If the processor isn't in privileged mode, fault out right away
|
||||
if(!pstate_priv && tick_npt)
|
||||
if(!PstatePriv && TickNpt)
|
||||
return new PrivilegedAction
|
||||
|
||||
%(code)s;
|
||||
|
|
@ -116,20 +116,13 @@ def template PrivTickExecute {{
|
|||
}
|
||||
}};
|
||||
|
||||
def template Rb2OrImm13Decode {{
|
||||
{
|
||||
return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
|
||||
: (SparcStaticInst *)(new %(class_name)s(machInst)));
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Priv(code, *opt_flags) {{
|
||||
uses_imm = (code.find('Rs2_or_imm13') != -1)
|
||||
if uses_imm:
|
||||
orig_code = code
|
||||
code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
|
||||
imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
|
||||
code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
|
||||
imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
|
|
@ -142,7 +135,7 @@ def format Priv(code, *opt_flags) {{
|
|||
header_output += BasicDeclare.subst(imm_iop)
|
||||
decoder_output += BasicConstructor.subst(imm_iop)
|
||||
exec_output += PrivExecute.subst(imm_iop)
|
||||
decode_block = Rb2OrImm13Decode.subst(iop)
|
||||
decode_block = ROrImmDecode.subst(iop)
|
||||
else:
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
}};
|
||||
|
|
@ -152,8 +145,8 @@ def format PrivTick(code, *opt_flags) {{
|
|||
uses_imm = (code.find('Rs2_or_imm13') != -1)
|
||||
if uses_imm:
|
||||
orig_code = code
|
||||
code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
|
||||
imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
|
||||
code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
|
||||
imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
|
|
@ -166,7 +159,7 @@ def format PrivTick(code, *opt_flags) {{
|
|||
header_output += BasicDeclare.subst(imm_iop)
|
||||
decoder_output += BasicConstructor.subst(imm_iop)
|
||||
exec_output += PrivTickExecute.subst(imm_iop)
|
||||
decode_block = Rb2OrImm13Decode.subst(iop)
|
||||
decode_block = Rb2OrImmDecode.subst(iop)
|
||||
else:
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
}};
|
||||
|
|
|
|||
|
|
@ -98,6 +98,11 @@ namespace SparcISA
|
|||
typedef uint32_t MachInst;
|
||||
typedef uint64_t ExtMachInst;
|
||||
|
||||
inline ExtMachInst
|
||||
makeExtMI(MachInst inst, const Addr &pc) {
|
||||
return ExtMachInst(inst);
|
||||
}
|
||||
|
||||
const int NumIntRegs = 32;
|
||||
const int NumFloatRegs = 64;
|
||||
const int NumMiscRegs = 32;
|
||||
|
|
|
|||
|
|
@ -79,11 +79,13 @@ static inline uint64_t swap_byte(uint64_t x) {return swap_byte64(x);}
|
|||
static inline int64_t swap_byte(int64_t x) {return swap_byte64((uint64_t)x);}
|
||||
static inline uint32_t swap_byte(uint32_t x) {return swap_byte32(x);}
|
||||
static inline int32_t swap_byte(int32_t x) {return swap_byte32((uint32_t)x);}
|
||||
//#if defined(__APPLE__)
|
||||
//This is to prevent the following two functions from compiling on
|
||||
//64bit machines. It won't detect everything, so it should be changed.
|
||||
#ifndef __x86_64__
|
||||
static inline long swap_byte(long x) {return swap_byte32((long)x);}
|
||||
static inline unsigned long swap_byte(unsigned long x)
|
||||
{ return swap_byte32((unsigned long)x);}
|
||||
//#endif
|
||||
#endif
|
||||
static inline uint16_t swap_byte(uint16_t x) {return swap_byte32(x);}
|
||||
static inline int16_t swap_byte(int16_t x) {return swap_byte16((uint16_t)x);}
|
||||
static inline uint8_t swap_byte(uint8_t x) {return x;}
|
||||
|
|
|
|||
Loading…
Reference in a new issue