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emulate callpal halt for non FULL_SYSTEM

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in the process make m5_exit more generic

arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    There's no reason that this needs to be in an arch specific file
arch/alpha/isa_desc:
    m5_exit -> SimExit
    Emulate callpal halt and cause the simulator to exit
    while we're at it, sort #includes
sim/sim_events.cc:
sim/sim_events.hh:
    move the m5_exit function here, renaming it to SimExit.
    Also Allow the caller to pass in the termination message.

--HG--
extra : convert_revision : 54b43b17a412ab387b8672c27ef0b04fce10ee15
This commit is contained in:
Nathan Binkert 2003-10-28 10:05:58 -05:00
parent 5cf0b0541b
commit cec7f73abf
5 changed files with 18 additions and 15 deletions
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6
arch/alpha/ev5.cc
View file

@ -54,12 +54,6 @@ AlphaISA::initCPU(RegFile *regs)
regs->npc = regs->pc + sizeof(MachInst);
}
void
m5_exit()
{
static SimExitEvent event("m5_exit instruction encountered");
}
////////////////////////////////////////////////////////////////////////
//
// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE

2
arch/alpha/ev5.hh
View file

@ -9,8 +9,6 @@
#include "targetarch/isa_traits.hh"
void m5_exit();
////////////////////////////////////////////////////////////////////////
//
//

18
arch/alpha/isa_desc
View file

@ -18,17 +18,17 @@ let {{
#include <fenv.h>
#endif
#include "cpu/static_inst.hh"
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "cpu/full_cpu/op_class.hh"
#include "cpu/exec_context.hh"
#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/full_cpu/spec_state.hh"
#include "cpu/full_cpu/full_cpu.hh"
#include "cpu/exetrace.hh"
#include "cpu/full_cpu/full_cpu.hh"
#include "cpu/full_cpu/op_class.hh"
#include "cpu/full_cpu/spec_state.hh"
#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/static_inst.hh"
#include "sim/annotation.hh"
#include "sim/sim_events.hh"
#ifdef FULL_SYSTEM
#include "targetarch/ev5.hh"
@ -2356,6 +2356,10 @@ decode OPCODE default Unknown::unknown() {
#else
0x00: decode PALFUNC {
format EmulatedCallPal {
0x00: halt ({{
if (!xc->misspeculating())
SimExit("halt instruction encountered");
}});
0x83: callsys({{ xc->syscall(); }});
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});
@ -2414,7 +2418,7 @@ decode OPCODE default Unknown::unknown() {
}}, No_OpClass);
0x20: m5exit({{
if (!xc->misspeculating())
m5_exit();
SimExit("m5_exit instruction encountered");
}}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
0x40: resetstats({{

5
sim/sim_events.cc
View file

@ -63,6 +63,11 @@ SimExitEvent::description()
return "simulation termination";
}
void
SimExit(const char *message)
{
static SimExitEvent event(message);
}
//
// constructor: automatically schedules at specified time

2
sim/sim_events.hh
View file

@ -66,6 +66,8 @@ class SimExitEvent : public Event
virtual const char *description();
};
void SimExit(const char *message);
//
// Event class to terminate simulation after 'n' related events have
// occurred using a shared counter: used to terminate when *all*