ARM: Centralize the declaration of resTemp.
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776a06fd39
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2 changed files with 36 additions and 61 deletions
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@ -83,30 +83,25 @@ format DataOp {
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1: decode MISC_OPCODE {
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0x9: decode PREPOST {
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0: decode OPCODE {
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0x0: mul({{ uint32_t resTemp;
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Rn = resTemp = Rm * Rs; }},
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0x0: mul({{ Rn = resTemp = Rm * Rs; }},
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{{ Cpsr<29:> }},
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{{ Cpsr<28:> }});
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0x1: mla({{ uint32_t resTemp;
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Rn = resTemp = Rm * Rs; }},
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0x1: mla({{ Rn = resTemp = Rm * Rs; }},
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{{ Cpsr<29:> }},
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{{ Cpsr<28:> }});
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0x2: WarnUnimpl::umall();
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0x4: umull({{
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uint64_t resTemp;
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resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
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Rd = (uint32_t)(resTemp & 0xffffffff);
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Rn = (uint32_t)(resTemp >> 32);
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}}, {{ 1 }}, {{ 1 }});
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0x5: WarnUnimpl::smlal();
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0x6: smull({{
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int64_t resTemp;
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resTemp = ((int64_t)Rm.sw)*((int64_t)Rs.sw);
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Rd = (int32_t)(resTemp & 0xffffffff);
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Rn = (int32_t)(resTemp >> 32);
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}}, {{ 1 }}, {{ 1 }});
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0x7: umlal({{
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uint64_t resTemp;
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resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
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resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
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Rd = (uint32_t)(resTemp & 0xffffffff);
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@ -231,66 +226,61 @@ format DataOp {
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}
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0: decode IS_MISC {
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0: decode OPCODE {
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0x0: and({{ uint32_t resTemp;
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Rd = resTemp = Rn & op2; }},
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0x0: and({{ Rd = resTemp = Rn & op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0x1: eor({{ uint32_t resTemp;
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Rd = resTemp = Rn ^ op2; }},
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0x1: eor({{ Rd = resTemp = Rn ^ op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0x2: sub({{ uint32_t resTemp, val2 = op2;
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0x2: sub({{ uint32_t val2 = op2;
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Rd = resTemp = Rn - val2; }},
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{{ arm_sub_carry(resTemp, Rn, val2) }},
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{{ arm_sub_overflow(resTemp, Rn, val2) }});
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0x3: rsb({{ uint32_t resTemp, val2 = op2;
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0x3: rsb({{ uint32_t val2 = op2;
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Rd = resTemp = val2 - Rn; }},
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{{ arm_sub_carry(resTemp, val2, Rn) }},
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{{ arm_sub_overflow(resTemp, val2, Rn) }});
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0x4: add({{ uint32_t resTemp, val2 = op2;
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0x4: add({{ uint32_t val2 = op2;
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Rd = resTemp = Rn + val2; }},
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{{ arm_add_carry(resTemp, Rn, val2) }},
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{{ arm_add_overflow(resTemp, Rn, val2) }});
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0x5: adc({{ uint32_t resTemp, val2 = op2;
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0x5: adc({{ uint32_t val2 = op2;
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Rd = resTemp = Rn + val2 + Cpsr<29:>; }},
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{{ arm_add_carry(resTemp, Rn, val2) }},
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{{ arm_add_overflow(resTemp, Rn, val2) }});
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0x6: sbc({{ uint32_t resTemp, val2 = op2;
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0x6: sbc({{ uint32_t val2 = op2;
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Rd = resTemp = Rn - val2 - !Cpsr<29:>; }},
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{{ arm_sub_carry(resTemp, Rn, val2) }},
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{{ arm_sub_overflow(resTemp, Rn, val2) }});
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0x7: rsc({{ uint32_t resTemp, val2 = op2;
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0x7: rsc({{ uint32_t val2 = op2;
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Rd = resTemp = val2 - Rn - !Cpsr<29:>; }},
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{{ arm_sub_carry(resTemp, val2, Rn) }},
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{{ arm_sub_overflow(resTemp, val2, Rn) }});
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0x8: tst({{ uint32_t resTemp = Rn & op2; }},
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0x8: tst({{ resTemp = Rn & op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0x9: teq({{ uint32_t resTemp = Rn ^ op2; }},
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0x9: teq({{ resTemp = Rn ^ op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xa: cmp({{ uint32_t resTemp, val2 = op2;
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0xa: cmp({{ uint32_t val2 = op2;
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resTemp = Rn - val2; }},
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{{ arm_sub_carry(resTemp, Rn, val2) }},
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{{ arm_sub_overflow(resTemp, Rn, val2) }});
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0xb: cmn({{ uint32_t resTemp, val2 = op2;
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0xb: cmn({{ uint32_t val2 = op2;
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resTemp = Rn + val2; }},
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{{ arm_add_carry(resTemp, Rn, val2) }},
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{{ arm_add_overflow(resTemp, Rn, val2) }});
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0xc: orr({{ uint32_t resTemp, val2 = op2;
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0xc: orr({{ uint32_t val2 = op2;
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Rd = resTemp = Rn | val2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xd: mov({{ uint32_t resTemp;
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Rd = resTemp = op2; }},
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0xd: mov({{ Rd = resTemp = op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xe: bic({{ uint32_t resTemp;
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Rd = resTemp = Rn & ~op2; }},
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0xe: bic({{ Rd = resTemp = Rn & ~op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xf: mvn({{ uint32_t resTemp;
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Rd = resTemp = ~op2; }},
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0xf: mvn({{ Rd = resTemp = ~op2; }},
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{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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}
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@ -360,68 +350,52 @@ format DataOp {
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0x1: decode IS_MISC {
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0: decode OPCODE {
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format DataImmOp {
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0x0: andi({{ uint32_t resTemp;
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Rd = resTemp = Rn & rotated_imm; }},
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0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0x1: eori({{ uint32_t resTemp;
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Rd = resTemp = Rn ^ rotated_imm; }},
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0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0x2: subi({{ uint32_t resTemp;
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Rd = resTemp = Rn - rotated_imm; }},
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0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }},
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{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
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0x3: rsbi({{ uint32_t resTemp;
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Rd = resTemp = rotated_imm - Rn; }},
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0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }},
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{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
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{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
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0x4: addi({{ uint32_t resTemp;
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Rd = resTemp = Rn + rotated_imm; }},
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0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }},
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{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
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0x5: adci({{ uint32_t resTemp;
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Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }},
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0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }},
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{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
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0x6: sbci({{ uint32_t resTemp;
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Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }},
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0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }},
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{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
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0x7: rsci({{ uint32_t resTemp;
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Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}},
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0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}},
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{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
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{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
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0x8: tsti({{ uint32_t resTemp;
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resTemp = Rn & rotated_imm; }},
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0x8: tsti({{ resTemp = Rn & rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0x9: teqi({{ uint32_t resTemp;
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resTemp = Rn ^ rotated_imm; }},
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0x9: teqi({{ resTemp = Rn ^ rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xa: cmpi({{ uint32_t resTemp;
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resTemp = Rn - rotated_imm; }},
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0xa: cmpi({{ resTemp = Rn - rotated_imm; }},
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{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
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0xb: cmni({{ uint32_t resTemp;
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resTemp = Rn + rotated_imm; }},
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0xb: cmni({{ resTemp = Rn + rotated_imm; }},
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{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
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0xc: orri({{ uint32_t resTemp;
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Rd = resTemp = Rn | rotated_imm; }},
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0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xd: movi({{ uint32_t resTemp;
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Rd = resTemp = rotated_imm; }},
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0xd: movi({{ Rd = resTemp = rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xe: bici({{ uint32_t resTemp;
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Rd = resTemp = Rn & ~rotated_imm; }},
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0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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0xf: mvni({{ uint32_t resTemp;
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Rd = resTemp = ~rotated_imm; }},
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0xf: mvni({{ Rd = resTemp = ~rotated_imm; }},
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{{ (rotate ? rotated_carry:Cpsr<29:>) }},
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{{ Cpsr<28:> }});
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}
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@ -41,6 +41,8 @@ def template PredOpExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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uint64_t resTemp = 0;
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resTemp = resTemp;
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%(op_decl)s;
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%(op_rd)s;
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@ -100,7 +102,6 @@ let {{
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}};
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def format DataOp(code, icValue, ivValue) {{
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code += "resTemp = resTemp;"
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regCode = re.sub(r'op2', 'shift_rm_rs(Rm, Rs, \
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shift, Cpsr<29:0>)', code)
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immCode = re.sub(r'op2', 'shift_rm_imm(Rm, shift_size, \
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