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added some comments to palcode and zeroed system type in HWPRB (m5 will fill in)

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console/console.c:
    0 the system type, let m5 overwrite
palcode/platform_m5.s:
    add some comments and make the timer interrupt actually care what CPU it happened on
This commit is contained in:
Ali Saidi 2004-05-11 17:31:28 -04:00
parent 8283dbcf3a
commit ce9b1a1e37
2 changed files with 16 additions and 10 deletions
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2
system/alpha/console/console.c
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@ -205,7 +205,7 @@ struct rpb xxm_rpb = {
#if 0 #if 0
0x12, /* 050: system type - masquarade as some random 21064 */ 0x12, /* 050: system type - masquarade as some random 21064 */
#endif #endif
34, /* masquerade a Tsunami RGD */ 0, /* masquerade a Tsunami RGD */
(1<<10), /* 058: system variation */ (1<<10), /* 058: system variation */
'c'|('o'<<8)|('o'<<16)|('l'<< 24), /* 060: system revision */ 'c'|('o'<<8)|('o'<<16)|('l'<< 24), /* 060: system revision */
1024*4096, /* 068: scaled interval clock intr freq OVERRIDEN*/ 1024*4096, /* 068: scaled interval clock intr freq OVERRIDEN*/

24
system/alpha/palcode/platform_m5.s
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@ -694,13 +694,15 @@ EXPORT(sys_interrupt)
cmpeq r13, 23, r12 cmpeq r13, 23, r12
bne r12, sys_int_23 // Check for level 23 interrupt bne r12, sys_int_23 // Check for level 23 interrupt
// IPI in Tsunami
cmpeq r13, 22, r12 cmpeq r13, 22, r12
bne r12, sys_int_22 // Check for level 22 interrupt (might be bne r12, sys_int_22 // Check for level 22 interrupt
// interprocessor or timer interrupt) // timer interrupt
cmpeq r13, 21, r12 cmpeq r13, 21, r12
bne r12, sys_int_21 // Check for level 21 interrupt bne r12, sys_int_21 // Check for level 21 interrupt
// I/O
cmpeq r13, 20, r12 cmpeq r13, 20, r12
bne r12, sys_int_20 // Check for level 20 interrupt (might be corrected bne r12, sys_int_20 // Check for level 20 interrupt (might be corrected
@ -753,16 +755,20 @@ sys_int_23:
ALIGN_BRANCH ALIGN_BRANCH
sys_int_22: sys_int_22:
or r31,1,r16 // a0 means it is a I/O interrupt or r31,1,r16 // a0 means it is a clock interrupt
lda r8,0xf01(r31) lda r8,0xf01(r31) // build up an address for the MISC register
sll r8,16,r8 sll r8,16,r8
lda r8,0xa000(r8) lda r8,0xa000(r8)
sll r8,16,r8 sll r8,16,r8
lda r8,0x080(r8) lda r8,0x080(r8)
or r31,0x10,r9
ldq_p r10,0(r8) // read misc register
and r10,0x3,r10 // isolate CPUID
or r31,0x10,r9 // load r9 with bit to clear
sll r9,r10,r9 // left shift by CPU ID
stq_p r9, 0(r8) // clear the rtc interrupt stq_p r9, 0(r8) // clear the rtc interrupt
br r31, pal_post_interrupt // br r31, pal_post_interrupt // Tell the OS
ALIGN_BRANCH ALIGN_BRANCH