Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
This commit is contained in:
commit
ce4531c079
|
@ -206,6 +206,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
*/
|
*/
|
||||||
Result instResult;
|
Result instResult;
|
||||||
|
|
||||||
|
/** Records changes to result? */
|
||||||
|
bool recordResult;
|
||||||
|
|
||||||
/** PC of this instruction. */
|
/** PC of this instruction. */
|
||||||
Addr PC;
|
Addr PC;
|
||||||
|
|
||||||
|
@ -263,6 +266,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Dumps out contents of this BaseDynInst into given string. */
|
/** Dumps out contents of this BaseDynInst into given string. */
|
||||||
void dump(std::string &outstring);
|
void dump(std::string &outstring);
|
||||||
|
|
||||||
|
/** Read this CPU's ID. */
|
||||||
|
int readCpuId() { return cpu->readCpuId(); }
|
||||||
|
|
||||||
/** Returns the fault type. */
|
/** Returns the fault type. */
|
||||||
Fault getFault() { return fault; }
|
Fault getFault() { return fault; }
|
||||||
|
|
||||||
|
@ -402,37 +408,42 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
/** Records an integer register being set to a value. */
|
/** Records an integer register being set to a value. */
|
||||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||||
{
|
{
|
||||||
instResult.integer = val;
|
if (recordResult)
|
||||||
|
instResult.integer = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Records an fp register being set to a value. */
|
/** Records an fp register being set to a value. */
|
||||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||||
{
|
{
|
||||||
if (width == 32)
|
if (recordResult) {
|
||||||
instResult.dbl = (double)val;
|
if (width == 32)
|
||||||
else if (width == 64)
|
instResult.dbl = (double)val;
|
||||||
instResult.dbl = val;
|
else if (width == 64)
|
||||||
else
|
instResult.dbl = val;
|
||||||
panic("Unsupported width!");
|
else
|
||||||
|
panic("Unsupported width!");
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Records an fp register being set to a value. */
|
/** Records an fp register being set to a value. */
|
||||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||||
{
|
{
|
||||||
// instResult.fp = val;
|
if (recordResult)
|
||||||
instResult.dbl = (double)val;
|
instResult.dbl = (double)val;
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Records an fp register being set to an integer value. */
|
/** Records an fp register being set to an integer value. */
|
||||||
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
|
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
|
||||||
{
|
{
|
||||||
instResult.integer = val;
|
if (recordResult)
|
||||||
|
instResult.integer = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Records an fp register being set to an integer value. */
|
/** Records an fp register being set to an integer value. */
|
||||||
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
|
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
|
||||||
{
|
{
|
||||||
instResult.integer = val;
|
if (recordResult)
|
||||||
|
instResult.integer = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Records that one of the source registers is ready. */
|
/** Records that one of the source registers is ready. */
|
||||||
|
@ -624,6 +635,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
||||||
|
|
||||||
/** Sets iterator for this instruction in the list of all insts. */
|
/** Sets iterator for this instruction in the list of all insts. */
|
||||||
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
|
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Returns the number of consecutive store conditional failures. */
|
||||||
|
unsigned readStCondFailures()
|
||||||
|
{ return thread->storeCondFailures; }
|
||||||
|
|
||||||
|
/** Sets the number of consecutive store conditional failures. */
|
||||||
|
void setStCondFailures(unsigned sc_failures)
|
||||||
|
{ thread->storeCondFailures = sc_failures; }
|
||||||
};
|
};
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
|
|
|
@ -97,6 +97,7 @@ BaseDynInst<Impl>::initVars()
|
||||||
readyRegs = 0;
|
readyRegs = 0;
|
||||||
|
|
||||||
instResult.integer = 0;
|
instResult.integer = 0;
|
||||||
|
recordResult = true;
|
||||||
|
|
||||||
status.reset();
|
status.reset();
|
||||||
|
|
||||||
|
|
|
@ -260,7 +260,7 @@ Fault
|
||||||
AlphaO3CPU<Impl>::hwrei(unsigned tid)
|
AlphaO3CPU<Impl>::hwrei(unsigned tid)
|
||||||
{
|
{
|
||||||
// Need to clear the lock flag upon returning from an interrupt.
|
// Need to clear the lock flag upon returning from an interrupt.
|
||||||
this->lockFlag = false;
|
this->setMiscReg(TheISA::Lock_Flag_DepTag, false, tid);
|
||||||
|
|
||||||
this->thread[tid]->kernelStats->hwrei();
|
this->thread[tid]->kernelStats->hwrei();
|
||||||
|
|
||||||
|
|
|
@ -63,7 +63,7 @@ template<class Impl>
|
||||||
void
|
void
|
||||||
DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
|
DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
|
||||||
{
|
{
|
||||||
warn("Default fetch doesn't update it's state from a functional call.");
|
warn("DefaultFetch doesn't update its state from a functional call.");
|
||||||
}
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
|
@ -1276,11 +1276,12 @@ DefaultFetch<Impl>::fetch(bool &status_change)
|
||||||
|
|
||||||
fetchStatus[tid] = TrapPending;
|
fetchStatus[tid] = TrapPending;
|
||||||
status_change = true;
|
status_change = true;
|
||||||
|
|
||||||
// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
|
|
||||||
#else // !FULL_SYSTEM
|
#else // !FULL_SYSTEM
|
||||||
warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
|
fetchStatus[tid] = TrapPending;
|
||||||
|
status_change = true;
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
DPRINTF(Fetch, "[tid:%i]: fault (%d) detected @ PC %08p", tid, fault, PC[tid]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -37,6 +37,7 @@
|
||||||
#include <queue>
|
#include <queue>
|
||||||
|
|
||||||
#include "arch/faults.hh"
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/locked_mem.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
#include "base/hashmap.hh"
|
#include "base/hashmap.hh"
|
||||||
#include "cpu/inst_seq.hh"
|
#include "cpu/inst_seq.hh"
|
||||||
|
@ -510,8 +511,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
if (req->isLocked()) {
|
if (req->isLocked()) {
|
||||||
cpu->lockAddr = req->getPaddr();
|
// Disable recording the result temporarily. Writing to misc
|
||||||
cpu->lockFlag = true;
|
// regs normally updates the result, but this is not the
|
||||||
|
// desired behavior when handling store conditionals.
|
||||||
|
load_inst->recordResult = false;
|
||||||
|
TheISA::handleLockedRead(load_inst.get(), req);
|
||||||
|
load_inst->recordResult = true;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
@ -29,6 +29,7 @@
|
||||||
* Korey Sewell
|
* Korey Sewell
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "arch/locked_mem.hh"
|
||||||
#include "config/use_checker.hh"
|
#include "config/use_checker.hh"
|
||||||
|
|
||||||
#include "cpu/o3/lsq.hh"
|
#include "cpu/o3/lsq.hh"
|
||||||
|
@ -614,27 +615,24 @@ LSQUnit<Impl>::writebackStores()
|
||||||
|
|
||||||
// @todo: Remove this SC hack once the memory system handles it.
|
// @todo: Remove this SC hack once the memory system handles it.
|
||||||
if (req->isLocked()) {
|
if (req->isLocked()) {
|
||||||
if (req->isUncacheable()) {
|
// Disable recording the result temporarily. Writing to
|
||||||
req->setScResult(2);
|
// misc regs normally updates the result, but this is not
|
||||||
} else {
|
// the desired behavior when handling store conditionals.
|
||||||
if (cpu->lockFlag) {
|
inst->recordResult = false;
|
||||||
req->setScResult(1);
|
bool success = TheISA::handleLockedWrite(inst.get(), req);
|
||||||
DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
|
inst->recordResult = true;
|
||||||
inst->seqNum);
|
|
||||||
} else {
|
if (!success) {
|
||||||
req->setScResult(0);
|
// Instantly complete this store.
|
||||||
// Hack: Instantly complete this store.
|
DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
|
||||||
// completeDataAccess(data_pkt);
|
"Instantly completing it.\n",
|
||||||
DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
|
inst->seqNum);
|
||||||
"Instantly completing it.\n",
|
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
|
||||||
inst->seqNum);
|
wb->schedule(curTick + 1);
|
||||||
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
|
delete state;
|
||||||
wb->schedule(curTick + 1);
|
completeStore(storeWBIdx);
|
||||||
delete state;
|
incrStIdx(storeWBIdx);
|
||||||
completeStore(storeWBIdx);
|
continue;
|
||||||
incrStIdx(storeWBIdx);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
// Non-store conditionals do not need a writeback.
|
// Non-store conditionals do not need a writeback.
|
||||||
|
|
Loading…
Reference in a new issue