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mem: Use pkt::getBlockAddr instead of BaseCace::blockAlign

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Change-Id: I0ed4e528cb750a323facdc811dde7f0ed1ff228e
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
This commit is contained in:
Nikos Nikoleris 2016-10-26 11:07:27 +01:00 committed by Andreas Sandberg
parent ceb3bd9733
commit ce2a0076c9
2 changed files with 8 additions and 12 deletions
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8
src/mem/cache/base.hh vendored
View file

@ -484,15 +484,11 @@ class BaseCache : public MemObject
return blkSize;
}
Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
const AddrRangeList &getAddrRanges() const { return addrRanges; }
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
{
MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize,
MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
pkt, time, order++,
allocOnFill(pkt->cmd));
@ -513,7 +509,7 @@ class BaseCache : public MemObject
// should only see writes or clean evicts here
assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
Addr blk_addr = blockAlign(pkt->getAddr());
Addr blk_addr = pkt->getBlockAddr(blkSize);
WriteQueueEntry *wq_entry =
writeBuffer.findMatch(blk_addr, pkt->isSecure());

12
src/mem/cache/cache.cc vendored
View file

@ -737,7 +737,7 @@ Cache::recvTimingReq(PacketPtr pkt)
} else {
// miss
Addr blk_addr = blockAlign(pkt->getAddr());
Addr blk_addr = pkt->getBlockAddr(blkSize);
// ignore any existing MSHR if we are dealing with an
// uncacheable request
@ -961,7 +961,7 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
}
// the packet should be block aligned
assert(pkt->getAddr() == blockAlign(pkt->getAddr()));
assert(pkt->getAddr() == pkt->getBlockAddr(blkSize));
pkt->allocate();
DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(),
@ -1149,7 +1149,7 @@ Cache::functionalAccess(PacketPtr pkt, bool fromCpuSide)
return;
}
Addr blk_addr = blockAlign(pkt->getAddr());
Addr blk_addr = pkt->getBlockAddr(blkSize);
bool is_secure = pkt->isSecure();
CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
@ -1731,7 +1731,7 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
#endif
// When handling a fill, we should have no writes to this line.
assert(addr == blockAlign(addr));
assert(addr == pkt->getBlockAddr(blkSize));
assert(!writeBuffer.findMatch(addr, is_secure));
if (blk == nullptr) {
@ -2092,7 +2092,7 @@ Cache::recvTimingSnoopReq(PacketPtr pkt)
bool is_secure = pkt->isSecure();
CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
Addr blk_addr = blockAlign(pkt->getAddr());
Addr blk_addr = pkt->getBlockAddr(blkSize);
MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
// Update the latency cost of the snoop so that the crossbar can
@ -2281,7 +2281,7 @@ Cache::getNextQueueEntry()
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
Addr pf_addr = blockAlign(pkt->getAddr());
Addr pf_addr = pkt->getBlockAddr(blkSize);
if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
!mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
!writeBuffer.findMatch(pf_addr, pkt->isSecure())) {