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SPARC: Clean up some historical style issues.

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This commit is contained in:
Gabe Black 2010-11-11 02:03:58 -08:00
parent 0b7967d606
commit cdc585e0e8
51 changed files with 2213 additions and 2189 deletions
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365
src/arch/sparc/asi.cc
View file

@ -33,160 +33,161 @@
namespace SparcISA namespace SparcISA
{ {
bool AsiIsBlock(ASI asi)
bool
asiIsBlock(ASI asi)
{ {
return return asi == ASI_BLK_AIUP ||
(asi == ASI_BLK_AIUP) || asi == ASI_BLK_AIUS ||
(asi == ASI_BLK_AIUS) || asi == ASI_BLK_AIUP_L ||
(asi == ASI_BLK_AIUP_L) || asi == ASI_BLK_AIUS_L ||
(asi == ASI_BLK_AIUS_L) || asi == ASI_BLK_P ||
(asi == ASI_BLK_P) || asi == ASI_BLK_S ||
(asi == ASI_BLK_S) || asi == ASI_BLK_PL ||
(asi == ASI_BLK_PL) || asi == ASI_BLK_SL;
(asi == ASI_BLK_SL);
} }
bool AsiIsPrimary(ASI asi) bool
asiIsPrimary(ASI asi)
{ {
return return asi == ASI_AIUP ||
(asi == ASI_AIUP) || asi == ASI_BLK_AIUP ||
(asi == ASI_BLK_AIUP) || asi == ASI_AIUP_L ||
(asi == ASI_AIUP_L) || asi == ASI_BLK_AIUP_L ||
(asi == ASI_BLK_AIUP_L) || asi == ASI_LDTX_AIUP ||
(asi == ASI_LDTX_AIUP) || asi == ASI_LDTX_AIUP_L ||
(asi == ASI_LDTX_AIUP_L) || asi == ASI_P ||
(asi == ASI_P) || asi == ASI_PNF ||
(asi == ASI_PNF) || asi == ASI_PL ||
(asi == ASI_PL) || asi == ASI_PNFL ||
(asi == ASI_PNFL) || asi == ASI_PST8_P ||
(asi == ASI_PST8_P) || asi == ASI_PST16_P ||
(asi == ASI_PST16_P) || asi == ASI_PST32_P ||
(asi == ASI_PST32_P) || asi == ASI_PST8_PL ||
(asi == ASI_PST8_PL) || asi == ASI_PST16_PL ||
(asi == ASI_PST16_PL) || asi == ASI_PST32_PL ||
(asi == ASI_PST32_PL) || asi == ASI_FL8_P ||
(asi == ASI_FL8_P) || asi == ASI_FL16_P ||
(asi == ASI_FL16_P) || asi == ASI_FL8_PL ||
(asi == ASI_FL8_PL) || asi == ASI_FL16_PL ||
(asi == ASI_FL16_PL) || asi == ASI_LDTX_P ||
(asi == ASI_LDTX_P) || asi == ASI_LDTX_PL ||
(asi == ASI_LDTX_PL) || asi == ASI_BLK_P ||
(asi == ASI_BLK_P) || asi == ASI_BLK_PL;
(asi == ASI_BLK_PL);
} }
bool AsiIsSecondary(ASI asi) bool
asiIsSecondary(ASI asi)
{ {
return return asi == ASI_AIUS ||
(asi == ASI_AIUS) || asi == ASI_BLK_AIUS ||
(asi == ASI_BLK_AIUS) || asi == ASI_AIUS_L ||
(asi == ASI_AIUS_L) || asi == ASI_BLK_AIUS_L ||
(asi == ASI_BLK_AIUS_L) || asi == ASI_LDTX_AIUS ||
(asi == ASI_LDTX_AIUS) || asi == ASI_LDTX_AIUS_L ||
(asi == ASI_LDTX_AIUS_L) || asi == ASI_S ||
(asi == ASI_S) || asi == ASI_SNF ||
(asi == ASI_SNF) || asi == ASI_SL ||
(asi == ASI_SL) || asi == ASI_SNFL ||
(asi == ASI_SNFL) || asi == ASI_PST8_S ||
(asi == ASI_PST8_S) || asi == ASI_PST16_S ||
(asi == ASI_PST16_S) || asi == ASI_PST32_S ||
(asi == ASI_PST32_S) || asi == ASI_PST8_SL ||
(asi == ASI_PST8_SL) || asi == ASI_PST16_SL ||
(asi == ASI_PST16_SL) || asi == ASI_PST32_SL ||
(asi == ASI_PST32_SL) || asi == ASI_FL8_S ||
(asi == ASI_FL8_S) || asi == ASI_FL16_S ||
(asi == ASI_FL16_S) || asi == ASI_FL8_SL ||
(asi == ASI_FL8_SL) || asi == ASI_FL16_SL ||
(asi == ASI_FL16_SL) || asi == ASI_LDTX_S ||
(asi == ASI_LDTX_S) || asi == ASI_LDTX_SL ||
(asi == ASI_LDTX_SL) || asi == ASI_BLK_S ||
(asi == ASI_BLK_S) || asi == ASI_BLK_SL;
(asi == ASI_BLK_SL);
} }
bool AsiIsNucleus(ASI asi) bool
asiIsNucleus(ASI asi)
{ {
return return asi == ASI_N ||
(asi == ASI_N) || asi == ASI_NL ||
(asi == ASI_NL) || asi == ASI_LDTX_N ||
(asi == ASI_LDTX_N) || asi == ASI_LDTX_NL;
(asi == ASI_LDTX_NL);
} }
bool AsiIsAsIfUser(ASI asi) bool
asiIsAsIfUser(ASI asi)
{ {
return return asi == ASI_AIUP ||
(asi == ASI_AIUP) || asi == ASI_AIUS ||
(asi == ASI_AIUS) || asi == ASI_BLK_AIUP ||
(asi == ASI_BLK_AIUP) || asi == ASI_BLK_AIUS ||
(asi == ASI_BLK_AIUS) || asi == ASI_AIUP_L ||
(asi == ASI_AIUP_L) || asi == ASI_AIUS_L ||
(asi == ASI_AIUS_L) || asi == ASI_BLK_AIUP_L ||
(asi == ASI_BLK_AIUP_L) || asi == ASI_BLK_AIUS_L ||
(asi == ASI_BLK_AIUS_L) || asi == ASI_LDTX_AIUP ||
(asi == ASI_LDTX_AIUP) || asi == ASI_LDTX_AIUS ||
(asi == ASI_LDTX_AIUS) || asi == ASI_LDTX_AIUP_L ||
(asi == ASI_LDTX_AIUP_L) || asi == ASI_LDTX_AIUS_L;
(asi == ASI_LDTX_AIUS_L);
} }
bool AsiIsIO(ASI asi) bool
asiIsIO(ASI asi)
{ {
return return asi == ASI_REAL_IO ||
(asi == ASI_REAL_IO) || asi == ASI_REAL_IO_L;
(asi == ASI_REAL_IO_L);
} }
bool AsiIsReal(ASI asi) bool
asiIsReal(ASI asi)
{ {
return return asi == ASI_REAL ||
(asi == ASI_REAL) || asi == ASI_REAL_IO ||
(asi == ASI_REAL_IO) || asi == ASI_REAL_L ||
(asi == ASI_REAL_L) || asi == ASI_REAL_IO_L ||
(asi == ASI_REAL_IO_L) || asi == ASI_LDTX_REAL ||
(asi == ASI_LDTX_REAL) || asi == ASI_LDTX_REAL_L;
(asi == ASI_LDTX_REAL_L);
} }
bool AsiIsLittle(ASI asi) bool
asiIsLittle(ASI asi)
{ {
return return asi == ASI_NL ||
(asi == ASI_NL) || asi == ASI_AIUP_L ||
(asi == ASI_AIUP_L) || asi == ASI_AIUS_L ||
(asi == ASI_AIUS_L) || asi == ASI_REAL_L ||
(asi == ASI_REAL_L) || asi == ASI_REAL_IO_L ||
(asi == ASI_REAL_IO_L) || asi == ASI_BLK_AIUP_L ||
(asi == ASI_BLK_AIUP_L) || asi == ASI_BLK_AIUS_L ||
(asi == ASI_BLK_AIUS_L) || asi == ASI_LDTX_AIUP_L ||
(asi == ASI_LDTX_AIUP_L) || asi == ASI_LDTX_AIUS_L ||
(asi == ASI_LDTX_AIUS_L) || asi == ASI_LDTX_REAL_L ||
(asi == ASI_LDTX_REAL_L) || asi == ASI_LDTX_NL ||
(asi == ASI_LDTX_NL) || asi == ASI_PL ||
(asi == ASI_PL) || asi == ASI_SL ||
(asi == ASI_SL) || asi == ASI_PNFL ||
(asi == ASI_PNFL) || asi == ASI_SNFL ||
(asi == ASI_SNFL) || asi == ASI_PST8_PL ||
(asi == ASI_PST8_PL) || asi == ASI_PST8_SL ||
(asi == ASI_PST8_SL) || asi == ASI_PST16_PL ||
(asi == ASI_PST16_PL) || asi == ASI_PST16_SL ||
(asi == ASI_PST16_SL) || asi == ASI_PST32_PL ||
(asi == ASI_PST32_PL) || asi == ASI_PST32_SL ||
(asi == ASI_PST32_SL) || asi == ASI_FL8_PL ||
(asi == ASI_FL8_PL) || asi == ASI_FL8_SL ||
(asi == ASI_FL8_SL) || asi == ASI_FL16_PL ||
(asi == ASI_FL16_PL) || asi == ASI_FL16_SL ||
(asi == ASI_FL16_SL) || asi == ASI_LDTX_PL ||
(asi == ASI_LDTX_PL) || asi == ASI_LDTX_SL ||
(asi == ASI_LDTX_SL) || asi == ASI_BLK_PL ||
(asi == ASI_BLK_PL) || asi == ASI_BLK_SL ||
(asi == ASI_BLK_SL) || asi == ASI_LTX_L;
(asi == ASI_LTX_L);
} }
bool AsiIsTwin(ASI asi) bool
asiIsTwin(ASI asi)
{ {
return return (asi >= ASI_LDTX_AIUP &&
(asi >= ASI_LDTX_AIUP &&
asi <= ASI_LDTX_N && asi <= ASI_LDTX_N &&
asi != ASI_QUEUE) || asi != ASI_QUEUE) ||
(asi >= ASI_LDTX_AIUP_L && (asi >= ASI_LDTX_AIUP_L &&
@ -198,72 +199,75 @@ namespace SparcISA
asi == ASI_LDTX_SL; asi == ASI_LDTX_SL;
} }
bool AsiIsPartialStore(ASI asi) bool
asiIsPartialStore(ASI asi)
{ {
return return asi == ASI_PST8_P ||
(asi == ASI_PST8_P) || asi == ASI_PST8_S ||
(asi == ASI_PST8_S) || asi == ASI_PST16_P ||
(asi == ASI_PST16_P) || asi == ASI_PST16_S ||
(asi == ASI_PST16_S) || asi == ASI_PST32_P ||
(asi == ASI_PST32_P) || asi == ASI_PST32_S ||
(asi == ASI_PST32_S) || asi == ASI_PST8_PL ||
(asi == ASI_PST8_PL) || asi == ASI_PST8_SL ||
(asi == ASI_PST8_SL) || asi == ASI_PST16_PL ||
(asi == ASI_PST16_PL) || asi == ASI_PST16_SL ||
(asi == ASI_PST16_SL) || asi == ASI_PST32_PL ||
(asi == ASI_PST32_PL) || asi == ASI_PST32_SL;
(asi == ASI_PST32_SL);
} }
bool AsiIsFloatingLoad(ASI asi) bool
asiIsFloatingLoad(ASI asi)
{ {
return return asi == ASI_FL8_P ||
(asi == ASI_FL8_P) || asi == ASI_FL8_S ||
(asi == ASI_FL8_S) || asi == ASI_FL16_P ||
(asi == ASI_FL16_P) || asi == ASI_FL16_S ||
(asi == ASI_FL16_S) || asi == ASI_FL8_PL ||
(asi == ASI_FL8_PL) || asi == ASI_FL8_SL ||
(asi == ASI_FL8_SL) || asi == ASI_FL16_PL ||
(asi == ASI_FL16_PL) || asi == ASI_FL16_SL;
(asi == ASI_FL16_SL);
} }
bool AsiIsNoFault(ASI asi) bool
asiIsNoFault(ASI asi)
{ {
return return asi == ASI_PNF ||
(asi == ASI_PNF) || asi == ASI_SNF ||
(asi == ASI_SNF) || asi == ASI_PNFL ||
(asi == ASI_PNFL) || asi == ASI_SNFL;
(asi == ASI_SNFL);
} }
bool AsiIsScratchPad(ASI asi) bool
asiIsScratchPad(ASI asi)
{ {
return return asi == ASI_SCRATCHPAD ||
(asi == ASI_SCRATCHPAD) || asi == ASI_HYP_SCRATCHPAD;
(asi == ASI_HYP_SCRATCHPAD);
} }
bool AsiIsCmt(ASI asi) bool
asiIsCmt(ASI asi)
{ {
return return asi == ASI_CMT_PER_STRAND ||
(asi == ASI_CMT_PER_STRAND) || asi == ASI_CMT_SHARED;
(asi == ASI_CMT_SHARED);
} }
bool AsiIsQueue(ASI asi) bool
asiIsQueue(ASI asi)
{ {
return asi == ASI_QUEUE; return asi == ASI_QUEUE;
} }
bool AsiIsInterrupt(ASI asi) bool
asiIsInterrupt(ASI asi)
{ {
return asi == ASI_SWVR_INTR_RECEIVE || return asi == ASI_SWVR_INTR_RECEIVE ||
asi == ASI_SWVR_UDB_INTR_W || asi == ASI_SWVR_UDB_INTR_W ||
asi == ASI_SWVR_UDB_INTR_R ; asi == ASI_SWVR_UDB_INTR_R ;
} }
bool AsiIsMmu(ASI asi) bool
asiIsMmu(ASI asi)
{ {
return asi == ASI_MMU || return asi == ASI_MMU ||
asi == ASI_LSU_CONTROL_REG || asi == ASI_LSU_CONTROL_REG ||
@ -277,30 +281,35 @@ namespace SparcISA
asi <= ASI_TLB_INVALIDATE_ALL); asi <= ASI_TLB_INVALIDATE_ALL);
} }
bool AsiIsUnPriv(ASI asi) bool
asiIsUnPriv(ASI asi)
{ {
return asi >= 0x80; return asi >= 0x80;
} }
bool AsiIsPriv(ASI asi) bool
asiIsPriv(ASI asi)
{ {
return asi <= 0x2f; return asi <= 0x2f;
} }
bool AsiIsHPriv(ASI asi) bool
asiIsHPriv(ASI asi)
{ {
return asi >= 0x30 && asi <= 0x7f; return asi >= 0x30 && asi <= 0x7f;
} }
bool AsiIsReg(ASI asi) bool
asiIsReg(ASI asi)
{ {
return AsiIsMmu(asi) || AsiIsScratchPad(asi) || return asiIsMmu(asi) || asiIsScratchPad(asi) ||
AsiIsSparcError(asi) || AsiIsInterrupt(asi) asiIsSparcError(asi) || asiIsInterrupt(asi)
|| AsiIsCmt(asi); || asiIsCmt(asi);
} }
bool AsiIsSparcError(ASI asi) bool
asiIsSparcError(ASI asi)
{ {
return asi == ASI_SPARC_ERROR_EN_REG || return asi == ASI_SPARC_ERROR_EN_REG ||
asi == ASI_SPARC_ERROR_STATUS_REG; asi == ASI_SPARC_ERROR_STATUS_REG;

47
src/arch/sparc/asi.hh
View file

@ -34,6 +34,7 @@
namespace SparcISA namespace SparcISA
{ {
enum ASI { enum ASI {
ASI_IMPLICIT = 0x00, ASI_IMPLICIT = 0x00,
/* Priveleged ASIs */ /* Priveleged ASIs */
@ -248,29 +249,29 @@ namespace SparcISA
}; };
// Functions that classify an asi // Functions that classify an asi
bool AsiIsBlock(ASI); bool asiIsBlock(ASI);
bool AsiIsPrimary(ASI); bool asiIsPrimary(ASI);
bool AsiIsSecondary(ASI); bool asiIsSecondary(ASI);
bool AsiIsNucleus(ASI); bool asiIsNucleus(ASI);
bool AsiIsAsIfUser(ASI); bool asiIsAsIfUser(ASI);
bool AsiIsIO(ASI); bool asiIsIO(ASI);
bool AsiIsReal(ASI); bool asiIsReal(ASI);
bool AsiIsLittle(ASI); bool asiIsLittle(ASI);
bool AsiIsTwin(ASI); bool asiIsTwin(ASI);
bool AsiIsPartialStore(ASI); bool asiIsPartialStore(ASI);
bool AsiIsFloatingLoad(ASI); bool asiIsFloatingLoad(ASI);
bool AsiIsNoFault(ASI); bool asiIsNoFault(ASI);
bool AsiIsScratchPad(ASI); bool asiIsScratchPad(ASI);
bool AsiIsCmt(ASI); bool asiIsCmt(ASI);
bool AsiIsQueue(ASI); bool asiIsQueue(ASI);
bool AsiIsDtlb(ASI); bool asiIsDtlb(ASI);
bool AsiIsMmu(ASI); bool asiIsMmu(ASI);
bool AsiIsUnPriv(ASI); bool asiIsUnPriv(ASI);
bool AsiIsPriv(ASI); bool asiIsPriv(ASI);
bool AsiIsHPriv(ASI); bool asiIsHPriv(ASI);
bool AsiIsReg(ASI); bool asiIsReg(ASI);
bool AsiIsInterrupt(ASI); bool asiIsInterrupt(ASI);
bool AsiIsSparcError(ASI); bool asiIsSparcError(ASI);
}; };
#endif // __ARCH_SPARC_ASI_HH__ #endif // __ARCH_SPARC_ASI_HH__

54
src/arch/sparc/faults.cc
View file

@ -272,7 +272,8 @@ template<> SparcFaultBase::FaultVals
* effects which go with entering RED state because of a trap. * effects which go with entering RED state because of a trap.
*/ */
void enterREDState(ThreadContext *tc) void
enterREDState(ThreadContext *tc)
{ {
//@todo Disable the mmu? //@todo Disable the mmu?
//@todo Disable watchpoints? //@todo Disable watchpoints?
@ -294,17 +295,16 @@ void enterREDState(ThreadContext *tc)
* the handler. * the handler.
*/ */
void doREDFault(ThreadContext *tc, TrapType tt) void
doREDFault(ThreadContext *tc, TrapType tt)
{ {
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
//MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
//MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3); MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState(); PCState pc = tc->pcState();
@ -365,8 +365,7 @@ void doREDFault(ThreadContext *tc, TrapType tt)
else else
changedCWP = false; changedCWP = false;
if(changedCWP) if (changedCWP) {
{
CWP = (CWP + NWindows) % NWindows; CWP = (CWP + NWindows) % NWindows;
tc->setMiscReg(MISCREG_CWP, CWP); tc->setMiscReg(MISCREG_CWP, CWP);
} }
@ -377,17 +376,16 @@ void doREDFault(ThreadContext *tc, TrapType tt)
* the handler. * the handler.
*/ */
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) void
doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
{ {
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
//MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
//MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3); MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState(); PCState pc = tc->pcState();
@ -438,8 +436,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
// PSTATE.tle is unchanged // PSTATE.tle is unchanged
// PSTATE.tct = 0 // PSTATE.tct = 0
if (gotoHpriv) if (gotoHpriv) {
{
PSTATE &= ~(1 << 9); // PSTATE.cle = 0 PSTATE &= ~(1 << 9); // PSTATE.cle = 0
// The manual says PSTATE.priv should be 0, but Legion leaves it alone // The manual says PSTATE.priv should be 0, but Legion leaves it alone
HPSTATE &= ~(1 << 5); // HPSTATE.red = 0 HPSTATE &= ~(1 << 5); // HPSTATE.red = 0
@ -464,14 +461,14 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
else else
changedCWP = false; changedCWP = false;
if (changedCWP) if (changedCWP) {
{
CWP = (CWP + NWindows) % NWindows; CWP = (CWP + NWindows) % NWindows;
tc->setMiscReg(MISCREG_CWP, CWP); tc->setMiscReg(MISCREG_CWP, CWP);
} }
} }
void getREDVector(MiscReg TT, Addr &PC, Addr &NPC) void
getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
{ {
//XXX The following constant might belong in a header file. //XXX The following constant might belong in a header file.
const Addr RSTVAddr = 0xFFF0000000ULL; const Addr RSTVAddr = 0xFFF0000000ULL;
@ -479,14 +476,16 @@ void getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
NPC = PC + sizeof(MachInst); NPC = PC + sizeof(MachInst);
} }
void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) void
getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
{ {
Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA); Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
NPC = PC + sizeof(MachInst); NPC = PC + sizeof(MachInst);
} }
void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) void
getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
{ {
Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA); Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
PC = (TBA & ~mask(15)) | PC = (TBA & ~mask(15)) |
@ -497,9 +496,9 @@ void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscRe
#if FULL_SYSTEM #if FULL_SYSTEM
void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst) void
SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{ {
//panic("Invoking a second fault!\n");
FaultBase::invoke(tc); FaultBase::invoke(tc);
countStat()++; countStat()++;
@ -555,7 +554,8 @@ void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
tc->pcState(pc); tc->pcState(pc);
} }
void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst) void
PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
// For SPARC, when a system is first started, there is a power // For SPARC, when a system is first started, there is a power
// on reset Trap which sets the processor into the following state. // on reset Trap which sets the processor into the following state.
@ -621,8 +621,8 @@ void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
#else // !FULL_SYSTEM #else // !FULL_SYSTEM
void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, void
StaticInstPtr inst) FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
Process *p = tc->getProcessPtr(); Process *p = tc->getProcessPtr();
TlbEntry entry; TlbEntry entry;
@ -636,7 +636,8 @@ void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
} }
} }
void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) void
FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
Process *p = tc->getProcessPtr(); Process *p = tc->getProcessPtr();
TlbEntry entry; TlbEntry entry;
@ -654,7 +655,8 @@ void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
} }
} }
void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) void
SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
doNormalFault(tc, trapType(), false); doNormalFault(tc, trapType(), false);
@ -668,7 +670,8 @@ void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
tc->pcState(lp->readSpillStart()); tc->pcState(lp->readSpillStart());
} }
void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) void
FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
doNormalFault(tc, trapType(), false); doNormalFault(tc, trapType(), false);
@ -682,7 +685,8 @@ void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
tc->pcState(lp->readFillStart()); tc->pcState(lp->readFillStart());
} }
void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) void
TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
// In SE, this mechanism is how the process requests a service from the // In SE, this mechanism is how the process requests a service from the
// operating system. We'll get the process object from the thread context // operating system. We'll get the process object from the thread context

22
src/arch/sparc/faults.hh
View file

@ -86,7 +86,9 @@ class SparcFault : public SparcFaultBase
TrapType trapType() { return vals.trapType; } TrapType trapType() { return vals.trapType; }
FaultPriority priority() { return vals.priority; } FaultPriority priority() { return vals.priority; }
FaultStat & countStat() { return vals.count; } FaultStat & countStat() { return vals.count; }
PrivilegeLevel getNextLevel(PrivilegeLevel current)
PrivilegeLevel
getNextLevel(PrivilegeLevel current)
{ {
return vals.nextPrivilegeLevel[current]; return vals.nextPrivilegeLevel[current];
} }
@ -143,7 +145,8 @@ class InternalProcessorError :
bool isMachineCheckFault() const { return true; } bool isMachineCheckFault() const { return true; }
}; };
class InstructionInvalidTSBEntry : public SparcFault<InstructionInvalidTSBEntry> {}; class InstructionInvalidTSBEntry :
public SparcFault<InstructionInvalidTSBEntry> {};
class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {}; class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {};
@ -257,13 +260,15 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
class SpillNOther : public EnumeratedFault<SpillNOther> class SpillNOther : public EnumeratedFault<SpillNOther>
{ {
public: public:
SpillNOther(uint32_t n) : EnumeratedFault<SpillNOther>(n) {;} SpillNOther(uint32_t n) : EnumeratedFault<SpillNOther>(n)
{}
}; };
class FillNNormal : public EnumeratedFault<FillNNormal> class FillNNormal : public EnumeratedFault<FillNNormal>
{ {
public: public:
FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n) {;} FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
{}
// These need to be handled specially to enable fill traps in SE // These need to be handled specially to enable fill traps in SE
#if !FULL_SYSTEM #if !FULL_SYSTEM
void invoke(ThreadContext * tc, void invoke(ThreadContext * tc,
@ -274,13 +279,15 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
class FillNOther : public EnumeratedFault<FillNOther> class FillNOther : public EnumeratedFault<FillNOther>
{ {
public: public:
FillNOther(uint32_t n) : EnumeratedFault<FillNOther>(n) {;} FillNOther(uint32_t n) : EnumeratedFault<FillNOther>(n)
{}
}; };
class TrapInstruction : public EnumeratedFault<TrapInstruction> class TrapInstruction : public EnumeratedFault<TrapInstruction>
{ {
public: public:
TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) {;} TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
{}
// In SE, trap instructions are requesting services from the OS. // In SE, trap instructions are requesting services from the OS.
#if !FULL_SYSTEM #if !FULL_SYSTEM
void invoke(ThreadContext * tc, void invoke(ThreadContext * tc,
@ -288,7 +295,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
#endif #endif
}; };
static inline Fault genMachineCheckFault() static inline Fault
genMachineCheckFault()
{ {
return new InternalProcessorError; return new InternalProcessorError;
} }

4
src/arch/sparc/interrupts.hh
View file

@ -181,9 +181,7 @@ class Interrupts : public SimObject
void void
updateIntrInfo(ThreadContext *tc) updateIntrInfo(ThreadContext *tc)
{ {}
}
uint64_t uint64_t
get_vec(int int_num) get_vec(int int_num)

40
src/arch/sparc/isa/base.isa
View file

@ -119,7 +119,8 @@ output header {{
bool passesCondition(uint32_t codes, uint32_t condition); bool passesCondition(uint32_t codes, uint32_t condition);
inline int64_t sign_ext(uint64_t data, int origWidth) inline int64_t
sign_ext(uint64_t data, int origWidth)
{ {
int shiftAmount = 64 - origWidth; int shiftAmount = 64 - origWidth;
return (((int64_t)data) << shiftAmount) >> shiftAmount; return (((int64_t)data) << shiftAmount) >> shiftAmount;
@ -255,8 +256,7 @@ output decoder {{
if (num <= 0) if (num <= 0)
return; return;
printReg(os, indexArray[0]); printReg(os, indexArray[0]);
for(int x = 1; x < num; x++) for (int x = 1; x < num; x++) {
{
os << ", "; os << ", ";
printReg(os, indexArray[x]); printReg(os, indexArray[x]);
} }
@ -435,7 +435,8 @@ output decoder {{
} }
} }
std::string SparcStaticInst::generateDisassembly(Addr pc, std::string
SparcStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream ss; std::stringstream ss;
@ -446,19 +447,15 @@ output decoder {{
// a third one, it's a read-modify-write dest (Rc), // a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx // e.g. for CMOVxx
if (_numSrcRegs > 0) if (_numSrcRegs > 0)
{
printReg(ss, _srcRegIdx[0]); printReg(ss, _srcRegIdx[0]);
} if (_numSrcRegs > 1) {
if(_numSrcRegs > 1)
{
ss << ","; ss << ",";
printReg(ss, _srcRegIdx[1]); printReg(ss, _srcRegIdx[1]);
} }
// just print the first dest... if there's a second one, // just print the first dest... if there's a second one,
// it's generally implicit // it's generally implicit
if(_numDestRegs > 0) if (_numDestRegs > 0) {
{
if (_numSrcRegs > 0) if (_numSrcRegs > 0)
ss << ","; ss << ",";
printReg(ss, _destRegIdx[0]); printReg(ss, _destRegIdx[0]);
@ -467,14 +464,14 @@ output decoder {{
return ss.str(); return ss.str();
} }
bool passesFpCondition(uint32_t fcc, uint32_t condition) bool
passesFpCondition(uint32_t fcc, uint32_t condition)
{ {
bool u = (fcc == 3); bool u = (fcc == 3);
bool g = (fcc == 2); bool g = (fcc == 2);
bool l = (fcc == 1); bool l = (fcc == 1);
bool e = (fcc == 0); bool e = (fcc == 0);
switch(condition) switch (condition) {
{
case FAlways: case FAlways:
return 1; return 1;
case FNever: case FNever:
@ -512,7 +509,8 @@ output decoder {{
"condition code %d", condition); "condition code %d", condition);
} }
bool passesCondition(uint32_t codes, uint32_t condition) bool
passesCondition(uint32_t codes, uint32_t condition)
{ {
CondCodes condCodes; CondCodes condCodes;
condCodes.bits = 0; condCodes.bits = 0;
@ -521,8 +519,7 @@ output decoder {{
condCodes.z = codes & 0x4 ? 1 : 0; condCodes.z = codes & 0x4 ? 1 : 0;
condCodes.n = codes & 0x8 ? 1 : 0; condCodes.n = codes & 0x8 ? 1 : 0;
switch(condition) switch (condition) {
{
case Always: case Always:
return true; return true;
case Never: case Never:
@ -567,17 +564,20 @@ output exec {{
/// @retval Full-system mode: NoFault if FP is enabled, FpDisabled /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
/// if not. Non-full-system mode: always returns NoFault. /// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM #if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
Fault fault = NoFault; // dummy... this ipr access should not fault Fault fault = NoFault; // dummy... this ipr access should not fault
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault; return NoFault;
else } else {
return new FpDisabled; return new FpDisabled;
} }
}
#else #else
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
return NoFault; return NoFault;
} }

121
src/arch/sparc/isa/decoder.isa
View file

@ -184,29 +184,34 @@ decode OP default Unknown::unknown()
}}); }});
0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
0x0D: udivx({{ 0x0D: udivx({{
if(Rs2_or_imm13 == 0) fault = new DivisionByZero; if (Rs2_or_imm13 == 0)
else Rd.udw = Rs1.udw / Rs2_or_imm13; fault = new DivisionByZero;
else
Rd.udw = Rs1.udw / Rs2_or_imm13;
}}); }});
0x0E: udiv({{ 0x0E: udiv({{
if(Rs2_or_imm13 == 0) fault = new DivisionByZero; if (Rs2_or_imm13 == 0) {
else fault = new DivisionByZero;
{ } else {
Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
if (Rd.udw >> 32 != 0) if (Rd.udw >> 32 != 0)
Rd.udw = 0xFFFFFFFF; Rd.udw = 0xFFFFFFFF;
} }
}}); }});
0x0F: sdiv({{ 0x0F: sdiv({{
if(Rs2_or_imm13.sdw == 0) if (Rs2_or_imm13.sdw == 0) {
fault = new DivisionByZero; fault = new DivisionByZero;
else } else {
{ Rd.udw = ((int64_t)((Y << 32) |
Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) if ((int64_t)Rd.udw >=
std::numeric_limits<int32_t>::max()) {
Rd.udw = 0x7FFFFFFF; Rd.udw = 0x7FFFFFFF;
else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) } else if ((int64_t)Rd.udw <=
std::numeric_limits<int32_t>::min()) {
Rd.udw = ULL(0xFFFFFFFF80000000); Rd.udw = ULL(0xFFFFFFFF80000000);
} }
}
}}); }});
} }
format IntOpCc { format IntOpCc {
@ -241,32 +246,38 @@ decode OP default Unknown::unknown()
Rd = res = op1 - op2 - Ccr<0:>; Rd = res = op1 - op2 - Ccr<0:>;
}}, sub=True); }}, sub=True);
0x1D: IntOpCcRes::udivxcc({{ 0x1D: IntOpCcRes::udivxcc({{
if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; if (Rs2_or_imm13.udw == 0)
else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); fault = new DivisionByZero;
else
Rd = Rs1.udw / Rs2_or_imm13.udw;}});
0x1E: IntOpCcRes::udivcc({{ 0x1E: IntOpCcRes::udivcc({{
uint64_t resTemp; uint64_t resTemp;
uint32_t val2 = Rs2_or_imm13.udw; uint32_t val2 = Rs2_or_imm13.udw;
int32_t overflow = 0; int32_t overflow = 0;
if(val2 == 0) fault = new DivisionByZero; if (val2 == 0) {
else fault = new DivisionByZero;
{ } else {
resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
overflow = (resTemp<63:32> != 0); overflow = (resTemp<63:32> != 0);
if(overflow) Rd = resTemp = 0xFFFFFFFF; if (overflow)
else Rd = resTemp; Rd = resTemp = 0xFFFFFFFF;
else
Rd = resTemp;
} }
}}, iv={{overflow}}); }}, iv={{overflow}});
0x1F: IntOpCcRes::sdivcc({{ 0x1F: IntOpCcRes::sdivcc({{
int64_t val2 = Rs2_or_imm13.sdw<31:0>; int64_t val2 = Rs2_or_imm13.sdw<31:0>;
bool overflow = false, underflow = false; bool overflow = false, underflow = false;
if(val2 == 0) fault = new DivisionByZero; if (val2 == 0) {
else fault = new DivisionByZero;
{ } else {
Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
if(overflow) Rd = 0x7FFFFFFF; if (overflow)
else if(underflow) Rd = ULL(0xFFFFFFFF80000000); Rd = 0x7FFFFFFF;
else if (underflow)
Rd = ULL(0xFFFFFFFF80000000);
} }
}}, iv={{overflow || underflow}}); }}, iv={{overflow || underflow}});
0x20: taddcc({{ 0x20: taddcc({{
@ -288,14 +299,16 @@ decode OP default Unknown::unknown()
Rd = res = op1 + op2; Rd = res = op1 + op2;
bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
findOverflow(32, res, op1, op2); findOverflow(32, res, op1, op2);
if(overflow) fault = new TagOverflow; if (overflow)
fault = new TagOverflow;
}}, iv={{overflow}}); }}, iv={{overflow}});
0x23: tsubcctv({{ 0x23: tsubcctv({{
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
Rd = res = op1 - op2; Rd = res = op1 - op2;
bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
findOverflow(32, res, op1, ~op2); findOverflow(32, res, op1, ~op2);
if(overflow) fault = new TagOverflow; if (overflow)
fault = new TagOverflow;
}}, iv={{overflow}}, sub=True); }}, iv={{overflow}}, sub=True);
0x24: mulscc({{ 0x24: mulscc({{
int32_t savedLSB = Rs1<0:>; int32_t savedLSB = Rs1<0:>;
@ -405,8 +418,7 @@ decode OP default Unknown::unknown()
// 0x11-0x1F should cause an illegal instruction exception // 0x11-0x1F should cause an illegal instruction exception
} }
0x2B: BasicOperate::flushw({{ 0x2B: BasicOperate::flushw({{
if(NWindows - 2 - Cansave != 0) if (NWindows - 2 - Cansave != 0) {
{
if (Otherwin) if (Otherwin)
fault = new SpillNOther(4*Wstate<5:3>); fault = new SpillNOther(4*Wstate<5:3>);
else else
@ -459,8 +471,10 @@ decode OP default Unknown::unknown()
} }
} }
0x2D: sdivx({{ 0x2D: sdivx({{
if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; if (Rs2_or_imm13.sdw == 0)
else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; fault = new DivisionByZero;
else
Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
}}); }});
0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
0x2F: decode RCOND3 0x2F: decode RCOND3
@ -907,10 +921,9 @@ decode OP default Unknown::unknown()
// because they're the most likely to be used, and // because they're the most likely to be used, and
// second because otherwise, we end up shifting by // second because otherwise, we end up shifting by
// greater than the width of the type being shifted, // greater than the width of the type being shifted,
//namely 64, which produces undefined results according // namely 64, which produces undefined results
//to the C standard. // according to the C standard.
switch(Gsr<2:0>) switch (Gsr<2:0>) {
{
case 0: case 0:
Frd.udw = msbX; Frd.udw = msbX;
break; break;
@ -1002,10 +1015,9 @@ decode OP default Unknown::unknown()
} }
0x38: Branch::jmpl({{ 0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13; Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3) if (target & 0x3) {
fault = new MemAddressNotAligned; fault = new MemAddressNotAligned;
else } else {
{
SparcISA::PCState pc = PCS; SparcISA::PCState pc = PCS;
if (Pstate<3:>) if (Pstate<3:>)
Rd = (pc.pc())<31:0>; Rd = (pc.pc())<31:0>;
@ -1017,22 +1029,17 @@ decode OP default Unknown::unknown()
}}); }});
0x39: Branch::return({{ 0x39: Branch::return({{
Addr target = Rs1 + Rs2_or_imm13; Addr target = Rs1 + Rs2_or_imm13;
if(fault == NoFault) if (fault == NoFault) {
{
// Check for fills which are higher priority than alignment // Check for fills which are higher priority than alignment
// faults. // faults.
if(Canrestore == 0) if (Canrestore == 0) {
{
if (Otherwin) if (Otherwin)
fault = new FillNOther(4*Wstate<5:3>); fault = new FillNOther(4*Wstate<5:3>);
else else
fault = new FillNNormal(4*Wstate<2:0>); fault = new FillNNormal(4*Wstate<2:0>);
} } else if (target & 0x3) { // Check for alignment faults
//Check for alignment faults
else if(target & 0x3)
fault = new MemAddressNotAligned; fault = new MemAddressNotAligned;
else } else {
{
SparcISA::PCState pc = PCS; SparcISA::PCState pc = PCS;
pc.nnpc(target); pc.nnpc(target);
PCS = pc; PCS = pc;
@ -1045,16 +1052,14 @@ decode OP default Unknown::unknown()
0x3A: decode CC 0x3A: decode CC
{ {
0x0: Trap::tcci({{ 0x0: Trap::tcci({{
if(passesCondition(Ccr<3:0>, COND2)) if (passesCondition(Ccr<3:0>, COND2)) {
{
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
fault = new TrapInstruction(lTrapNum); fault = new TrapInstruction(lTrapNum);
} }
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall); }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
0x2: Trap::tccx({{ 0x2: Trap::tccx({{
if(passesCondition(Ccr<7:4>, COND2)) if (passesCondition(Ccr<7:4>, COND2)) {
{
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
fault = new TrapInstruction(lTrapNum); fault = new TrapInstruction(lTrapNum);
@ -1064,19 +1069,14 @@ decode OP default Unknown::unknown()
0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
MemWriteOp); MemWriteOp);
0x3C: save({{ 0x3C: save({{
if(Cansave == 0) if (Cansave == 0) {
{
if (Otherwin) if (Otherwin)
fault = new SpillNOther(4*Wstate<5:3>); fault = new SpillNOther(4*Wstate<5:3>);
else else
fault = new SpillNNormal(4*Wstate<2:0>); fault = new SpillNNormal(4*Wstate<2:0>);
} } else if (Cleanwin - Canrestore == 0) {
else if(Cleanwin - Canrestore == 0)
{
fault = new CleanWindow; fault = new CleanWindow;
} } else {
else
{
Cwp = (Cwp + 1) % NWindows; Cwp = (Cwp + 1) % NWindows;
Rd_next = Rs1 + Rs2_or_imm13; Rd_next = Rs1 + Rs2_or_imm13;
Cansave = Cansave - 1; Cansave = Cansave - 1;
@ -1084,15 +1084,12 @@ decode OP default Unknown::unknown()
} }
}}); }});
0x3D: restore({{ 0x3D: restore({{
if(Canrestore == 0) if (Canrestore == 0) {
{
if (Otherwin) if (Otherwin)
fault = new FillNOther(4*Wstate<5:3>); fault = new FillNOther(4*Wstate<5:3>);
else else
fault = new FillNNormal(4*Wstate<2:0>); fault = new FillNNormal(4*Wstate<2:0>);
} } else {
else
{
Cwp = (Cwp - 1 + NWindows) % NWindows; Cwp = (Cwp - 1 + NWindows) % NWindows;
Rd_prev = Rs1 + Rs2_or_imm13; Rd_prev = Rs1 + Rs2_or_imm13;
Cansave = Cansave + 1; Cansave = Cansave + 1;

9
src/arch/sparc/isa/formats/basic.isa
View file

@ -35,7 +35,8 @@ def template BasicExecDeclare {{
// Definitions of execute methods that panic. // Definitions of execute methods that panic.
def template BasicExecPanic {{ def template BasicExecPanic {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const Fault
execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{ {
panic("Execute method called when it shouldn't!"); panic("Execute method called when it shouldn't!");
M5_DUMMY_RETURN M5_DUMMY_RETURN
@ -91,7 +92,8 @@ def template BasicConstructorWithMnemonic {{
// Basic instruction class execute method template. // Basic instruction class execute method template.
def template BasicExecute {{ def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Fault
%(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
@ -101,8 +103,7 @@ def template BasicExecute {{
%(op_rd)s; %(op_rd)s;
%(code)s; %(code)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(op_wb)s; %(op_wb)s;
} }
return fault; return fault;

23
src/arch/sparc/isa/formats/branch.isa
View file

@ -127,8 +127,8 @@ output decoder {{
template class BranchNBits<30>; template class BranchNBits<30>;
std::string Branch::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -141,7 +141,8 @@ output decoder {{
return response.str(); return response.str();
} }
std::string BranchImm13::generateDisassembly(Addr pc, std::string
BranchImm13::generateDisassembly(Addr pc,
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -158,7 +159,8 @@ output decoder {{
return response.str(); return response.str();
} }
std::string BranchDisp::generateDisassembly(Addr pc, std::string
BranchDisp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -170,8 +172,8 @@ output decoder {{
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
ccprintf(response, "0x%x", target); ccprintf(response, "0x%x", target);
if(symtab && symtab->findNearestSymbol(target, symbol, symbolAddr)) if (symtab &&
{ symtab->findNearestSymbol(target, symbol, symbolAddr)) {
ccprintf(response, " <%s", symbol); ccprintf(response, " <%s", symbol);
if (symbolAddr != target) if (symbolAddr != target)
ccprintf(response, "+%d>", target - symbolAddr); ccprintf(response, "+%d>", target - symbolAddr);
@ -196,8 +198,7 @@ def template JumpExecute {{
PCS = PCS; PCS = PCS;
%(code)s; %(code)s;
if(fault == NoFault) if (fault == NoFault) {
{
// Write the resulting state to the execution context // Write the resulting state to the execution context
%(op_wb)s; %(op_wb)s;
} }
@ -207,7 +208,8 @@ def template JumpExecute {{
}}; }};
def template BranchExecute {{ def template BranchExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Fault
%(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
// Attempt to execute the instruction // Attempt to execute the instruction
@ -222,8 +224,7 @@ def template BranchExecute {{
%(fail)s; %(fail)s;
} }
if(fault == NoFault) if (fault == NoFault) {
{
// Write the resulting state to the execution context // Write the resulting state to the execution context
%(op_wb)s; %(op_wb)s;
} }

38
src/arch/sparc/isa/formats/integerop.isa
View file

@ -151,11 +151,11 @@ def template SetHiDecode {{
output decoder {{ output decoder {{
bool IntOp::printPseudoOps(std::ostream &os, Addr pc, bool
IntOp::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const const SymbolTable *symbab) const
{ {
if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) {
{
printMnemonic(os, "mov"); printMnemonic(os, "mov");
printSrcReg(os, 1); printSrcReg(os, 1);
ccprintf(os, ", "); ccprintf(os, ", ");
@ -165,25 +165,21 @@ output decoder {{
return false; return false;
} }
bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, bool
IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const const SymbolTable *symbab) const
{ {
if(!std::strcmp(mnemonic, "or")) if (!std::strcmp(mnemonic, "or")) {
{ if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) {
if(_numSrcRegs > 0 && _srcRegIdx[0] == 0) if (imm == 0) {
{
if(imm == 0)
printMnemonic(os, "clr"); printMnemonic(os, "clr");
else } else {
{
printMnemonic(os, "mov"); printMnemonic(os, "mov");
ccprintf(os, " 0x%x, ", imm); ccprintf(os, " 0x%x, ", imm);
} }
printDestReg(os, 0); printDestReg(os, 0);
return true; return true;
} } else if (imm == 0) {
else if(imm == 0)
{
printMnemonic(os, "mov"); printMnemonic(os, "mov");
printSrcReg(os, 0); printSrcReg(os, 0);
ccprintf(os, ", "); ccprintf(os, ", ");
@ -194,8 +190,8 @@ output decoder {{
return false; return false;
} }
std::string IntOp::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -209,7 +205,8 @@ output decoder {{
return response.str(); return response.str();
} }
std::string IntOpImm::generateDisassembly(Addr pc, std::string
IntOpImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -227,8 +224,8 @@ output decoder {{
return response.str(); return response.str();
} }
std::string SetHi::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -250,8 +247,7 @@ def template IntOpExecute {{
%(code)s; %(code)s;
// Write the resulting state to the execution context // Write the resulting state to the execution context
if(fault == NoFault) if (fault == NoFault) {
{
%(cc_code)s; %(cc_code)s;
%(op_wb)s; %(op_wb)s;
} }

12
src/arch/sparc/isa/formats/mem/blockmem.isa
View file

@ -100,8 +100,7 @@ output decoder {{
bool save = flags[IsStore]; bool save = flags[IsStore];
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if(save) if (save) {
{
printReg(response, _srcRegIdx[0]); printReg(response, _srcRegIdx[0]);
ccprintf(response, ", "); ccprintf(response, ", ");
} }
@ -110,8 +109,7 @@ output decoder {{
ccprintf(response, " + "); ccprintf(response, " + ");
printReg(response, _srcRegIdx[!save ? 1 : 2]); printReg(response, _srcRegIdx[!save ? 1 : 2]);
ccprintf(response, " ]"); ccprintf(response, " ]");
if(load) if (load) {
{
ccprintf(response, ", "); ccprintf(response, ", ");
printReg(response, _destRegIdx[0]); printReg(response, _destRegIdx[0]);
} }
@ -127,8 +125,7 @@ output decoder {{
bool save = flags[IsStore]; bool save = flags[IsStore];
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if(save) if (save) {
{
printReg(response, _srcRegIdx[1]); printReg(response, _srcRegIdx[1]);
ccprintf(response, ", "); ccprintf(response, ", ");
} }
@ -138,8 +135,7 @@ output decoder {{
ccprintf(response, " + 0x%x ]", imm); ccprintf(response, " + 0x%x ]", imm);
else else
ccprintf(response, " + -0x%x ]", -imm); ccprintf(response, " + -0x%x ]", -imm);
if(load) if (load) {
{
ccprintf(response, ", "); ccprintf(response, ", ");
printReg(response, _destRegIdx[0]); printReg(response, _destRegIdx[0]);
} }

24
src/arch/sparc/isa/formats/mem/swap.isa
View file

@ -45,23 +45,19 @@ def template SwapExecute {{
%(ea_code)s; %(ea_code)s;
DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
%(fault_check)s; %(fault_check)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(code)s; %(code)s;
} }
if(storeCond && fault == NoFault) if (storeCond && fault == NoFault) {
{
%(EA_trunc)s %(EA_trunc)s
fault = xc->write((uint%(mem_acc_size)s_t)Mem, fault = xc->write((uint%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, &mem_data); EA, %(asi_val)s, &mem_data);
} }
if(fault == NoFault) if (fault == NoFault) {
{
// Handle the swapping // Handle the swapping
%(postacc_code)s; %(postacc_code)s;
} }
if(fault == NoFault) if (fault == NoFault) {
{
// Write the resulting state to the execution context // Write the resulting state to the execution context
%(op_wb)s; %(op_wb)s;
} }
@ -86,12 +82,10 @@ def template SwapInitiateAcc {{
DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
%(fault_check)s; %(fault_check)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(code)s; %(code)s;
} }
if(fault == NoFault) if (fault == NoFault) {
{
%(EA_trunc)s %(EA_trunc)s
fault = xc->write((uint%(mem_acc_size)s_t)Mem, fault = xc->write((uint%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, &mem_data); EA, %(asi_val)s, &mem_data);
@ -111,13 +105,11 @@ def template SwapCompleteAcc {{
uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>(); uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>();
if(fault == NoFault) if (fault == NoFault) {
{
// Handle the swapping // Handle the swapping
%(postacc_code)s; %(postacc_code)s;
} }
if(fault == NoFault) if (fault == NoFault) {
{
// Write the resulting state to the execution context // Write the resulting state to the execution context
%(op_wb)s; %(op_wb)s;
} }

54
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -79,21 +79,18 @@ output decoder {{
bool store = flags[IsStore]; bool store = flags[IsStore];
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if(store) if (store) {
{
printReg(response, _srcRegIdx[0]); printReg(response, _srcRegIdx[0]);
ccprintf(response, ", "); ccprintf(response, ", ");
} }
ccprintf(response, "["); ccprintf(response, "[");
if(_srcRegIdx[!store ? 0 : 1] != 0) if (_srcRegIdx[!store ? 0 : 1] != 0) {
{
printSrcReg(response, !store ? 0 : 1); printSrcReg(response, !store ? 0 : 1);
ccprintf(response, " + "); ccprintf(response, " + ");
} }
printSrcReg(response, !store ? 1 : 2); printSrcReg(response, !store ? 1 : 2);
ccprintf(response, "]"); ccprintf(response, "]");
if(load) if (load) {
{
ccprintf(response, ", "); ccprintf(response, ", ");
printReg(response, _destRegIdx[0]); printReg(response, _destRegIdx[0]);
} }
@ -109,14 +106,12 @@ output decoder {{
bool save = flags[IsStore]; bool save = flags[IsStore];
printMnemonic(response, mnemonic); printMnemonic(response, mnemonic);
if(save) if (save) {
{
printReg(response, _srcRegIdx[0]); printReg(response, _srcRegIdx[0]);
ccprintf(response, ", "); ccprintf(response, ", ");
} }
ccprintf(response, "["); ccprintf(response, "[");
if(_srcRegIdx[!save ? 0 : 1] != 0) if (_srcRegIdx[!save ? 0 : 1] != 0) {
{
printReg(response, _srcRegIdx[!save ? 0 : 1]); printReg(response, _srcRegIdx[!save ? 0 : 1]);
ccprintf(response, " + "); ccprintf(response, " + ");
} }
@ -124,8 +119,7 @@ output decoder {{
ccprintf(response, "0x%x]", imm); ccprintf(response, "0x%x]", imm);
else else
ccprintf(response, "-0x%x]", -imm); ccprintf(response, "-0x%x]", -imm);
if(load) if (load) {
{
ccprintf(response, ", "); ccprintf(response, ", ");
printReg(response, _destRegIdx[0]); printReg(response, _destRegIdx[0]);
} }
@ -147,17 +141,14 @@ def template LoadExecute {{
%(ea_code)s; %(ea_code)s;
DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
%(fault_check)s; %(fault_check)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(EA_trunc)s %(EA_trunc)s
fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
} }
if(fault == NoFault) if (fault == NoFault) {
{
%(code)s; %(code)s;
} }
if(fault == NoFault) if (fault == NoFault) {
{
// Write the resulting state to the execution context // Write the resulting state to the execution context
%(op_wb)s; %(op_wb)s;
} }
@ -178,8 +169,7 @@ def template LoadInitiateAcc {{
%(ea_code)s; %(ea_code)s;
DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
%(fault_check)s; %(fault_check)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(EA_trunc)s %(EA_trunc)s
fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
} }
@ -196,8 +186,7 @@ def template LoadCompleteAcc {{
%(op_rd)s; %(op_rd)s;
Mem = pkt->get<typeof(Mem)>(); Mem = pkt->get<typeof(Mem)>();
%(code)s; %(code)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(op_wb)s; %(op_wb)s;
} }
return fault; return fault;
@ -220,18 +209,15 @@ def template StoreExecute {{
%(ea_code)s; %(ea_code)s;
DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
%(fault_check)s; %(fault_check)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(code)s; %(code)s;
} }
if(storeCond && fault == NoFault) if (storeCond && fault == NoFault) {
{
%(EA_trunc)s %(EA_trunc)s
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0); EA, %(asi_val)s, 0);
} }
if(fault == NoFault) if (fault == NoFault) {
{
// Write the resulting state to the execution context // Write the resulting state to the execution context
%(op_wb)s; %(op_wb)s;
} }
@ -254,12 +240,10 @@ def template StoreInitiateAcc {{
%(ea_code)s; %(ea_code)s;
DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
%(fault_check)s; %(fault_check)s;
if(fault == NoFault) if (fault == NoFault) {
{
%(code)s; %(code)s;
} }
if(storeCond && fault == NoFault) if (storeCond && fault == NoFault) {
{
%(EA_trunc)s %(EA_trunc)s
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0); EA, %(asi_val)s, 0);
@ -310,10 +294,10 @@ let {{
# those that are only available in hpriv # those that are only available in hpriv
AlternateASIPrivFaultCheck = ''' AlternateASIPrivFaultCheck = '''
if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) && if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
!AsiIsUnPriv((ASI)EXT_ASI)) || !asiIsUnPriv((ASI)EXT_ASI)) ||
(!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))) (!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI)))
fault = new PrivilegedAction; fault = new PrivilegedAction;
else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
fault = new PrivilegedAction; fault = new PrivilegedAction;
''' '''

13
src/arch/sparc/isa/formats/micro.isa
View file

@ -28,7 +28,8 @@
// This delcares the initiateAcc function in memory operations // This delcares the initiateAcc function in memory operations
def template MacroInitiateAcc {{ def template MacroInitiateAcc {{
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const Fault
initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const
{ {
panic("Tried to execute a macroop directly!\n"); panic("Tried to execute a macroop directly!\n");
return NoFault; return NoFault;
@ -36,8 +37,8 @@ def template MacroInitiateAcc {{
}}; }};
def template MacroCompleteAcc {{ def template MacroCompleteAcc {{
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Fault
Trace::InstRecord *) const completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const
{ {
panic("Tried to execute a macroop directly!\n"); panic("Tried to execute a macroop directly!\n");
return NoFault; return NoFault;
@ -46,7 +47,8 @@ def template MacroCompleteAcc {{
// This template provides the execute functions for a store // This template provides the execute functions for a store
def template MacroExecute {{ def template MacroExecute {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const Fault
execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{ {
panic("Tried to execute a macroop directly!\n"); panic("Tried to execute a macroop directly!\n");
return NoFault; return NoFault;
@ -129,7 +131,8 @@ output header {{
output decoder {{ output decoder {{
std::string SparcMacroInst::generateDisassembly(Addr pc, std::string
SparcMacroInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;

18
src/arch/sparc/isa/formats/priv.isa
View file

@ -122,8 +122,8 @@ output header {{
}}; }};
output decoder {{ output decoder {{
std::string Priv::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -132,8 +132,8 @@ output decoder {{
return response.str(); return response.str();
} }
std::string RdPriv::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -145,8 +145,8 @@ output decoder {{
return response.str(); return response.str();
} }
std::string WrPriv::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -155,8 +155,7 @@ output decoder {{
ccprintf(response, " "); ccprintf(response, " ");
// If the first reg is %g0, don't print it. // If the first reg is %g0, don't print it.
// This improves readability // This improves readability
if(_srcRegIdx[0] != 0) if (_srcRegIdx[0] != 0) {
{
printSrcReg(response, 0); printSrcReg(response, 0);
ccprintf(response, ", "); ccprintf(response, ", ");
} }
@ -176,8 +175,7 @@ output decoder {{
ccprintf(response, " "); ccprintf(response, " ");
// If the first reg is %g0, don't print it. // If the first reg is %g0, don't print it.
// This improves readability // This improves readability
if(_srcRegIdx[0] != 0) if (_srcRegIdx[0] != 0) {
{
printSrcReg(response, 0); printSrcReg(response, 0);
ccprintf(response, ", "); ccprintf(response, ", ");
} }

14
src/arch/sparc/isa/formats/trap.isa
View file

@ -55,8 +55,8 @@ output header {{
}}; }};
output decoder {{ output decoder {{
std::string Trap::generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
std::stringstream response; std::stringstream response;
@ -71,7 +71,8 @@ output decoder {{
}}; }};
def template TrapExecute {{ def template TrapExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Fault
%(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
@ -83,7 +84,8 @@ def template TrapExecute {{
}}; }};
def template FpUnimplExecute {{ def template FpUnimplExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Fault
%(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
@ -113,8 +115,8 @@ output header {{
{ {
} }
std::string generateDisassembly(Addr pc, std::string
const SymbolTable *symtab) const generateDisassembly(Addr pc, const SymbolTable *symtab) const
{ {
return mnemonic; return mnemonic;
} }

9
src/arch/sparc/isa/operands.isa
View file

@ -48,17 +48,20 @@ output header {{
// A function to "decompress" double and quad floating point // A function to "decompress" double and quad floating point
// register numbers stuffed into 5 bit fields. These have their // register numbers stuffed into 5 bit fields. These have their
// MSB put in the LSB position but are otherwise normal. // MSB put in the LSB position but are otherwise normal.
static inline unsigned int dfpr(unsigned int regNum) static inline unsigned int
dfpr(unsigned int regNum)
{ {
return (regNum & (~1)) | ((regNum & 1) << 5); return (regNum & (~1)) | ((regNum & 1) << 5);
} }
static inline unsigned int dfprl(unsigned int regNum) static inline unsigned int
dfprl(unsigned int regNum)
{ {
return dfpr(regNum) & (~0x1); return dfpr(regNum) & (~0x1);
} }
static inline unsigned int dfprh(unsigned int regNum) static inline unsigned int
dfprh(unsigned int regNum)
{ {
return dfpr(regNum) | 0x1; return dfpr(regNum) | 0x1;
} }

6
src/arch/sparc/linux/process.cc
View file

@ -67,8 +67,7 @@ Sparc32LinuxProcess::Sparc32LinuxProcess(LiveProcessParams * params,
void Sparc32LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) void Sparc32LinuxProcess::handleTrap(int trapNum, ThreadContext *tc)
{ {
switch(trapNum) switch (trapNum) {
{
case 0x10: //Linux 32 bit syscall trap case 0x10: //Linux 32 bit syscall trap
tc->syscall(tc->readIntReg(1)); tc->syscall(tc->readIntReg(1));
break; break;
@ -84,8 +83,7 @@ Sparc64LinuxProcess::Sparc64LinuxProcess(LiveProcessParams * params,
void Sparc64LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) void Sparc64LinuxProcess::handleTrap(int trapNum, ThreadContext *tc)
{ {
switch(trapNum) switch (trapNum) {
{
// case 0x10: // Linux 32 bit syscall trap // case 0x10: // Linux 32 bit syscall trap
case 0x6d: // Linux 64 bit syscall trap case 0x6d: // Linux 64 bit syscall trap
tc->syscall(tc->readIntReg(1)); tc->syscall(tc->readIntReg(1));

6
src/arch/sparc/linux/process.hh
View file

@ -64,7 +64,8 @@ class Sparc32LinuxProcess : public SparcLinuxProcess, public Sparc32LiveProcess
/// Constructor. /// Constructor.
Sparc32LinuxProcess(LiveProcessParams * params, ObjectFile *objFile); Sparc32LinuxProcess(LiveProcessParams * params, ObjectFile *objFile);
SyscallDesc* getDesc(int callnum) SyscallDesc*
getDesc(int callnum)
{ {
return SparcLinuxProcess::getDesc32(callnum); return SparcLinuxProcess::getDesc32(callnum);
} }
@ -79,7 +80,8 @@ class Sparc64LinuxProcess : public SparcLinuxProcess, public Sparc64LiveProcess
/// Constructor. /// Constructor.
Sparc64LinuxProcess(LiveProcessParams * params, ObjectFile *objFile); Sparc64LinuxProcess(LiveProcessParams * params, ObjectFile *objFile);
SyscallDesc* getDesc(int callnum) SyscallDesc*
getDesc(int callnum)
{ {
return SparcLinuxProcess::getDesc(callnum); return SparcLinuxProcess::getDesc(callnum);
} }

13
src/arch/sparc/linux/syscalls.cc
View file

@ -56,8 +56,8 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
} }
SyscallReturn getresuidFunc(SyscallDesc *desc, int num, SyscallReturn
LiveProcess *p, ThreadContext *tc) getresuidFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
{ {
const IntReg id = htog(100); const IntReg id = htog(100);
int index = 0; int index = 0;
@ -66,22 +66,19 @@ SyscallReturn getresuidFunc(SyscallDesc *desc, int num,
Addr suid = p->getSyscallArg(tc, index); Addr suid = p->getSyscallArg(tc, index);
// Handle the EFAULT case // Handle the EFAULT case
// Set the ruid // Set the ruid
if(ruid) if (ruid) {
{
BufferArg ruidBuff(ruid, sizeof(IntReg)); BufferArg ruidBuff(ruid, sizeof(IntReg));
memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg)); memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
ruidBuff.copyOut(tc->getMemPort()); ruidBuff.copyOut(tc->getMemPort());
} }
// Set the euid // Set the euid
if(euid) if (euid) {
{
BufferArg euidBuff(euid, sizeof(IntReg)); BufferArg euidBuff(euid, sizeof(IntReg));
memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg)); memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
euidBuff.copyOut(tc->getMemPort()); euidBuff.copyOut(tc->getMemPort());
} }
// Set the suid // Set the suid
if(suid) if (suid) {
{
BufferArg suidBuff(suid, sizeof(IntReg)); BufferArg suidBuff(suid, sizeof(IntReg));
memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg)); memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
suidBuff.copyOut(tc->getMemPort()); suidBuff.copyOut(tc->getMemPort());

10
src/arch/sparc/miscregs.hh
View file

@ -115,7 +115,8 @@ namespace SparcISA
MISCREG_NUMMISCREGS MISCREG_NUMMISCREGS
}; };
struct HPSTATE { struct HPSTATE
{
const static uint64_t id = 0x800; // this impl. dependent (id) field m const static uint64_t id = 0x800; // this impl. dependent (id) field m
const static uint64_t ibe = 0x400; const static uint64_t ibe = 0x400;
const static uint64_t red = 0x20; const static uint64_t red = 0x20;
@ -124,7 +125,8 @@ namespace SparcISA
}; };
struct PSTATE { struct PSTATE
{
const static int cle = 0x200; const static int cle = 0x200;
const static int tle = 0x100; const static int tle = 0x100;
const static int mm = 0xC0; const static int mm = 0xC0;
@ -134,7 +136,8 @@ namespace SparcISA
const static int ie = 0x2; const static int ie = 0x2;
}; };
struct STS { struct STS
{
const static int st_idle = 0x00; const static int st_idle = 0x00;
const static int st_wait = 0x01; const static int st_wait = 0x01;
const static int st_halt = 0x02; const static int st_halt = 0x02;
@ -154,6 +157,7 @@ namespace SparcISA
const int NumMiscArchRegs = MISCREG_NUMMISCREGS; const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
const int NumMiscRegs = MISCREG_NUMMISCREGS; const int NumMiscRegs = MISCREG_NUMMISCREGS;
} }
#endif #endif

2
src/arch/sparc/mmaped_ipr.hh
View file

@ -45,6 +45,7 @@
namespace SparcISA namespace SparcISA
{ {
inline Tick inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt) handleIprRead(ThreadContext *xc, Packet *pkt)
{ {
@ -55,7 +56,6 @@ handleIprRead(ThreadContext *xc, Packet *pkt)
#endif #endif
} }
inline Tick inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt) handleIprWrite(ThreadContext *xc, Packet *pkt)
{ {

5
src/arch/sparc/pagetable.cc
View file

@ -33,6 +33,7 @@
namespace SparcISA namespace SparcISA
{ {
void void
TlbEntry::serialize(std::ostream &os) TlbEntry::serialize(std::ostream &os)
{ {
@ -67,8 +68,8 @@ TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
} }
int PageTableEntry::pageSizes[] = {8*1024, 64*1024, 0, 4*1024*1024, 0, int PageTableEntry::pageSizes[] =
256*1024*1024L}; { 8 * 1024, 64 * 1024, 0, 4 * 1024 * 1024, 0, 256 * 1024 * 1024L} ;
} }

10
src/arch/sparc/pagetable.hh
View file

@ -86,8 +86,7 @@ class PageTableEntry
bool populated; bool populated;
public: public:
PageTableEntry() PageTableEntry() : entry(0), type(invalid), populated(false)
: entry(0), type(invalid), populated(false)
{} {}
PageTableEntry(uint64_t e, EntryType t = sun4u) PageTableEntry(uint64_t e, EntryType t = sun4u)
@ -96,7 +95,8 @@ class PageTableEntry
populate(entry, type); populate(entry, type);
} }
void populate(uint64_t e, EntryType t = sun4u) void
populate(uint64_t e, EntryType t = sun4u)
{ {
entry = e; entry = e;
type = t; type = t;
@ -131,6 +131,7 @@ class PageTableEntry
static int pageSizes[6]; static int pageSizes[6];
uint64_t operator()() const { assert(populated); return entry4u; } uint64_t operator()() const { assert(populated); return entry4u; }
const PageTableEntry & const PageTableEntry &
operator=(uint64_t e) operator=(uint64_t e)
{ {
@ -261,7 +262,8 @@ struct TlbEntry
bool used; bool used;
bool valid; bool valid;
Addr pageStart() Addr
pageStart()
{ {
return pte.paddr(); return pte.paddr();
} }

32
src/arch/sparc/predecoder.hh
View file

@ -42,6 +42,7 @@ class ThreadContext;
namespace SparcISA namespace SparcISA
{ {
class Predecoder class Predecoder
{ {
protected: protected:
@ -53,53 +54,56 @@ namespace SparcISA
Predecoder(ThreadContext * _tc) : tc(_tc) Predecoder(ThreadContext * _tc) : tc(_tc)
{} {}
ThreadContext * getTC() ThreadContext *
getTC()
{ {
return tc; return tc;
} }
void setTC(ThreadContext * _tc) void
setTC(ThreadContext * _tc)
{ {
tc = _tc; tc = _tc;
} }
void process() void process() {}
{ void reset() {}
}
void reset()
{}
// Use this to give data to the predecoder. This should be used // Use this to give data to the predecoder. This should be used
// when there is control flow. // when there is control flow.
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) void
moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
{ {
emi = inst; emi = inst;
// The I bit, bit 13, is used to figure out where the ASI // The I bit, bit 13, is used to figure out where the ASI
// should come from. Use that in the ExtMachInst. This is // should come from. Use that in the ExtMachInst. This is
// slightly redundant, but it removes the need to put a condition // slightly redundant, but it removes the need to put a condition
// into all the execute functions // into all the execute functions
if(inst & (1 << 13)) if (inst & (1 << 13)) {
emi |= (static_cast<ExtMachInst>( emi |= (static_cast<ExtMachInst>(
tc->readMiscRegNoEffect(MISCREG_ASI)) tc->readMiscRegNoEffect(MISCREG_ASI))
<< (sizeof(MachInst) * 8)); << (sizeof(MachInst) * 8));
else } else {
emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5)) emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
<< (sizeof(MachInst) * 8)); << (sizeof(MachInst) * 8));
} }
}
bool needMoreBytes() bool
needMoreBytes()
{ {
return true; return true;
} }
bool extMachInstReady() bool
extMachInstReady()
{ {
return true; return true;
} }
// This returns a constant reference to the ExtMachInst to avoid a copy // This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst & getExtMachInst(PCState &pcState) const ExtMachInst &
getExtMachInst(PCState &pcState)
{ {
return emi; return emi;
} }

21
src/arch/sparc/process.cc
View file

@ -67,11 +67,11 @@ SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params,
spillStart = 0; spillStart = 0;
} }
void SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) void
SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc)
{ {
PCState pc = tc->pcState(); PCState pc = tc->pcState();
switch(trapNum) switch (trapNum) {
{
case 0x01: // Software breakpoint case 0x01: // Software breakpoint
warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); warn("Software breakpoint encountered at pc %#x.\n", pc.pc());
break; break;
@ -225,8 +225,7 @@ SparcLiveProcess::argsInit(int pageSize)
// Setup the auxilliary vectors. These will already have endian conversion. // Setup the auxilliary vectors. These will already have endian conversion.
// Auxilliary vectors are loaded only for elf formatted executables. // Auxilliary vectors are loaded only for elf formatted executables.
ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
if(elfObject) if (elfObject) {
{
// Bits which describe the system hardware capabilities // Bits which describe the system hardware capabilities
auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap));
// The system page size // The system page size
@ -363,8 +362,7 @@ SparcLiveProcess::argsInit(int pageSize)
initVirtMem->writeString(file_name_base, filename.c_str()); initVirtMem->writeString(file_name_base, filename.c_str());
// Copy the aux stuff // Copy the aux stuff
for(int x = 0; x < auxv.size(); x++) for (int x = 0; x < auxv.size(); x++) {
{
initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
(uint8_t*)&(auxv[x].a_type), intSize); (uint8_t*)&(auxv[x].a_type), intSize);
initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
@ -440,8 +438,7 @@ void Sparc32LiveProcess::flushWindows(ThreadContext *tc)
MiscReg CWP = tc->readMiscReg(MISCREG_CWP); MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
MiscReg origCWP = CWP; MiscReg origCWP = CWP;
CWP = (CWP + Cansave + 2) % NWindows; CWP = (CWP + Cansave + 2) % NWindows;
while(NWindows - 2 - Cansave != 0) while (NWindows - 2 - Cansave != 0) {
{
if (Otherwin) { if (Otherwin) {
panic("Otherwin non-zero.\n"); panic("Otherwin non-zero.\n");
} else { } else {
@ -467,7 +464,8 @@ void Sparc32LiveProcess::flushWindows(ThreadContext *tc)
tc->setMiscReg(MISCREG_CWP, origCWP); tc->setMiscReg(MISCREG_CWP, origCWP);
} }
void Sparc64LiveProcess::flushWindows(ThreadContext *tc) void
Sparc64LiveProcess::flushWindows(ThreadContext *tc)
{ {
IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
@ -475,8 +473,7 @@ void Sparc64LiveProcess::flushWindows(ThreadContext *tc)
MiscReg CWP = tc->readMiscReg(MISCREG_CWP); MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
MiscReg origCWP = CWP; MiscReg origCWP = CWP;
CWP = (CWP + Cansave + 2) % NWindows; CWP = (CWP + Cansave + 2) % NWindows;
while(NWindows - 2 - Cansave != 0) while (NWindows - 2 - Cansave != 0) {
{
if (Otherwin) { if (Otherwin) {
panic("Otherwin non-zero.\n"); panic("Otherwin non-zero.\n");
} else { } else {

7
src/arch/sparc/process.hh
View file

@ -62,11 +62,8 @@ class SparcLiveProcess : public LiveProcess
// Handles traps which request services from the operating system // Handles traps which request services from the operating system
virtual void handleTrap(int trapNum, ThreadContext *tc); virtual void handleTrap(int trapNum, ThreadContext *tc);
Addr readFillStart() Addr readFillStart() { return fillStart; }
{ return fillStart; } Addr readSpillStart() { return spillStart; }
Addr readSpillStart()
{ return spillStart; }
virtual void flushWindows(ThreadContext *tc) = 0; virtual void flushWindows(ThreadContext *tc) = 0;
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);

1
src/arch/sparc/registers.hh
View file

@ -39,6 +39,7 @@
namespace SparcISA namespace SparcISA
{ {
using SparcISAInst::MaxInstSrcRegs; using SparcISAInst::MaxInstSrcRegs;
using SparcISAInst::MaxInstDestRegs; using SparcISAInst::MaxInstDestRegs;

2
src/arch/sparc/remote_gdb.hh
View file

@ -44,6 +44,7 @@ class PhysicalMemory;
namespace SparcISA namespace SparcISA
{ {
class RemoteGDB : public BaseRemoteGDB class RemoteGDB : public BaseRemoteGDB
{ {
protected: protected:
@ -72,6 +73,7 @@ namespace SparcISA
Addr nextBkpt; Addr nextBkpt;
}; };
} }
#endif /* __ARCH_SPARC_REMOTE_GDB_H__ */ #endif /* __ARCH_SPARC_REMOTE_GDB_H__ */

6
src/arch/sparc/sparc_traits.hh
View file

@ -46,12 +46,10 @@ namespace SparcISA
// const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16; // const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
// const int NumMicroIntRegs = 1; // const int NumMicroIntRegs = 1;
// const int NumIntRegs = // const int NumIntRegs = NumRegularIntRegs + NumMicroIntRegs;
// NumRegularIntRegs +
// NumMicroIntRegs;
const int NumFloatRegs = 64; const int NumFloatRegs = 64;
const int NumFloatArchRegs = NumFloatRegs; const int NumFloatArchRegs = NumFloatRegs;
// const int NumMiscRegs = 40; // const int NumMiscRegs = 40;
} }
#endif // __ARCH_SPARC_ISA_TRAITS_HH__ #endif // __ARCH_SPARC_SPARC_TRAITS_HH__

5
src/arch/sparc/stacktrace.hh
View file

@ -39,13 +39,15 @@
class ThreadContext; class ThreadContext;
namespace SparcISA namespace SparcISA
{ {
class StackTrace class StackTrace
{ {
private: private:
std::vector<Addr> stack; std::vector<Addr> stack;
public: public:
bool trace(ThreadContext *tc, StaticInstPtr inst) bool
trace(ThreadContext *tc, StaticInstPtr inst)
{ {
panic("StackTrace::trace not implemented for SPARC.\n"); panic("StackTrace::trace not implemented for SPARC.\n");
return false; return false;
@ -56,6 +58,7 @@ namespace SparcISA
public: public:
void dprintf() {} void dprintf() {}
}; };
} }
#endif // __ARCH_SPARC_STACKTRACE_HH__ #endif // __ARCH_SPARC_STACKTRACE_HH__

12
src/arch/sparc/system.hh
View file

@ -111,26 +111,30 @@ class SparcSystem : public System
/** Add a function-based event to reset binary. */ /** Add a function-based event to reset binary. */
template <class T> template <class T>
T *addResetFuncEvent(const char *lbl) T *
addResetFuncEvent(const char *lbl)
{ {
return addFuncEvent<T>(resetSymtab, lbl); return addFuncEvent<T>(resetSymtab, lbl);
} }
/** Add a function-based event to the hypervisor. */ /** Add a function-based event to the hypervisor. */
template <class T> template <class T>
T *addHypervisorFuncEvent(const char *lbl) T *
addHypervisorFuncEvent(const char *lbl)
{ {
return addFuncEvent<T>(hypervisorSymtab, lbl); return addFuncEvent<T>(hypervisorSymtab, lbl);
} }
/** Add a function-based event to the openboot. */ /** Add a function-based event to the openboot. */
template <class T> template <class T>
T *addOpenbootFuncEvent(const char *lbl) T *
addOpenbootFuncEvent(const char *lbl)
{ {
return addFuncEvent<T>(openbootSymtab, lbl); return addFuncEvent<T>(openbootSymtab, lbl);
} }
virtual Addr fixFuncEventAddr(Addr addr) virtual Addr
fixFuncEventAddr(Addr addr)
{ {
//XXX This may eventually have to do something useful. //XXX This may eventually have to do something useful.
return addr; return addr;

62
src/arch/sparc/tlb.cc
View file

@ -131,21 +131,6 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
} }
} }
/*
i = lookupTable.find(tr);
if (i != lookupTable.end()) {
i->second->valid = false;
if (i->second->used) {
i->second->used = false;
usedEntries--;
}
freeList.push_front(i->second);
DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
i->second);
lookupTable.erase(i);
}
*/
if (entry != -1) { if (entry != -1) {
assert(entry < size && entry >= 0); assert(entry < size && entry >= 0);
new_entry = &tlb[entry]; new_entry = &tlb[entry];
@ -164,13 +149,6 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
lastReplaced = x; lastReplaced = x;
new_entry = &tlb[x]; new_entry = &tlb[x];
} }
/*
for (x = 0; x < size; x++) {
if (!tlb[x].valid || !tlb[x].used) {
new_entry = &tlb[x];
break;
}
}*/
} }
insertAllLocked: insertAllLocked:
@ -642,24 +620,24 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
} }
} else { } else {
// We need to check for priv level/asi priv // We need to check for priv level/asi priv
if (!priv && !hpriv && !AsiIsUnPriv(asi)) { if (!priv && !hpriv && !asiIsUnPriv(asi)) {
// It appears that context should be Nucleus in these cases? // It appears that context should be Nucleus in these cases?
writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
return new PrivilegedAction; return new PrivilegedAction;
} }
if (!hpriv && AsiIsHPriv(asi)) { if (!hpriv && asiIsHPriv(asi)) {
writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
return new DataAccessException; return new DataAccessException;
} }
if (AsiIsPrimary(asi)) { if (asiIsPrimary(asi)) {
context = pri_context; context = pri_context;
ct = Primary; ct = Primary;
} else if (AsiIsSecondary(asi)) { } else if (asiIsSecondary(asi)) {
context = sec_context; context = sec_context;
ct = Secondary; ct = Secondary;
} else if (AsiIsNucleus(asi)) { } else if (asiIsNucleus(asi)) {
ct = Nucleus; ct = Nucleus;
context = 0; context = 0;
} else { // ???? } else { // ????
@ -669,34 +647,34 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
} }
if (!implicit && asi != ASI_P && asi != ASI_S) { if (!implicit && asi != ASI_P && asi != ASI_S) {
if (AsiIsLittle(asi)) if (asiIsLittle(asi))
panic("Little Endian ASIs not supported\n"); panic("Little Endian ASIs not supported\n");
//XXX It's unclear from looking at the documentation how a no fault //XXX It's unclear from looking at the documentation how a no fault
// load differs from a regular one, other than what happens concerning // load differs from a regular one, other than what happens concerning
// nfo and e bits in the TTE // nfo and e bits in the TTE
// if (AsiIsNoFault(asi)) // if (asiIsNoFault(asi))
// panic("No Fault ASIs not supported\n"); // panic("No Fault ASIs not supported\n");
if (AsiIsPartialStore(asi)) if (asiIsPartialStore(asi))
panic("Partial Store ASIs not supported\n"); panic("Partial Store ASIs not supported\n");
if (AsiIsCmt(asi)) if (asiIsCmt(asi))
panic("Cmt ASI registers not implmented\n"); panic("Cmt ASI registers not implmented\n");
if (AsiIsInterrupt(asi)) if (asiIsInterrupt(asi))
goto handleIntRegAccess; goto handleIntRegAccess;
if (AsiIsMmu(asi)) if (asiIsMmu(asi))
goto handleMmuRegAccess; goto handleMmuRegAccess;
if (AsiIsScratchPad(asi)) if (asiIsScratchPad(asi))
goto handleScratchRegAccess; goto handleScratchRegAccess;
if (AsiIsQueue(asi)) if (asiIsQueue(asi))
goto handleQueueRegAccess; goto handleQueueRegAccess;
if (AsiIsSparcError(asi)) if (asiIsSparcError(asi))
goto handleSparcErrorRegAccess; goto handleSparcErrorRegAccess;
if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
!AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
panic("Accessing ASI %#X. Should we?\n", asi); panic("Accessing ASI %#X. Should we?\n", asi);
} }
@ -714,12 +692,12 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
return new DataAccessException; return new DataAccessException;
} }
if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
real = true; real = true;
context = 0; context = 0;
} }
if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
req->setPaddr(vaddr & PAddrImplMask); req->setPaddr(vaddr & PAddrImplMask);
return NoFault; return NoFault;
} }
@ -752,13 +730,13 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
return new FastDataAccessProtection; return new FastDataAccessProtection;
} }
if (e->pte.nofault() && !AsiIsNoFault(asi)) { if (e->pte.nofault() && !asiIsNoFault(asi)) {
writeTagAccess(vaddr, context); writeTagAccess(vaddr, context);
writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
return new DataAccessException; return new DataAccessException;
} }
if (e->pte.sideffect() && AsiIsNoFault(asi)) { if (e->pte.sideffect() && asiIsNoFault(asi)) {
writeTagAccess(vaddr, context); writeTagAccess(vaddr, context);
writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
return new DataAccessException; return new DataAccessException;

3
src/arch/sparc/tlb.hh
View file

@ -156,7 +156,8 @@ class TLB : public BaseTLB
typedef SparcTLBParams Params; typedef SparcTLBParams Params;
TLB(const Params *p); TLB(const Params *p);
void demapPage(Addr vaddr, uint64_t asn) void
demapPage(Addr vaddr, uint64_t asn)
{ {
panic("demapPage(Addr) is not implemented.\n"); panic("demapPage(Addr) is not implemented.\n");
} }

36
src/arch/sparc/tlb_map.hh
View file

@ -46,7 +46,8 @@ class TlbMap
public: public:
typedef RangeMap::iterator iterator; typedef RangeMap::iterator iterator;
iterator find(const TlbRange &r) iterator
find(const TlbRange &r)
{ {
iterator i; iterator i;
@ -79,7 +80,8 @@ class TlbMap
return tree.end(); return tree.end();
} }
bool intersect(const TlbRange &r) bool
intersect(const TlbRange &r)
{ {
iterator i; iterator i;
i = find(r); i = find(r);
@ -89,7 +91,8 @@ class TlbMap
} }
iterator insert(TlbRange &r, TlbEntry *d) iterator
insert(TlbRange &r, TlbEntry *d)
{ {
if (intersect(r)) if (intersect(r))
return tree.end(); return tree.end();
@ -97,47 +100,56 @@ class TlbMap
return tree.insert(std::make_pair<TlbRange,TlbEntry*>(r, d)).first; return tree.insert(std::make_pair<TlbRange,TlbEntry*>(r, d)).first;
} }
size_t erase(TlbRange k) size_t
erase(TlbRange k)
{ {
return tree.erase(k); return tree.erase(k);
} }
void erase(iterator p) void
erase(iterator p)
{ {
tree.erase(p); tree.erase(p);
} }
void erase(iterator p, iterator q) void
erase(iterator p, iterator q)
{ {
tree.erase(p,q); tree.erase(p,q);
} }
void clear() void
clear()
{ {
tree.erase(tree.begin(), tree.end()); tree.erase(tree.begin(), tree.end());
} }
iterator begin() iterator
begin()
{ {
return tree.begin(); return tree.begin();
} }
iterator end() iterator
end()
{ {
return tree.end(); return tree.end();
} }
size_t size() size_t
size()
{ {
return tree.size(); return tree.size();
} }
bool empty() bool
empty()
{ {
return tree.empty(); return tree.empty();
} }
void print() void
print()
{ {
iterator i; iterator i;
i = tree.begin(); i = tree.begin();

5
src/arch/sparc/types.hh
View file

@ -37,6 +37,7 @@
namespace SparcISA namespace SparcISA
{ {
typedef uint32_t MachInst; typedef uint32_t MachInst;
typedef uint64_t ExtMachInst; typedef uint64_t ExtMachInst;
@ -44,9 +45,11 @@ namespace SparcISA
typedef Twin64_t LargestRead; typedef Twin64_t LargestRead;
struct CoreSpecific { struct CoreSpecific
{
int core_type; int core_type;
}; };
} }
#endif #endif

6
src/arch/sparc/ua2005.cc
View file

@ -334,9 +334,10 @@ ISA::processSTickCompare(ThreadContext *tc)
if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
} }
} else } else {
cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
} }
}
void void
ISA::processHSTickCompare(ThreadContext *tc) ISA::processHSTickCompare(ThreadContext *tc)
@ -361,7 +362,8 @@ ISA::processHSTickCompare(ThreadContext *tc)
setMiscReg(MISCREG_HINTP, 1, tc); setMiscReg(MISCREG_HINTP, 1, tc);
} }
// Need to do something to cause interrupt to happen here !!! @todo // Need to do something to cause interrupt to happen here !!! @todo
} else } else {
cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1)); cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
} }
}

84
src/arch/sparc/utility.cc
View file

@ -72,15 +72,18 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
// Read all the trap level dependent registers and save them off // Read all the trap level dependent registers and save them off
for(int i = 1; i <= MaxTL; i++) for (int i = 1; i <= MaxTL; i++) {
{
src->setMiscRegNoEffect(MISCREG_TL, i); src->setMiscRegNoEffect(MISCREG_TL, i);
dest->setMiscRegNoEffect(MISCREG_TL, i); dest->setMiscRegNoEffect(MISCREG_TL, i);
dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); dest->setMiscRegNoEffect(MISCREG_TT,
dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); src->readMiscRegNoEffect(MISCREG_TT));
dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); dest->setMiscRegNoEffect(MISCREG_TPC,
dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); src->readMiscRegNoEffect(MISCREG_TPC));
dest->setMiscRegNoEffect(MISCREG_TNPC,
src->readMiscRegNoEffect(MISCREG_TNPC));
dest->setMiscRegNoEffect(MISCREG_TSTATE,
src->readMiscRegNoEffect(MISCREG_TSTATE));
} }
// Save off the traplevel // Save off the traplevel
@ -89,40 +92,63 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
// ASRs // ASRs
// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); // dest->setMiscRegNoEffect(MISCREG_Y,
// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); // src->readMiscRegNoEffect(MISCREG_Y));
dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); // dest->setMiscRegNoEffect(MISCREG_CCR,
dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); // src->readMiscRegNoEffect(MISCREG_CCR));
dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); dest->setMiscRegNoEffect(MISCREG_ASI,
dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); src->readMiscRegNoEffect(MISCREG_ASI));
dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); dest->setMiscRegNoEffect(MISCREG_TICK,
dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); src->readMiscRegNoEffect(MISCREG_TICK));
dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); dest->setMiscRegNoEffect(MISCREG_FPRS,
src->readMiscRegNoEffect(MISCREG_FPRS));
dest->setMiscRegNoEffect(MISCREG_SOFTINT,
src->readMiscRegNoEffect(MISCREG_SOFTINT));
dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
dest->setMiscRegNoEffect(MISCREG_STICK,
src->readMiscRegNoEffect(MISCREG_STICK));
dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
// Priv Registers // Priv Registers
dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); dest->setMiscRegNoEffect(MISCREG_TICK,
dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); src->readMiscRegNoEffect(MISCREG_TICK));
dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); dest->setMiscRegNoEffect(MISCREG_TBA,
dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); src->readMiscRegNoEffect(MISCREG_TBA));
dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); dest->setMiscRegNoEffect(MISCREG_PSTATE,
// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); src->readMiscRegNoEffect(MISCREG_PSTATE));
// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); dest->setMiscRegNoEffect(MISCREG_PIL,
// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); src->readMiscRegNoEffect(MISCREG_PIL));
// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); dest->setMiscReg(MISCREG_CWP,
// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); src->readMiscRegNoEffect(MISCREG_CWP));
// dest->setMiscRegNoEffect(MISCREG_CANSAVE,
// src->readMiscRegNoEffect(MISCREG_CANSAVE));
// dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
// src->readMiscRegNoEffect(MISCREG_CANRESTORE));
// dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
// src->readMiscRegNoEffect(MISCREG_OTHERWIN));
// dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
// src->readMiscRegNoEffect(MISCREG_CLEANWIN));
// dest->setMiscRegNoEffect(MISCREG_WSTATE,
// src->readMiscRegNoEffect(MISCREG_WSTATE));
dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
// Hyperprivilged registers // Hyperprivilged registers
dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); dest->setMiscRegNoEffect(MISCREG_HPSTATE,
dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); src->readMiscRegNoEffect(MISCREG_HPSTATE));
dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); dest->setMiscRegNoEffect(MISCREG_HINTP,
src->readMiscRegNoEffect(MISCREG_HINTP));
dest->setMiscRegNoEffect(MISCREG_HTBA,
src->readMiscRegNoEffect(MISCREG_HTBA));
dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
// FSR // FSR
dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); dest->setMiscRegNoEffect(MISCREG_FSR,
src->readMiscRegNoEffect(MISCREG_FSR));
// Strand Status Register // Strand Status Register
dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,

3
src/arch/sparc/utility.hh
View file

@ -52,8 +52,7 @@ namespace SparcISA
return ret; return ret;
} }
uint64_t uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
static inline bool static inline bool
inUserMode(ThreadContext *tc) inUserMode(ThreadContext *tc)